llvm.org GIT mirror llvm / f7da2c7
Take advantage of the recent improvements to the liveintervals set (tracking instructions which define each value#) to simplify and improve the coallescer. In particular, this patch: 1. Implements iterative coallescing. 2. Reverts an unsafe hack from handlePhysRegDef, superceeding it with a better solution. 3. Implements PR865, "coallescing" away the second copy in code like: A = B ... B = A This also includes changes to symbolically print registers in intervals when possible. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29862 91177308-0d34-0410-b5e6-96231b3b80d8 Chris Lattner 13 years ago
5 changed file(s) with 407 addition(s) and 253 deletion(s). Raw diff Collapse all Expand all
8181
8282 /// InstDefiningValue - This tracks the def index of the instruction that
8383 /// defines a particular value number in the interval. This may be ~0,
84 /// which is treated as unknown.
84 /// which is treated as unknown, or ~1, which is a deleted value number.
8585 SmallVector InstDefiningValue;
8686 public:
8787
115115 std::swap(weight, other.weight);
116116 std::swap(ranges, other.ranges);
117117 std::swap(NumValues, other.NumValues);
118 std::swap(InstDefiningValue, other.InstDefiningValue);
118119 }
119120
120121 bool containsOneValue() const { return NumValues == 1; }
121122
123 unsigned getNumValNums() const { return NumValues; }
124
122125 /// getNextValue - Create a new value number and return it. MIIdx specifies
123126 /// the instruction that defines the value number.
124127 unsigned getNextValue(unsigned MIIdx) {
137140 void setInstDefiningValNum(unsigned ValNo, unsigned MIIdx) {
138141 InstDefiningValue[ValNo] = MIIdx;
139142 }
143
144 /// MergeValueNumberInto - This method is called when two value nubmers
145 /// are found to be equivalent. This eliminates V1, replacing all
146 /// LiveRanges with the V1 value number with the V2 value number. This can
147 /// cause merging of V1/V2 values numbers and compaction of the value space.
148 void MergeValueNumberInto(unsigned V1, unsigned V2);
140149
141150
142151 bool empty() const { return ranges.empty(); }
162171
163172 /// getLiveRangeContaining - Return the live range that contains the
164173 /// specified index, or null if there is none.
165 const LiveRange *getLiveRangeContaining(unsigned Idx) const;
166
167
174 const LiveRange *getLiveRangeContaining(unsigned Idx) const {
175 const_iterator I = FindLiveRangeContaining(Idx);
176 return I == end() ? 0 : &*I;
177 }
178
179 /// FindLiveRangeContaining - Return an iterator to the live range that
180 /// contains the specified index, or end() if there is none.
181 const_iterator FindLiveRangeContaining(unsigned Idx) const;
182
183 /// FindLiveRangeContaining - Return an iterator to the live range that
184 /// contains the specified index, or end() if there is none.
185 iterator FindLiveRangeContaining(unsigned Idx);
186
168187 /// joinable - Two intervals are joinable if the either don't overlap at all
169188 /// or if the destination of the copy is a single assignment value, and it
170189 /// only overlaps with one value in the source interval.
5252 std::vector allocatableRegs_;
5353
5454 public:
55 struct InstrSlots
56 {
55 struct CopyRec {
56 MachineInstr *MI;
57 unsigned SrcReg, DstReg;
58 };
59 CopyRec getCopyRec(MachineInstr *MI, unsigned SrcReg, unsigned DstReg) {
60 CopyRec R;
61 R.MI = MI;
62 R.SrcReg = SrcReg;
63 R.DstReg = DstReg;
64 return R;
65 }
66 struct InstrSlots {
5767 enum {
5868 LOAD = 0,
5969 USE = 1,
132142 virtual void print(std::ostream &O, const Module* = 0) const;
133143
134144 private:
145 /// RemoveMachineInstrFromMaps - This marks the specified machine instr as
146 /// deleted.
147 void RemoveMachineInstrFromMaps(MachineInstr *MI) {
148 // remove index -> MachineInstr and
149 // MachineInstr -> index mappings
150 Mi2IndexMap::iterator mi2i = mi2iMap_.find(MI);
151 if (mi2i != mi2iMap_.end()) {
152 i2miMap_[mi2i->second/InstrSlots::NUM] = 0;
153 mi2iMap_.erase(mi2i);
154 }
155 }
156
135157 /// computeIntervals - compute live intervals
136158 void computeIntervals();
137159
138160 /// joinIntervals - join compatible live intervals
139161 void joinIntervals();
140162
141 /// joinIntervalsInMachineBB - Join intervals based on move
142 /// instructions in the specified basic block.
143 void joinIntervalsInMachineBB(MachineBasicBlock *MBB);
144
163 /// CopyCoallesceInMBB - Coallsece copies in the specified MBB, putting
164 /// copies that cannot yet be coallesced into the "TryAgain" list.
165 void CopyCoallesceInMBB(MachineBasicBlock *MBB,
166 std::vector &TryAgain);
167
168 /// JoinCopy - Attempt to join intervals corresponding to SrcReg/DstReg,
169 /// which are the src/dst of the copy instruction CopyMI. This returns true
170 /// if the copy was successfully coallesced away, or if it is never possible
171 /// to coallesce these this copy, due to register constraints. It returns
172 /// false if it is not currently possible to coallesce this interval, but
173 /// it may be possible if other things get coallesced.
174 bool JoinCopy(MachineInstr *CopyMI, unsigned SrcReg, unsigned DstReg);
175
145176 /// handleRegisterDef - update intervals for a register def
146177 /// (calls handlePhysicalRegisterDef and
147178 /// handleVirtualRegisterDef)
156187 LiveInterval& interval);
157188
158189 /// handlePhysicalRegisterDef - update intervals for a physical register
159 /// def. If the defining instruction is a move instruction, SrcReg will be
160 /// the input register, and DestReg will be the result. Note that Interval
161 /// may not match DestReg (it might be an alias instead).
162 ///
190 /// def.
163191 void handlePhysicalRegisterDef(MachineBasicBlock* mbb,
164192 MachineBasicBlock::iterator mi,
165193 LiveInterval& interval,
166 unsigned SrcReg, unsigned DestReg,
167194 bool isLiveIn = false);
168195
169196 /// Return true if the two specified registers belong to different
171198 bool differingRegisterClasses(unsigned RegA, unsigned RegB) const;
172199
173200
174 bool AdjustIfAllOverlappingRangesAreCopiesFrom(LiveInterval &IntA,
175 LiveInterval &IntB,
176 unsigned CopyIdx);
201 bool AdjustCopiesBackFrom(LiveInterval &IntA, LiveInterval &IntB,
202 MachineInstr *CopyMI, unsigned CopyIdx);
177203
178204 bool overlapsAliases(const LiveInterval *lhs,
179205 const LiveInterval *rhs) const;
345345
346346 /// getLiveRangeContaining - Return the live range that contains the
347347 /// specified index, or null if there is none.
348 const LiveRange *LiveInterval::getLiveRangeContaining(unsigned Idx) const {
349 Ranges::const_iterator It = std::upper_bound(ranges.begin(),ranges.end(),Idx);
348 LiveInterval::const_iterator
349 LiveInterval::FindLiveRangeContaining(unsigned Idx) const {
350 const_iterator It = std::upper_bound(begin(), end(), Idx);
350351 if (It != ranges.begin()) {
351 const LiveRange &LR = *prior(It);
352 if (LR.contains(Idx))
353 return &LR;
354 }
355
356 return 0;
357 }
358
359
352 --It;
353 if (It->contains(Idx))
354 return It;
355 }
356
357 return end();
358 }
359
360 LiveInterval::iterator
361 LiveInterval::FindLiveRangeContaining(unsigned Idx) {
362 iterator It = std::upper_bound(begin(), end(), Idx);
363 if (It != ranges.begin()) {
364 --It;
365 if (It->contains(Idx))
366 return It;
367 }
368
369 return end();
370 }
360371
361372 /// join - Join two live intervals (this, and other) together. This operation
362373 /// is the result of a copy instruction in the source program, that occurs at
375386 std::swap(MergedSrcValIdx, MergedDstValIdx);
376387 std::swap(ranges, Other.ranges);
377388 std::swap(NumValues, Other.NumValues);
389 std::swap(InstDefiningValue, Other.InstDefiningValue);
378390 }
379391
380392 // Join the ranges of other into the ranges of this interval.
393405
394406 InsertPos = addRangeFrom(*I, InsertPos);
395407 }
396
408
409 // Update the value number information for the value number defined by the
410 // copy. The copy is about to be removed, so ensure that the value is defined
411 // by whatever the other value is defined by.
412 if (InstDefiningValue[MergedDstValIdx] == CopyIdx) {
413 InstDefiningValue[MergedDstValIdx] =
414 Other.InstDefiningValue[MergedSrcValIdx];
415 }
416
397417 weight += Other.weight;
398418 }
419
420 /// MergeValueNumberInto - This method is called when two value nubmers
421 /// are found to be equivalent. This eliminates V1, replacing all
422 /// LiveRanges with the V1 value number with the V2 value number. This can
423 /// cause merging of V1/V2 values numbers and compaction of the value space.
424 void LiveInterval::MergeValueNumberInto(unsigned V1, unsigned V2) {
425 assert(V1 != V2 && "Identical value#'s are always equivalent!");
426
427 // This code actually merges the (numerically) larger value number into the
428 // smaller value number, which is likely to allow us to compactify the value
429 // space. The only thing we have to be careful of is to preserve the
430 // instruction that defines the result value.
431
432 // Make sure V2 is smaller than V1.
433 if (V1 < V2) {
434 setInstDefiningValNum(V1, getInstForValNum(V2));
435 std::swap(V1, V2);
436 }
437
438 // Merge V1 live ranges into V2.
439 for (iterator I = begin(); I != end(); ) {
440 iterator LR = I++;
441 if (LR->ValId != V1) continue; // Not a V1 LiveRange.
442
443 // Okay, we found a V1 live range. If it had a previous, touching, V2 live
444 // range, extend it.
445 if (LR != begin()) {
446 iterator Prev = LR-1;
447 if (Prev->ValId == V2 && Prev->end == LR->start) {
448 Prev->end = LR->end;
449
450 // Erase this live-range.
451 ranges.erase(LR);
452 I = Prev+1;
453 LR = Prev;
454 }
455 }
456
457 // Okay, now we have a V1 or V2 live range that is maximally merged forward.
458 // Ensure that it is a V2 live-range.
459 LR->ValId = V2;
460
461 // If we can merge it into later V2 live ranges, do so now. We ignore any
462 // following V1 live ranges, as they will be merged in subsequent iterations
463 // of the loop.
464 if (I != end()) {
465 if (I->start == LR->end && I->ValId == V2) {
466 LR->end = I->end;
467 ranges.erase(I);
468 I = LR+1;
469 }
470 }
471 }
472 }
473
399474
400475 std::ostream& llvm::operator<<(std::ostream& os, const LiveRange &LR) {
401476 return os << '[' << LR.start << ',' << LR.end << ':' << LR.ValId << ")";
6060 cl::init(true));
6161 }
6262
63 void LiveIntervals::getAnalysisUsage(AnalysisUsage &AU) const
64 {
63 void LiveIntervals::getAnalysisUsage(AnalysisUsage &AU) const {
6564 AU.addRequired();
6665 AU.addPreservedID(PHIEliminationID);
6766 AU.addRequiredID(PHIEliminationID);
7069 MachineFunctionPass::getAnalysisUsage(AU);
7170 }
7271
73 void LiveIntervals::releaseMemory()
74 {
72 void LiveIntervals::releaseMemory() {
7573 mi2iMap_.clear();
7674 i2miMap_.clear();
7775 r2iMap_.clear();
139137 for (MachineFunction::livein_iterator I = fn.livein_begin(),
140138 E = fn.livein_end(); I != E; ++I) {
141139 handlePhysicalRegisterDef(Entry, Entry->begin(),
142 getOrCreateInterval(I->first), 0, 0, true);
140 getOrCreateInterval(I->first), true);
143141 for (const unsigned* AS = mri_->getAliasSet(I->first); *AS; ++AS)
144142 handlePhysicalRegisterDef(Entry, Entry->begin(),
145 getOrCreateInterval(*AS), 0, 0, true);
143 getOrCreateInterval(*AS), true);
146144 }
147145 }
148146
178176 (RegRep = rep(srcReg)) == rep(dstReg)) {
179177 // remove from def list
180178 LiveInterval &interval = getOrCreateInterval(RegRep);
181 // remove index -> MachineInstr and
182 // MachineInstr -> index mappings
183 Mi2IndexMap::iterator mi2i = mi2iMap_.find(mii);
184 if (mi2i != mi2iMap_.end()) {
185 i2miMap_[mi2i->second/InstrSlots::NUM] = 0;
186 mi2iMap_.erase(mi2i);
187 }
179 RemoveMachineInstrFromMaps(mii);
188180 mii = mbbi->erase(mii);
189181 ++numPeep;
190182 }
251243 assert(li.weight != HUGE_VAL &&
252244 "attempt to spill already spilled interval!");
253245
254 DEBUG(std::cerr << "\t\t\t\tadding intervals for spills for interval: "
255 << li << '\n');
246 DEBUG(std::cerr << "\t\t\t\tadding intervals for spills for interval: ";
247 li.print(std::cerr, mri_); std::cerr << '\n');
256248
257249 const TargetRegisterClass* rc = mf_->getSSARegMap()->getRegClass(li.reg);
258250
340332 // a def, we can't do this.
341333 if (!mop.isUse()) NewRegLiveIn = 0;
342334
343 DEBUG(std::cerr << "\t\t\t\tadded new interval: " << nI << '\n');
335 DEBUG(std::cerr << "\t\t\t\tadded new interval: ";
336 nI.print(std::cerr, mri_); std::cerr << '\n');
344337 }
345338 }
346339 }
477470 if (lv_->RegisterDefIsDead(mi, interval.reg))
478471 interval.addRange(LiveRange(RedefIndex, RedefIndex+1, 0));
479472
480 DEBUG(std::cerr << "RESULT: " << interval);
473 DEBUG(std::cerr << "RESULT: "; interval.print(std::cerr, mri_));
481474
482475 } else {
483476 // Otherwise, this must be because of phi elimination. If this is the
491484 MachineInstr *Killer = vi.Kills[0];
492485 unsigned Start = getInstructionIndex(Killer->getParent()->begin());
493486 unsigned End = getUseIndex(getInstructionIndex(Killer))+1;
494 DEBUG(std::cerr << "Removing [" << Start << "," << End << "] from: "
495 << interval << "\n");
487 DEBUG(std::cerr << "Removing [" << Start << "," << End << "] from: ";
488 interval.print(std::cerr, mri_); std::cerr << "\n");
496489 interval.removeRange(Start, End);
497 DEBUG(std::cerr << "RESULT: " << interval);
490 DEBUG(std::cerr << "RESULT: "; interval.print(std::cerr, mri_));
498491
499492 // Replace the interval with one of a NEW value number. Note that this
500493 // value number isn't actually defined by an instruction, weird huh? :)
501494 LiveRange LR(Start, End, interval.getNextValue(~0U));
502495 DEBUG(std::cerr << " replace range with " << LR);
503496 interval.addRange(LR);
504 DEBUG(std::cerr << "RESULT: " << interval);
497 DEBUG(std::cerr << "RESULT: "; interval.print(std::cerr, mri_));
505498 }
506499
507500 // In the case of PHI elimination, each variable definition is only
522515 void LiveIntervals::handlePhysicalRegisterDef(MachineBasicBlock *MBB,
523516 MachineBasicBlock::iterator mi,
524517 LiveInterval& interval,
525 unsigned SrcReg, unsigned DestReg,
526518 bool isLiveIn) {
527519 // A physical register cannot be live across basic block, so its
528520 // lifetime must end somewhere in its defining basic block.
563555 exit:
564556 assert(start < end && "did not find end of interval?");
565557
566 // Finally, if this is defining a new range for the physical register, and if
567 // that physreg is just a copy from a vreg, and if THAT vreg was a copy from
568 // the physreg, then the new fragment has the same value as the one copied
569 // into the vreg.
570 if (interval.reg == DestReg && !interval.empty() &&
571 MRegisterInfo::isVirtualRegister(SrcReg)) {
572
573 // Get the live interval for the vreg, see if it is defined by a copy.
574 LiveInterval &SrcInterval = getOrCreateInterval(SrcReg);
575
576 if (SrcInterval.containsOneValue()) {
577 assert(!SrcInterval.empty() && "Can't contain a value and be empty!");
578
579 // Get the first index of the first range. Though the interval may have
580 // multiple liveranges in it, we only check the first.
581 unsigned StartIdx = SrcInterval.begin()->start;
582 MachineInstr *SrcDefMI = getInstructionFromIndex(StartIdx);
583
584 // Check to see if the vreg was defined by a copy instruction, and that
585 // the source was this physreg.
586 unsigned VRegSrcSrc, VRegSrcDest;
587 if (tii_->isMoveInstr(*SrcDefMI, VRegSrcSrc, VRegSrcDest) &&
588 SrcReg == VRegSrcDest && VRegSrcSrc == DestReg) {
589 // Okay, now we know that the vreg was defined by a copy from this
590 // physreg. Find the value number being copied and use it as the value
591 // for this range.
592 const LiveRange *DefRange = interval.getLiveRangeContaining(StartIdx-1);
593 if (DefRange) {
594 LiveRange LR(start, end, DefRange->ValId);
595 interval.addRange(LR);
596 DEBUG(std::cerr << " +" << LR << '\n');
597 return;
598 }
599 }
600 }
601 }
602
603 LiveRange LR(start, end, interval.getNextValue(start));
558 LiveRange LR(start, end, interval.getNextValue(isLiveIn ? ~0U : start));
604559 interval.addRange(LR);
605560 DEBUG(std::cerr << " +" << LR << '\n');
606561 }
611566 if (MRegisterInfo::isVirtualRegister(reg))
612567 handleVirtualRegisterDef(MBB, MI, getOrCreateInterval(reg));
613568 else if (allocatableRegs_[reg]) {
614 unsigned SrcReg = 0, DestReg = 0;
615 if (!tii_->isMoveInstr(*MI, SrcReg, DestReg))
616 SrcReg = DestReg = 0;
617
618 handlePhysicalRegisterDef(MBB, MI, getOrCreateInterval(reg),
619 SrcReg, DestReg);
569 handlePhysicalRegisterDef(MBB, MI, getOrCreateInterval(reg));
620570 for (const unsigned* AS = mri_->getAliasSet(reg); *AS; ++AS)
621 handlePhysicalRegisterDef(MBB, MI, getOrCreateInterval(*AS),
622 SrcReg, DestReg);
571 handlePhysicalRegisterDef(MBB, MI, getOrCreateInterval(*AS));
623572 }
624573 }
625574
627576 /// registers. for some ordering of the machine instructions [1,N] a
628577 /// live interval is an interval [i, j) where 1 <= i <= j < N for
629578 /// which a variable is live
630 void LiveIntervals::computeIntervals()
631 {
579 void LiveIntervals::computeIntervals() {
632580 DEBUG(std::cerr << "********** COMPUTING LIVE INTERVALS **********\n");
633581 DEBUG(std::cerr << "********** Function: "
634582 << ((Value*)mf_->getFunction())->getName() << '\n');
663611 }
664612 }
665613
666 /// IntA is defined as a copy from IntB and we know it only has one value
667 /// number. If all of the places that IntA and IntB overlap are defined by
668 /// copies from IntA to IntB, we know that these two ranges can really be
669 /// merged if we adjust the value numbers. If it is safe, adjust the value
670 /// numbers and return true, allowing coalescing to occur.
671 bool LiveIntervals::
672 AdjustIfAllOverlappingRangesAreCopiesFrom(LiveInterval &IntA,
673 LiveInterval &IntB,
674 unsigned CopyIdx) {
675 std::vector Ranges;
676 IntA.getOverlapingRanges(IntB, CopyIdx, Ranges);
677
678 assert(!Ranges.empty() && "Why didn't we do a simple join of this?");
679
680 unsigned IntBRep = rep(IntB.reg);
681
682 // Check to see if all of the overlaps (entries in Ranges) are defined by a
683 // copy from IntA. If not, exit.
684 for (unsigned i = 0, e = Ranges.size(); i != e; ++i) {
685 unsigned Idx = Ranges[i]->start;
686 MachineInstr *MI = getInstructionFromIndex(Idx);
687 unsigned SrcReg, DestReg;
688 if (!tii_->isMoveInstr(*MI, SrcReg, DestReg)) return false;
614 /// AdjustCopiesBackFrom - We found a non-trivially-coallescable copy with IntA
615 /// being the source and IntB being the dest, thus this defines a value number
616 /// in IntB. If the source value number (in IntA) is defined by a copy from B,
617 /// see if we can merge these two pieces of B into a single value number,
618 /// eliminating a copy. For example:
619 ///
620 /// A3 = B0
621 /// ...
622 /// B1 = A3 <- this copy
623 ///
624 /// In this case, B0 can be extended to where the B1 copy lives, allowing the B1
625 /// value number to be replaced with B0 (which simplifies the B liveinterval).
626 ///
627 /// This returns true if an interval was modified.
628 ///
629 bool LiveIntervals::AdjustCopiesBackFrom(LiveInterval &IntA, LiveInterval &IntB,
630 MachineInstr *CopyMI,
631 unsigned CopyIdx) {
632 // BValNo is a value number in B that is defined by a copy from A. 'B3' in
633 // the example above.
634 LiveInterval::iterator BLR = IntB.FindLiveRangeContaining(CopyIdx);
635 unsigned BValNo = BLR->ValId;
636
637 // Get the location that B is defined at. Two options: either this value has
638 // an unknown definition point or it is defined at CopyIdx. If unknown, we
639 // can't process it.
640 unsigned BValNoDefIdx = IntB.getInstForValNum(BValNo);
641 if (BValNoDefIdx == ~0U) return false;
642 assert(BValNoDefIdx == CopyIdx &&
643 "Copy doesn't define the value?");
644
645 // AValNo is the value number in A that defines the copy, A0 in the example.
646 LiveInterval::iterator AValLR = IntA.FindLiveRangeContaining(CopyIdx-1);
647 unsigned AValNo = AValLR->ValId;
648
649 // If AValNo is defined as a copy from IntB, we can potentially process this.
650
651 // Get the instruction that defines this value number.
652 unsigned AValNoInstIdx = IntA.getInstForValNum(AValNo);
653
654 // If it's unknown, ignore it.
655 if (AValNoInstIdx == ~0U || AValNoInstIdx == ~1U) return false;
656 // Otherwise, get the instruction for it.
657 MachineInstr *AValNoInstMI = getInstructionFromIndex(AValNoInstIdx);
689658
690 // If this copy isn't actually defining this range, it must be a live
691 // range spanning basic blocks or something.
692 if (rep(DestReg) != rep(IntA.reg)) return false;
659 // If the value number is not defined by a copy instruction, ignore it.
660 unsigned SrcReg, DstReg;
661 if (!tii_->isMoveInstr(*AValNoInstMI, SrcReg, DstReg))
662 return false;
693663
694 // Check to see if this is coming from IntB. If not, bail out.
695 if (rep(SrcReg) != IntBRep) return false;
696 }
697
698 // Okay, we can change this one. Get the IntB value number that IntA is
699 // copied from.
700 unsigned ActualValNo = IntA.getLiveRangeContaining(CopyIdx-1)->ValId;
701
702 // Change all of the value numbers to the same as what we IntA is copied from.
703 for (unsigned i = 0, e = Ranges.size(); i != e; ++i)
704 Ranges[i]->ValId = ActualValNo;
705
664 // If the source register comes from an interval other than IntB, we can't
665 // handle this.
666 assert(rep(DstReg) == IntA.reg && "Not defining a reg in IntA?");
667 if (rep(SrcReg) != IntB.reg) return false;
668
669 // Get the LiveRange in IntB that this value number starts with.
670 LiveInterval::iterator ValLR = IntB.FindLiveRangeContaining(AValNoInstIdx-1);
671
672 // Make sure that the end of the live range is inside the same block as
673 // CopyMI.
674 MachineInstr *ValLREndInst = getInstructionFromIndex(ValLR->end-1);
675 if (ValLREndInst->getParent() != CopyMI->getParent()) return false;
676
677 // Okay, we now know that ValLR ends in the same block that the CopyMI
678 // live-range starts. If there are no intervening live ranges between them in
679 // IntB, we can merge them.
680 if (ValLR+1 != BLR) return false;
681
682 DEBUG(std::cerr << "\nExtending: "; IntB.print(std::cerr, mri_));
683
684 // Okay, we can merge them. We need to insert a new liverange:
685 // [ValLR.end, BLR.begin) of either value number, then we merge the
686 // two value numbers.
687 IntB.addRange(LiveRange(ValLR->end, BLR->start, BValNo));
688
689 // Okay, merge "B1" into the same value number as "B0".
690 if (BValNo != ValLR->ValId)
691 IntB.MergeValueNumberInto(BValNo, ValLR->ValId);
692 DEBUG(std::cerr << " result = "; IntB.print(std::cerr, mri_);
693 std::cerr << "\n");
694
695 // Finally, delete the copy instruction.
696 RemoveMachineInstrFromMaps(CopyMI);
697 CopyMI->eraseFromParent();
698 ++numPeep;
706699 return true;
707700 }
708701
709 void LiveIntervals::joinIntervalsInMachineBB(MachineBasicBlock *MBB) {
710 DEBUG(std::cerr << ((Value*)MBB->getBasicBlock())->getName() << ":\n");
711
712 for (MachineBasicBlock::iterator mi = MBB->begin(), mie = MBB->end();
713 mi != mie; ++mi) {
714 DEBUG(std::cerr << getInstructionIndex(mi) << '\t' << *mi);
715
716 // we only join virtual registers with allocatable
717 // physical registers since we do not have liveness information
718 // on not allocatable physical registers
719 unsigned SrcReg, DestReg;
720 if (tii_->isMoveInstr(*mi, SrcReg, DestReg) &&
721 (MRegisterInfo::isVirtualRegister(SrcReg) || allocatableRegs_[SrcReg])&&
722 (MRegisterInfo::isVirtualRegister(DestReg)||allocatableRegs_[DestReg])){
723
724 // Get representative registers.
725 SrcReg = rep(SrcReg);
726 DestReg = rep(DestReg);
727
728 // If they are already joined we continue.
729 if (SrcReg == DestReg)
730 continue;
731
732 // If they are both physical registers, we cannot join them.
733 if (MRegisterInfo::isPhysicalRegister(SrcReg) &&
734 MRegisterInfo::isPhysicalRegister(DestReg))
735 continue;
736
737 // If they are not of the same register class, we cannot join them.
738 if (differingRegisterClasses(SrcReg, DestReg))
739 continue;
740
741 LiveInterval &SrcInt = getInterval(SrcReg);
742 LiveInterval &DestInt = getInterval(DestReg);
743 assert(SrcInt.reg == SrcReg && DestInt.reg == DestReg &&
744 "Register mapping is horribly broken!");
745
746 DEBUG(std::cerr << "\t\tInspecting "; SrcInt.print(std::cerr, mri_);
747 std::cerr << " and "; DestInt.print(std::cerr, mri_);
748 std::cerr << ": ");
749
750 // If two intervals contain a single value and are joined by a copy, it
751 // does not matter if the intervals overlap, they can always be joined.
752 bool Joinable = SrcInt.containsOneValue() && DestInt.containsOneValue();
753
754 unsigned MIDefIdx = getDefIndex(getInstructionIndex(mi));
755
756 // If the intervals think that this is joinable, do so now.
757 if (!Joinable && DestInt.joinable(SrcInt, MIDefIdx))
758 Joinable = true;
759
760 // If DestInt is actually a copy from SrcInt (which we know) that is used
761 // to define another value of SrcInt, we can change the other range of
762 // SrcInt to be the value of the range that defines DestInt, allowing a
763 // coalesce.
764 if (!Joinable && DestInt.containsOneValue() &&
765 AdjustIfAllOverlappingRangesAreCopiesFrom(SrcInt, DestInt, MIDefIdx))
766 Joinable = true;
767
768 if (!Joinable || overlapsAliases(&SrcInt, &DestInt)) {
769 DEBUG(std::cerr << "Interference!\n");
770 } else {
771 DestInt.join(SrcInt, MIDefIdx);
772 DEBUG(std::cerr << "Joined. Result = " << DestInt << "\n");
773
774 if (!MRegisterInfo::isPhysicalRegister(SrcReg)) {
775 r2iMap_.erase(SrcReg);
776 r2rMap_[SrcReg] = DestReg;
777 } else {
778 // Otherwise merge the data structures the other way so we don't lose
779 // the physreg information.
780 r2rMap_[DestReg] = SrcReg;
781 DestInt.reg = SrcReg;
782 SrcInt.swap(DestInt);
783 r2iMap_.erase(DestReg);
784 }
785 ++numJoins;
786 }
787 }
788 }
789 }
702
703 /// JoinCopy - Attempt to join intervals corresponding to SrcReg/DstReg,
704 /// which are the src/dst of the copy instruction CopyMI. This returns true
705 /// if the copy was successfully coallesced away, or if it is never possible
706 /// to coallesce these this copy, due to register constraints. It returns
707 /// false if it is not currently possible to coallesce this interval, but
708 /// it may be possible if other things get coallesced.
709 bool LiveIntervals::JoinCopy(MachineInstr *CopyMI,
710 unsigned SrcReg, unsigned DstReg) {
711
712
713 DEBUG(std::cerr << getInstructionIndex(CopyMI) << '\t' << *CopyMI);
714
715 // Get representative registers.
716 SrcReg = rep(SrcReg);
717 DstReg = rep(DstReg);
718
719 // If they are already joined we continue.
720 if (SrcReg == DstReg) {
721 DEBUG(std::cerr << "\tCopy already coallesced.\n");
722 return true; // Not coallescable.
723 }
724
725 // If they are both physical registers, we cannot join them.
726 if (MRegisterInfo::isPhysicalRegister(SrcReg) &&
727 MRegisterInfo::isPhysicalRegister(DstReg)) {
728 DEBUG(std::cerr << "\tCan not coallesce physregs.\n");
729 return true; // Not coallescable.
730 }
731
732 // We only join virtual registers with allocatable physical registers.
733 if (MRegisterInfo::isPhysicalRegister(SrcReg) && !allocatableRegs_[SrcReg]){
734 DEBUG(std::cerr << "\tSrc reg is unallocatable physreg.\n");
735 return true; // Not coallescable.
736 }
737 if (MRegisterInfo::isPhysicalRegister(DstReg) && !allocatableRegs_[DstReg]){
738 DEBUG(std::cerr << "\tDst reg is unallocatable physreg.\n");
739 return true; // Not coallescable.
740 }
741
742 // If they are not of the same register class, we cannot join them.
743 if (differingRegisterClasses(SrcReg, DstReg)) {
744 DEBUG(std::cerr << "\tSrc/Dest are different register classes.\n");
745 return true; // Not coallescable.
746 }
747
748 LiveInterval &SrcInt = getInterval(SrcReg);
749 LiveInterval &DestInt = getInterval(DstReg);
750 assert(SrcInt.reg == SrcReg && DestInt.reg == DstReg &&
751 "Register mapping is horribly broken!");
752
753 DEBUG(std::cerr << "\t\tInspecting "; SrcInt.print(std::cerr, mri_);
754 std::cerr << " and "; DestInt.print(std::cerr, mri_);
755 std::cerr << ": ");
756
757 // If two intervals contain a single value and are joined by a copy, it
758 // does not matter if the intervals overlap, they can always be joined.
759
760 bool Joinable = SrcInt.containsOneValue() && DestInt.containsOneValue();
761
762 unsigned MIDefIdx = getDefIndex(getInstructionIndex(CopyMI));
763
764 // If the intervals think that this is joinable, do so now.
765 if (!Joinable && DestInt.joinable(SrcInt, MIDefIdx))
766 Joinable = true;
767
768 // If DestInt is actually a copy from SrcInt (which we know) that is used
769 // to define another value of SrcInt, we can change the other range of
770 // SrcInt to be the value of the range that defines DestInt, simplying the
771 // interval an promoting coallescing.
772 if (!Joinable && AdjustCopiesBackFrom(SrcInt, DestInt, CopyMI, MIDefIdx))
773 return true;
774
775 // If this looks joinable, do the final, expensive last check, checking to see
776 // if aliases overlap. If they do, we can never join these.
777 if (Joinable && overlapsAliases(&SrcInt, &DestInt)) {
778 DEBUG(std::cerr << "Alias Overlap Interference!\n");
779 return true; // Can never join these.
780 }
781
782 if (!Joinable) {
783 DEBUG(std::cerr << "Interference!\n");
784 return false;
785 }
786
787 DestInt.join(SrcInt, MIDefIdx);
788 DEBUG(std::cerr << "\n\t\tJoined. Result = "; DestInt.print(std::cerr, mri_);
789 std::cerr << "\n");
790
791 if (!MRegisterInfo::isPhysicalRegister(SrcReg)) {
792 r2iMap_.erase(SrcReg);
793 r2rMap_[SrcReg] = DstReg;
794 } else {
795 // Otherwise merge the data structures the other way so we don't lose
796 // the physreg information.
797 r2rMap_[DstReg] = SrcReg;
798 DestInt.reg = SrcReg;
799 SrcInt.swap(DestInt);
800 r2iMap_.erase(DstReg);
801 }
802 ++numJoins;
803 return true;
804 }
805
806
790807
791808 namespace {
792809 // DepthMBBCompare - Comparison predicate that sort first based on the loop
801818 };
802819 }
803820
821
822 void LiveIntervals::CopyCoallesceInMBB(MachineBasicBlock *MBB,
823 std::vector &TryAgain) {
824 DEBUG(std::cerr << ((Value*)MBB->getBasicBlock())->getName() << ":\n");
825
826 for (MachineBasicBlock::iterator MII = MBB->begin(), E = MBB->end();
827 MII != E;) {
828 MachineInstr *Inst = MII++;
829
830 // If this isn't a copy, we can't join intervals.
831 unsigned SrcReg, DstReg;
832 if (!tii_->isMoveInstr(*Inst, SrcReg, DstReg)) continue;
833
834 if (!JoinCopy(Inst, SrcReg, DstReg))
835 TryAgain.push_back(getCopyRec(Inst, SrcReg, DstReg));
836 }
837 }
838
839
804840 void LiveIntervals::joinIntervals() {
805841 DEBUG(std::cerr << "********** JOINING INTERVALS ***********\n");
806842
843 std::vector TryAgainList;
844
807845 const LoopInfo &LI = getAnalysis();
808846 if (LI.begin() == LI.end()) {
809847 // If there are no loops in the function, join intervals in function order.
810848 for (MachineFunction::iterator I = mf_->begin(), E = mf_->end();
811849 I != E; ++I)
812 joinIntervalsInMachineBB(I);
850 CopyCoallesceInMBB(I, TryAgainList);
813851 } else {
814852 // Otherwise, join intervals in inner loops before other intervals.
815853 // Unfortunately we can't just iterate over loop hierarchy here because
824862
825863 // Finally, join intervals in loop nest order.
826864 for (unsigned i = 0, e = MBBs.size(); i != e; ++i)
827 joinIntervalsInMachineBB(MBBs[i].second);
828 }
829
865 CopyCoallesceInMBB(MBBs[i].second, TryAgainList);
866 }
867
868 // Joining intervals can allow other intervals to be joined. Iteratively join
869 // until we make no progress.
870 bool ProgressMade = true;
871 while (ProgressMade) {
872 ProgressMade = false;
873
874 for (unsigned i = 0, e = TryAgainList.size(); i != e; ++i) {
875 CopyRec &TheCopy = TryAgainList[i];
876 if (TheCopy.MI &&
877 JoinCopy(TheCopy.MI, TheCopy.SrcReg, TheCopy.DstReg)) {
878 TheCopy.MI = 0; // Mark this one as done.
879 ProgressMade = true;
880 }
881 }
882 }
883
830884 DEBUG(std::cerr << "*** Register mapping ***\n");
831885 DEBUG(for (int i = 0, e = r2rMap_.size(); i != e; ++i)
832886 if (r2rMap_[i]) {
520520 // Process all of the spilled uses and all non spilled reg references.
521521 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
522522 MachineOperand &MO = MI.getOperand(i);
523
524523 if (!MO.isRegister() || MO.getReg() == 0)
525524 continue; // Ignore non-register operands.
526525
790789 }
791790
792791 if (!OpTakenCareOf) {
792 // Check to see if this is a noop copy. If so, eliminate the
793 // instruction before considering the dest reg to be changed.
793794 unsigned Src, Dst;
794 if (TII->isMoveInstr(MI, Src, Dst)) {
795 if (Src == Dst) {
796 // Check to see if this is a noop copy. If so, eliminate
797 // the instruction before considering the dest reg to be
798 // changed.
799 ++NumDCE;
800 DEBUG(std::cerr << "Removing now-noop copy: " << MI);
801 MBB.erase(&MI);
802 VRM.RemoveFromFoldedVirtMap(&MI);
803 goto ProcessNextInst;
804 } else if (MII != MBB.begin()) {
805 // Check to see if this is a sequence of the form:
806 // mov R0, R1
807 // mov R1, R0
808 // Eliminate the second move if so.
809 MachineBasicBlock::iterator PrevMII = MII; --PrevMII;
810 MachineInstr& PrevMI = *PrevMII;
811 unsigned PrevSrc, PrevDst;
812
813 if (TII->isMoveInstr(PrevMI, PrevSrc, PrevDst))
814 if (PrevSrc == Dst && PrevDst == Src) {
815 ++NumDCE;
816 DEBUG(std::cerr << "Removing now-noop copy: " << MI);
817 MBB.erase(&MI);
818 VRM.RemoveFromFoldedVirtMap(&MI);
819 goto ProcessNextInst;
820 }
821 }
795 if (TII->isMoveInstr(MI, Src, Dst) && Src == Dst) {
796 ++NumDCE;
797 DEBUG(std::cerr << "Removing now-noop copy: " << MI);
798 MBB.erase(&MI);
799 VRM.RemoveFromFoldedVirtMap(&MI);
800 goto ProcessNextInst;
822801 }
823
824802 Spills.ClobberPhysReg(VirtReg);
825803 continue;
826804 }
882860 }
883861 }
884862
863
864
885865 llvm::Spiller* llvm::createSpiller() {
886866 switch (SpillerOpt) {
887867 default: assert(0 && "Unreachable!");