llvm.org GIT mirror llvm / f769239
[x86] enable machine combiner reassociations for scalar single-precision multiplies git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@241752 91177308-0d34-0410-b5e6-96231b3b80d8 Sanjay Patel 4 years ago
4 changed file(s) with 31 addition(s) and 8 deletion(s). Raw diff Collapse all Expand all
64046404
64056405 // TODO: There are many more machine instruction opcodes to match:
64066406 // 1. Other data types (double, integer, vectors)
6407 // 2. Other math / logic operations (mul, and, or)
6407 // 2. Other math / logic operations (and, or)
64086408 static bool isAssociativeAndCommutative(unsigned Opcode) {
64096409 switch (Opcode) {
6410 case X86::ADDSSrr:
64106411 case X86::VADDSSrr:
6411 case X86::ADDSSrr:
6412 case X86::MULSSrr:
6413 case X86::VMULSSrr:
64126414 return true;
64136415 default:
64146416 return false;
None ; RUN: llc < %s -mtriple=x86_64-unknown-unknown | FileCheck %s
0 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mcpu=x86-64 | FileCheck %s
11
22 ; Anything more than one division using a single divisor operand
33 ; should be converted into a reciprocal and multiplication.
1616 ; CHECK: # BB#0:
1717 ; CHECK-NEXT: movss {{.*#+}} xmm3 = mem[0],zero,zero,zero
1818 ; CHECK-NEXT: divss %xmm2, %xmm3
19 ; CHECK-NEXT: mulss %xmm1, %xmm0
1920 ; CHECK-NEXT: mulss %xmm3, %xmm0
20 ; CHECK-NEXT: mulss %xmm1, %xmm0
2121 ; CHECK-NEXT: mulss %xmm3, %xmm0
2222 ; CHECK-NEXT: retq
2323 %div1 = fdiv arcp float %x, %z
143143 ret float %t2
144144 }
145145
146 ; Verify that SSE and AVX scalar single precison multiplies are reassociated.
147
148 define float @reassociate_muls1(float %x0, float %x1, float %x2, float %x3) {
149 ; SSE-LABEL: reassociate_muls1:
150 ; SSE: # BB#0:
151 ; SSE-NEXT: divss %xmm1, %xmm0
152 ; SSE-NEXT: mulss %xmm3, %xmm2
153 ; SSE-NEXT: mulss %xmm2, %xmm0
154 ; SSE-NEXT: retq
155 ;
156 ; AVX-LABEL: reassociate_muls1:
157 ; AVX: # BB#0:
158 ; AVX-NEXT: vdivss %xmm1, %xmm0, %xmm0
159 ; AVX-NEXT: vmulss %xmm3, %xmm2, %xmm1
160 ; AVX-NEXT: vmulss %xmm1, %xmm0, %xmm0
161 ; AVX-NEXT: retq
162 %t0 = fdiv float %x0, %x1
163 %t1 = fmul float %x2, %t0
164 %t2 = fmul float %x3, %t1
165 ret float %t2
166 }
3333 ; ESTIMATE: # BB#0:
3434 ; ESTIMATE-NEXT: vrsqrtss %xmm0, %xmm0, %xmm1
3535 ; ESTIMATE-NEXT: vmulss {{.*}}(%rip), %xmm1, %xmm2
36 ; ESTIMATE-NEXT: vmulss %xmm1, %xmm1, %xmm1
37 ; ESTIMATE-NEXT: vmulss %xmm0, %xmm1, %xmm1
36 ; ESTIMATE-NEXT: vmulss %xmm0, %xmm1, %xmm3
37 ; ESTIMATE-NEXT: vmulss %xmm3, %xmm1, %xmm1
3838 ; ESTIMATE-NEXT: vaddss {{.*}}(%rip), %xmm1, %xmm1
39 ; ESTIMATE-NEXT: vmulss %xmm0, %xmm2, %xmm2
3940 ; ESTIMATE-NEXT: vmulss %xmm2, %xmm1, %xmm1
40 ; ESTIMATE-NEXT: vmulss %xmm1, %xmm0, %xmm1
4141 ; ESTIMATE-NEXT: vxorps %xmm2, %xmm2, %xmm2
4242 ; ESTIMATE-NEXT: vcmpeqss %xmm2, %xmm0, %xmm0
4343 ; ESTIMATE-NEXT: vandnps %xmm1, %xmm0, %xmm0
7777 ; ESTIMATE: # BB#0:
7878 ; ESTIMATE-NEXT: vrsqrtss %xmm0, %xmm0, %xmm1
7979 ; ESTIMATE-NEXT: vmulss {{.*}}(%rip), %xmm1, %xmm2
80 ; ESTIMATE-NEXT: vmulss %xmm1, %xmm1, %xmm1
80 ; ESTIMATE-NEXT: vmulss %xmm0, %xmm1, %xmm0
8181 ; ESTIMATE-NEXT: vmulss %xmm0, %xmm1, %xmm0
8282 ; ESTIMATE-NEXT: vaddss {{.*}}(%rip), %xmm0, %xmm0
8383 ; ESTIMATE-NEXT: vmulss %xmm2, %xmm0, %xmm0