llvm.org GIT mirror llvm / f767018
R600/SI: add VOP mapping functions Make it possible to map between e32 and e64 encoding opcodes. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@176104 91177308-0d34-0410-b5e6-96231b3b80d8 Christian Konig 7 years ago
3 changed file(s) with 35 addition(s) and 11 deletion(s). Raw diff Collapse all Expand all
2121 #include "llvm/CodeGen/MachineRegisterInfo.h"
2222
2323 #define GET_INSTRINFO_CTOR
24 #define GET_INSTRMAP_INFO
2425 #include "AMDGPUGenInstrInfo.inc"
2526
2627 using namespace llvm;
7272 virtual const TargetRegisterClass *getSuperIndirectRegClass() const;
7373 };
7474
75 namespace AMDGPU {
76
77 int getVOPe64(uint16_t Opcode);
78
79 } // End namespace AMDGPU
80
7581 } // End namespace llvm
7682
7783 namespace SIInstrFlags {
142142 // Vector ALU classes
143143 //===----------------------------------------------------------------------===//
144144
145 class VOP {
146 string OpName = opName;
147 }
148
145149 multiclass VOP1_Helper op, RegisterClass drc, RegisterClass src,
146150 string opName, list pattern> {
147151
148 def _e32: VOP1 <
152 def _e32 : VOP1 <
149153 op, (outs drc:$dst), (ins src:$src0),
150154 opName#"_e32 $dst, $src0", pattern
151 >;
155 >, VOP ;
152156
153157 def _e64 : VOP3 <
154158 {1, 1, op{6}, op{5}, op{4}, op{3}, op{2}, op{1}, op{0}},
157161 i32imm:$abs, i32imm:$clamp,
158162 i32imm:$omod, i32imm:$neg),
159163 opName#"_e64 $dst, $src0, $abs, $clamp, $omod, $neg", []
160 > {
164 >, VOP {
161165 let SRC1 = SIOperand.ZERO;
162166 let SRC2 = SIOperand.ZERO;
163167 }
174178 def _e32 : VOP2 <
175179 op, (outs vrc:$dst), (ins arc:$src0, vrc:$src1),
176180 opName#"_e32 $dst, $src0, $src1", pattern
177 >;
181 >, VOP ;
178182
179183 def _e64 : VOP3 <
180184 {1, 0, 0, op{5}, op{4}, op{3}, op{2}, op{1}, op{0}},
183187 i32imm:$abs, i32imm:$clamp,
184188 i32imm:$omod, i32imm:$neg),
185189 opName#"_e64 $dst, $src0, $src1, $abs, $clamp, $omod, $neg", []
186 > {
190 >, VOP {
187191 let SRC2 = SIOperand.ZERO;
188192 }
189193 }
199203 def _e32 : VOP2 <
200204 op, (outs VReg_32:$dst), (ins VSrc_32:$src0, VReg_32:$src1),
201205 opName#"_e32 $dst, $src0, $src1", pattern
202 >;
206 >, VOP ;
203207
204208 def _e64 : VOP3b <
205209 {1, 0, 0, op{5}, op{4}, op{3}, op{2}, op{1}, op{0}},
208212 i32imm:$abs, i32imm:$clamp,
209213 i32imm:$omod, i32imm:$neg),
210214 opName#"_e64 $dst, $src0, $src1, $abs, $clamp, $omod, $neg", []
211 > {
215 >, VOP {
212216 let SRC2 = SIOperand.ZERO;
213217 /* the VOP2 variant puts the carry out into VCC, the VOP3 variant
214218 can write it into any SGPR. We currently don't use the carry out,
223227 def _e32 : VOPC <
224228 op, (ins arc:$src0, vrc:$src1),
225229 opName#"_e32 $dst, $src0, $src1", []
226 >;
230 >, VOP ;
227231
228232 def _e64 : VOP3 <
229233 {0, op{7}, op{6}, op{5}, op{4}, op{3}, op{2}, op{1}, op{0}},
235239 !if(!eq(!cast(cond), "COND_NULL"), [],
236240 [(set SReg_64:$dst, (i1 (setcc (vt arc:$src0), arc:$src1, cond)))]
237241 )
238 > {
242 >, VOP {
239243 let SRC2 = SIOperand.ZERO;
240244 }
241245 }
253257 (ins VSrc_32:$src0, VSrc_32:$src1, VSrc_32:$src2,
254258 i32imm:$abs, i32imm:$clamp, i32imm:$omod, i32imm:$neg),
255259 opName#" $dst, $src0, $src1, $src2, $abs, $clamp, $omod, $neg", pattern
256 >;
260 >, VOP ;
257261
258262 class VOP3_64 op, string opName, list pattern> : VOP3 <
259263 op, (outs VReg_64:$dst),
260264 (ins VSrc_64:$src0, VSrc_64:$src1, VSrc_64:$src2,
261265 i32imm:$abs, i32imm:$clamp, i32imm:$omod, i32imm:$neg),
262266 opName#" $dst, $src0, $src1, $src2, $abs, $clamp, $omod, $neg", pattern
263 >;
267 >, VOP ;
264268
265269 //===----------------------------------------------------------------------===//
266270 // Vector I/O classes
318322 let mayStore = 0;
319323 }
320324
325 //===----------------------------------------------------------------------===//
326 // Vector instruction mappings
327 //===----------------------------------------------------------------------===//
328
329 // Maps an opcode in e32 form to its e64 equivalent
330 def getVOPe64 : InstrMapping {
331 let FilterClass = "VOP";
332 let RowFields = ["OpName"];
333 let ColFields = ["Size"];
334 let KeyCol = ["4"];
335 let ValueCols = [["8"]];
336 }
337
321338 include "SIInstructions.td"