llvm.org GIT mirror llvm / f75e5b4
Change Feature64Bit to not imply FeatureSSE2. All x86-64 hardware has SSE2, however it's possible to disable SSE2, and the subtarget support code thinks that if 64-bit implies SSE2 and SSE2 is disabled then 64-bit should also be disabled. Instead, just mark all the 64-bit subtargets as explicitly supporting SSE2. Also, move the code that makes -march=x86-64 enable 64-bit support by default to only apply when there is no explicit subtarget. If you need to specify a subtarget and you want 64-bit code, you'll need to select a subtarget that supports 64-bit code. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@63575 91177308-0d34-0410-b5e6-96231b3b80d8 Dan Gohman 10 years ago
2 changed file(s) with 23 addition(s) and 18 deletion(s). Raw diff Collapse all Expand all
4444 def Feature3DNowA : SubtargetFeature<"3dnowa", "X863DNowLevel", "ThreeDNowA",
4545 "Enable 3DNow! Athlon instructions",
4646 [Feature3DNow]>;
47 // All x86-64 hardware has SSE2, but we don't mark SSE2 as an implied
48 // feature, because SSE2 can be disabled (e.g. for compiling OS kernels)
49 // without disabling 64-bit mode.
4750 def Feature64Bit : SubtargetFeature<"64bit", "HasX86_64", "true",
48 "Support 64-bit instructions",
49 [FeatureSSE2]>;
51 "Support 64-bit instructions">;
5052 def FeatureSlowBTMem : SubtargetFeature<"slow-bt-mem", "IsBTMemSlow", "true",
5153 "Bit testing of memory is slow">;
5254
6971 def : Proc<"pentium3", [FeatureSSE1]>;
7072 def : Proc<"pentium-m", [FeatureSSE2, FeatureSlowBTMem]>;
7173 def : Proc<"pentium4", [FeatureSSE2]>;
72 def : Proc<"x86-64", [Feature64Bit, FeatureSlowBTMem]>;
74 def : Proc<"x86-64", [FeatureSSE2, Feature64Bit, FeatureSlowBTMem]>;
7375 def : Proc<"yonah", [FeatureSSE3, FeatureSlowBTMem]>;
7476 def : Proc<"prescott", [FeatureSSE3, FeatureSlowBTMem]>;
7577 def : Proc<"nocona", [FeatureSSE3, Feature64Bit, FeatureSlowBTMem]>;
8688 def : Proc<"athlon-4", [FeatureSSE1, Feature3DNowA, FeatureSlowBTMem]>;
8789 def : Proc<"athlon-xp", [FeatureSSE1, Feature3DNowA, FeatureSlowBTMem]>;
8890 def : Proc<"athlon-mp", [FeatureSSE1, Feature3DNowA, FeatureSlowBTMem]>;
89 def : Proc<"k8", [Feature3DNowA, Feature64Bit, FeatureSlowBTMem]>;
90 def : Proc<"opteron", [Feature3DNowA, Feature64Bit, FeatureSlowBTMem]>;
91 def : Proc<"athlon64", [Feature3DNowA, Feature64Bit, FeatureSlowBTMem]>;
92 def : Proc<"athlon-fx", [Feature3DNowA, Feature64Bit, FeatureSlowBTMem]>;
91 def : Proc<"k8", [FeatureSSE2, Feature3DNowA, Feature64Bit,
92 FeatureSlowBTMem]>;
93 def : Proc<"opteron", [FeatureSSE2, Feature3DNowA, Feature64Bit,
94 FeatureSlowBTMem]>;
95 def : Proc<"athlon64", [FeatureSSE2, Feature3DNowA, Feature64Bit,
96 FeatureSlowBTMem]>;
97 def : Proc<"athlon-fx", [FeatureSSE2, Feature3DNowA, Feature64Bit,
98 FeatureSlowBTMem]>;
9399
94100 def : Proc<"winchip-c6", [FeatureMMX]>;
95101 def : Proc<"winchip2", [FeatureMMX, Feature3DNow]>;
326326 } else {
327327 // Otherwise, use CPUID to auto-detect feature set.
328328 AutoDetectSubtargetFeatures();
329 if (Is64Bit && X86SSELevel < SSE2) {
330 // Make sure SSE2 is enabled, it is available on all X86-64 CPUs.
329 // If requesting codegen for X86-64, make sure that 64-bit features
330 // are enabled.
331 if (Is64Bit)
332 HasX86_64 = true;
333 // Make sure SSE2 is enabled; it is available on all X86-64 CPUs.
334 if (Is64Bit && X86SSELevel < SSE2)
331335 X86SSELevel = SSE2;
332 }
333 }
334
335 // If requesting codegen for X86-64, make sure that 64-bit features
336 // are enabled.
337 if (Is64Bit) {
338 HasX86_64 = true;
339 }
340 assert(!Is64Bit || HasX86_64);
336 }
337
341338 DOUT << "Subtarget features: SSELevel " << X86SSELevel
342339 << ", 3DNowLevel " << X863DNowLevel
343340 << ", 64bit " << HasX86_64 << "\n";
341 assert((!Is64Bit || HasX86_64) &&
342 "64-bit code requested on a subtarget that doesn't support it!");
344343
345344 // Set the boolean corresponding to the current target triple, or the default
346345 // if one cannot be determined, to true.