llvm.org GIT mirror llvm / f738230
More cleanups for MachineOperand: - Eliminate the static "print" method for operands, moving it into MachineOperand::print. - Change various set* methods for register flags to take a bool for the value to set it to. Remove unset* methods. - Group methods more logically by operand flavor in MachineOperand.h git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@45461 91177308-0d34-0410-b5e6-96231b3b80d8 Chris Lattner 12 years ago
11 changed file(s) with 337 addition(s) and 322 deletion(s). Raw diff Collapse all Expand all
232232 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
233233 MachineOperand &MO = MI->getOperand(i);
234234 if (MO.isRegister() && MO.isKill() && MO.getReg() == reg) {
235 MO.unsetIsKill();
235 MO.setIsKill(false);
236236 Removed = true;
237237 break;
238238 }
277277 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
278278 MachineOperand &MO = MI->getOperand(i);
279279 if (MO.isRegister() && MO.isDef() && MO.getReg() == reg) {
280 MO.unsetIsDead();
280 MO.setIsDead(false);
281281 Removed = true;
282282 break;
283283 }
2020 namespace llvm {
2121
2222 class TargetInstrDescriptor;
23 class TargetMachine;
2423
2524 template struct ilist_traits;
2625 template struct ilist;
2222
2323 class MachineBasicBlock;
2424 class GlobalValue;
25 class MachineInstr;
25 class MachineInstr;
26 class TargetMachine;
2627
2728 /// MachineOperand class - Representation of each machine instruction operand.
2829 ///
7677
7778 MachineOperand() : ParentMI(0) {}
7879
79 void print(std::ostream &os) const;
80 void print(std::ostream *os) const { if (os) print(*os); }
81
8280 public:
8381 MachineOperand(const MachineOperand &M) {
8482 *this = M;
9593 MachineInstr *getParent() { return ParentMI; }
9694 const MachineInstr *getParent() const { return ParentMI; }
9795
96 void print(std::ostream &os, const TargetMachine *TM = 0) const;
97
9898 /// Accessors that tell you what kind of MachineOperand you're looking at.
9999 ///
100100 bool isRegister() const { return opType == MO_Register; }
106106 bool isGlobalAddress() const { return opType == MO_GlobalAddress; }
107107 bool isExternalSymbol() const { return opType == MO_ExternalSymbol; }
108108
109 //===--------------------------------------------------------------------===//
110 // Accessors for Register Operands
111 //===--------------------------------------------------------------------===//
112
113 /// getReg - Returns the register number.
114 unsigned getReg() const {
115 assert(isRegister() && "This is not a register operand!");
116 return contents.RegNo;
117 }
118
119 unsigned getSubReg() const {
120 assert(isRegister() && "Wrong MachineOperand accessor");
121 return (unsigned)SubReg;
122 }
123
124 bool isUse() const {
125 assert(isRegister() && "Wrong MachineOperand accessor");
126 return !IsDef;
127 }
128
129 bool isDef() const {
130 assert(isRegister() && "Wrong MachineOperand accessor");
131 return IsDef;
132 }
133
134 bool isImplicit() const {
135 assert(isRegister() && "Wrong MachineOperand accessor");
136 return IsImp;
137 }
138
139 bool isDead() const {
140 assert(isRegister() && "Wrong MachineOperand accessor");
141 return IsDead;
142 }
143
144 bool isKill() const {
145 assert(isRegister() && "Wrong MachineOperand accessor");
146 return IsKill;
147 }
148
149 //===--------------------------------------------------------------------===//
150 // Mutators for Register Operands
151 //===--------------------------------------------------------------------===//
152
153 void setReg(unsigned Reg) {
154 assert(isRegister() && "This is not a register operand!");
155 contents.RegNo = Reg;
156 }
157
158 void setSubReg(unsigned subReg) {
159 assert(isRegister() && "Wrong MachineOperand accessor");
160 SubReg = (unsigned char)subReg;
161 }
162
163 void setIsUse(bool Val = true) {
164 assert(isRegister() && "Wrong MachineOperand accessor");
165 IsDef = !Val;
166 }
167
168 void setIsDef(bool Val = true) {
169 assert(isRegister() && "Wrong MachineOperand accessor");
170 IsDef = Val;
171 }
172
173 void setImplicit(bool Val = true) {
174 assert(isRegister() && "Wrong MachineOperand accessor");
175 IsImp = Val;
176 }
177
178 void setIsKill(bool Val = true) {
179 assert(isRegister() && !IsDef && "Wrong MachineOperand accessor");
180 IsKill = Val;
181 }
182
183 void setIsDead(bool Val = true) {
184 assert(isRegister() && IsDef && "Wrong MachineOperand accessor");
185 IsDead = Val;
186 }
187
188
189 //===--------------------------------------------------------------------===//
190 // Accessors for various operand types.
191 //===--------------------------------------------------------------------===//
192
109193 int64_t getImm() const {
110194 assert(isImmediate() && "Wrong MachineOperand accessor");
111195 return contents.ImmVal;
141225 }
142226 int getOffset() const {
143227 assert((isGlobalAddress() || isExternalSymbol() || isConstantPoolIndex()) &&
144 "Wrong MachineOperand accessor");
228 "Wrong MachineOperand accessor");
145229 return auxInfo.offset;
146 }
147 unsigned getSubReg() const {
148 assert(isRegister() && "Wrong MachineOperand accessor");
149 return (unsigned)SubReg;
150230 }
151231 const char *getSymbolName() const {
152232 assert(isExternalSymbol() && "Wrong MachineOperand accessor");
153233 return contents.SymbolName;
154234 }
155
156 bool isUse() const {
157 assert(isRegister() && "Wrong MachineOperand accessor");
158 return !IsDef;
159 }
160 bool isDef() const {
161 assert(isRegister() && "Wrong MachineOperand accessor");
162 return IsDef;
163 }
164 void setIsUse() {
165 assert(isRegister() && "Wrong MachineOperand accessor");
166 IsDef = false;
167 }
168 void setIsDef() {
169 assert(isRegister() && "Wrong MachineOperand accessor");
170 IsDef = true;
171 }
172
173 bool isImplicit() const {
174 assert(isRegister() && "Wrong MachineOperand accessor");
175 return IsImp;
176 }
177 void setImplicit() {
178 assert(isRegister() && "Wrong MachineOperand accessor");
179 IsImp = true;
180 }
181
182 bool isKill() const {
183 assert(isRegister() && "Wrong MachineOperand accessor");
184 return IsKill;
185 }
186 bool isDead() const {
187 assert(isRegister() && "Wrong MachineOperand accessor");
188 return IsDead;
189 }
190 void setIsKill() {
191 assert(isRegister() && !IsDef && "Wrong MachineOperand accessor");
192 IsKill = true;
193 }
194 void setIsDead() {
195 assert(isRegister() && IsDef && "Wrong MachineOperand accessor");
196 IsDead = true;
197 }
198 void unsetIsKill() {
199 assert(isRegister() && !IsDef && "Wrong MachineOperand accessor");
200 IsKill = false;
201 }
202 void unsetIsDead() {
203 assert(isRegister() && IsDef && "Wrong MachineOperand accessor");
204 IsDead = false;
205 }
206
207 /// getReg - Returns the register number.
208 ///
209 unsigned getReg() const {
210 assert(isRegister() && "This is not a register operand!");
211 return contents.RegNo;
212 }
213
214 /// MachineOperand mutators.
215 ///
216 void setReg(unsigned Reg) {
217 assert(isRegister() && "This is not a register operand!");
218 contents.RegNo = Reg;
219 }
220
235
236 //===--------------------------------------------------------------------===//
237 // Mutators for various operand types.
238 //===--------------------------------------------------------------------===//
239
221240 void setImm(int64_t immVal) {
222241 assert(isImmediate() && "Wrong MachineOperand mutator");
223242 contents.ImmVal = immVal;
228247 "Wrong MachineOperand accessor");
229248 auxInfo.offset = Offset;
230249 }
231 void setSubReg(unsigned subReg) {
232 assert(isRegister() && "Wrong MachineOperand accessor");
233 SubReg = (unsigned char)subReg;
234 }
250
235251 void setConstantPoolIndex(unsigned Idx) {
236252 assert(isConstantPoolIndex() && "Wrong MachineOperand accessor");
237253 contents.Index = Idx;
238254 }
255
239256 void setJumpTableIndex(unsigned Idx) {
240257 assert(isJumpTableIndex() && "Wrong MachineOperand accessor");
241258 contents.Index = Idx;
242259 }
260
261 //===--------------------------------------------------------------------===//
262 // Other methods.
263 //===--------------------------------------------------------------------===//
243264
244265 /// isIdenticalTo - Return true if this operand is identical to the specified
245266 /// operand. Note: This method ignores isKill and isDead properties.
267288 SubReg = 0;
268289 }
269290
291 //===--------------------------------------------------------------------===//
292 // Construction methods.
293 //===--------------------------------------------------------------------===//
294
270295 static MachineOperand CreateImm(int64_t Val) {
271296 MachineOperand Op;
272297 Op.opType = MachineOperand::MO_Immediate;
273298 Op.contents.ImmVal = Val;
274299 return Op;
275300 }
301
276302 static MachineOperand CreateReg(unsigned Reg, bool isDef, bool isImp = false,
277303 bool isKill = false, bool isDead = false,
278304 unsigned SubReg = 0) {
338364 return *this;
339365 }
340366
341 friend std::ostream& operator<<(std::ostream& os, const MachineOperand& mop) {
342 mop.print(os);
343 return os;
344 }
345
346367 friend class MachineInstr;
347368 };
348369
349 std::ostream& operator<<(std::ostream &OS, const MachineOperand &MO);
370 inline std::ostream &operator<<(std::ostream &OS, const MachineOperand &MO) {
371 MO.print(OS, 0);
372 return OS;
373 }
350374
351375 } // End llvm namespace
352376
12121212 assert(KillMI && "Last use disappeared?");
12131213 int KillOp = KillMI->findRegisterUseOperandIdx(li.reg, true);
12141214 assert(KillOp != -1 && "Last use disappeared?");
1215 KillMI->getOperand(KillOp).unsetIsKill();
1215 KillMI->getOperand(KillOp).setIsKill(false);
12161216 }
12171217 vrm.removeKillPoint(li.reg);
12181218 bool DefIsReMat = vrm.isReMaterialized(li.reg);
607607 VarInfo &VI = getVarInfo(Reg);
608608 if (MO.isDef()) {
609609 if (MO.isDead()) {
610 MO.unsetIsDead();
610 MO.setIsDead(false);
611611 addVirtualRegisterDead(Reg, NewMI);
612612 }
613613 // Update the defining instruction.
615615 VI.DefInst = NewMI;
616616 }
617617 if (MO.isKill()) {
618 MO.unsetIsKill();
618 MO.setIsKill(false);
619619 addVirtualRegisterKilled(Reg, NewMI);
620620 }
621621 // If this is a kill of the value, update the VI kills list.
639639 unsigned Reg = MO.getReg();
640640 if (MO.isDef()) {
641641 if (MO.isDead()) {
642 MO.unsetIsDead();
642 MO.setIsDead(false);
643643 addRegisterDead(Reg, NewMI, RegInfo);
644644 }
645645 }
646646 if (MO.isKill()) {
647 MO.unsetIsKill();
647 MO.setIsKill(false);
648648 addRegisterKilled(Reg, NewMI, RegInfo);
649649 }
650650 }
658658 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
659659 MachineOperand &MO = MI->getOperand(i);
660660 if (MO.isRegister() && MO.isKill()) {
661 MO.unsetIsKill();
661 MO.setIsKill(false);
662662 unsigned Reg = MO.getReg();
663663 if (MRegisterInfo::isVirtualRegister(Reg)) {
664664 bool removed = getVarInfo(Reg).removeKill(MI);
674674 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
675675 MachineOperand &MO = MI->getOperand(i);
676676 if (MO.isRegister() && MO.isDead()) {
677 MO.unsetIsDead();
677 MO.setIsDead(false);
678678 unsigned Reg = MO.getReg();
679679 if (MRegisterInfo::isVirtualRegister(Reg)) {
680680 bool removed = getVarInfo(Reg).removeKill(MI);
2020 #include
2121 using namespace llvm;
2222
23 /// MachineInstr ctor - This constructor creates a dummy MachineInstr with
24 /// TID NULL and no operands.
25 MachineInstr::MachineInstr()
26 : TID(0), NumImplicitOps(0), parent(0) {
27 // Make sure that we get added to a machine basicblock
28 LeakDetector::addGarbageObject(this);
29 }
30
31 void MachineInstr::addImplicitDefUseOperands() {
32 if (TID->ImplicitDefs)
33 for (const unsigned *ImpDefs = TID->ImplicitDefs; *ImpDefs; ++ImpDefs)
34 addOperand(MachineOperand::CreateReg(*ImpDefs, true, true));
35 if (TID->ImplicitUses)
36 for (const unsigned *ImpUses = TID->ImplicitUses; *ImpUses; ++ImpUses)
37 addOperand(MachineOperand::CreateReg(*ImpUses, false, true));
38 }
39
40 /// MachineInstr ctor - This constructor create a MachineInstr and add the
41 /// implicit operands. It reserves space for number of operands specified by
42 /// TargetInstrDescriptor or the numOperands if it is not zero. (for
43 /// instructions with variable number of operands).
44 MachineInstr::MachineInstr(const TargetInstrDescriptor &tid, bool NoImp)
45 : TID(&tid), NumImplicitOps(0), parent(0) {
46 if (!NoImp && TID->ImplicitDefs)
47 for (const unsigned *ImpDefs = TID->ImplicitDefs; *ImpDefs; ++ImpDefs)
48 NumImplicitOps++;
49 if (!NoImp && TID->ImplicitUses)
50 for (const unsigned *ImpUses = TID->ImplicitUses; *ImpUses; ++ImpUses)
51 NumImplicitOps++;
52 Operands.reserve(NumImplicitOps + TID->numOperands);
53 if (!NoImp)
54 addImplicitDefUseOperands();
55 // Make sure that we get added to a machine basicblock
56 LeakDetector::addGarbageObject(this);
57 }
58
59 /// MachineInstr ctor - Work exactly the same as the ctor above, except that the
60 /// MachineInstr is created and added to the end of the specified basic block.
61 ///
62 MachineInstr::MachineInstr(MachineBasicBlock *MBB,
63 const TargetInstrDescriptor &tid)
64 : TID(&tid), NumImplicitOps(0), parent(0) {
65 assert(MBB && "Cannot use inserting ctor with null basic block!");
66 if (TID->ImplicitDefs)
67 for (const unsigned *ImpDefs = TID->ImplicitDefs; *ImpDefs; ++ImpDefs)
68 NumImplicitOps++;
69 if (TID->ImplicitUses)
70 for (const unsigned *ImpUses = TID->ImplicitUses; *ImpUses; ++ImpUses)
71 NumImplicitOps++;
72 Operands.reserve(NumImplicitOps + TID->numOperands);
73 addImplicitDefUseOperands();
74 // Make sure that we get added to a machine basicblock
75 LeakDetector::addGarbageObject(this);
76 MBB->push_back(this); // Add instruction to end of basic block!
77 }
78
79 /// MachineInstr ctor - Copies MachineInstr arg exactly
80 ///
81 MachineInstr::MachineInstr(const MachineInstr &MI) {
82 TID = MI.getInstrDescriptor();
83 NumImplicitOps = MI.NumImplicitOps;
84 Operands.reserve(MI.getNumOperands());
85
86 // Add operands
87 for (unsigned i = 0; i != MI.getNumOperands(); ++i) {
88 Operands.push_back(MI.getOperand(i));
89 Operands.back().ParentMI = this;
90 }
91
92 // Set parent, next, and prev to null
93 parent = 0;
94 prev = 0;
95 next = 0;
96 }
97
98
99 MachineInstr::~MachineInstr() {
100 LeakDetector::removeGarbageObject(this);
101 #ifndef NDEBUG
102 for (unsigned i = 0, e = Operands.size(); i != e; ++i)
103 assert(Operands[i].ParentMI == this && "ParentMI mismatch!");
104 #endif
105 }
106
107 /// getOpcode - Returns the opcode of this MachineInstr.
108 ///
109 int MachineInstr::getOpcode() const {
110 return TID->Opcode;
111 }
112
113 /// removeFromParent - This method unlinks 'this' from the containing basic
114 /// block, and returns it, but does not delete it.
115 MachineInstr *MachineInstr::removeFromParent() {
116 assert(getParent() && "Not embedded in a basic block!");
117 getParent()->remove(this);
118 return this;
119 }
120
121
122 /// OperandComplete - Return true if it's illegal to add a new operand
123 ///
124 bool MachineInstr::OperandsComplete() const {
125 unsigned short NumOperands = TID->numOperands;
126 if ((TID->Flags & M_VARIABLE_OPS) == 0 &&
127 getNumOperands()-NumImplicitOps >= NumOperands)
128 return true; // Broken: we have all the operands of this instruction!
129 return false;
130 }
131
132 /// getNumExplicitOperands - Returns the number of non-implicit operands.
133 ///
134 unsigned MachineInstr::getNumExplicitOperands() const {
135 unsigned NumOperands = TID->numOperands;
136 if ((TID->Flags & M_VARIABLE_OPS) == 0)
137 return NumOperands;
138
139 for (unsigned e = getNumOperands(); NumOperands != e; ++NumOperands) {
140 const MachineOperand &MO = getOperand(NumOperands);
141 if (!MO.isRegister() || !MO.isImplicit())
142 NumOperands++;
143 }
144 return NumOperands;
145 }
23 //===----------------------------------------------------------------------===//
24 // MachineOperand Implementation
25 //===----------------------------------------------------------------------===//
14626
14727 /// isIdenticalTo - Return true if this operand is identical to the specified
14828 /// operand.
17353 }
17454 }
17555
56 /// print - Print the specified machine operand.
57 ///
58 void MachineOperand::print(std::ostream &OS, const TargetMachine *TM) const {
59 switch (getType()) {
60 case MachineOperand::MO_Register:
61 if (getReg() == 0 || MRegisterInfo::isVirtualRegister(getReg())) {
62 OS << "%reg" << getReg();
63 } else {
64 // If the instruction is embedded into a basic block, we can find the
65 // target
66 // info for the instruction.
67 if (TM == 0)
68 if (const MachineInstr *MI = getParent())
69 if (const MachineBasicBlock *MBB = MI->getParent())
70 if (const MachineFunction *MF = MBB->getParent())
71 TM = &MF->getTarget();
72
73 if (TM)
74 OS << "%" << TM->getRegisterInfo()->get(getReg()).Name;
75 else
76 OS << "%mreg" << getReg();
77 }
78
79 if (isDef() || isKill() || isDead() || isImplicit()) {
80 OS << "<";
81 bool NeedComma = false;
82 if (isImplicit()) {
83 OS << (isDef() ? "imp-def" : "imp-use");
84 NeedComma = true;
85 } else if (isDef()) {
86 OS << "def";
87 NeedComma = true;
88 }
89 if (isKill() || isDead()) {
90 if (NeedComma) OS << ",";
91 if (isKill()) OS << "kill";
92 if (isDead()) OS << "dead";
93 }
94 OS << ">";
95 }
96 break;
97 case MachineOperand::MO_Immediate:
98 OS << getImm();
99 break;
100 case MachineOperand::MO_MachineBasicBlock:
101 OS << "mbb<"
102 << ((Value*)getMachineBasicBlock()->getBasicBlock())->getName()
103 << "," << (void*)getMachineBasicBlock() << ">";
104 break;
105 case MachineOperand::MO_FrameIndex:
106 OS << "";
107 break;
108 case MachineOperand::MO_ConstantPoolIndex:
109 OS << "
110 if (getOffset()) OS << "+" << getOffset();
111 OS << ">";
112 break;
113 case MachineOperand::MO_JumpTableIndex:
114 OS << "";
115 break;
116 case MachineOperand::MO_GlobalAddress:
117 OS << "getName();
118 if (getOffset()) OS << "+" << getOffset();
119 OS << ">";
120 break;
121 case MachineOperand::MO_ExternalSymbol:
122 OS << "
123 if (getOffset()) OS << "+" << getOffset();
124 OS << ">";
125 break;
126 default:
127 assert(0 && "Unrecognized operand type");
128 }
129 }
130
131 //===----------------------------------------------------------------------===//
132 // MachineInstr Implementation
133 //===----------------------------------------------------------------------===//
134
135 /// MachineInstr ctor - This constructor creates a dummy MachineInstr with
136 /// TID NULL and no operands.
137 MachineInstr::MachineInstr()
138 : TID(0), NumImplicitOps(0), parent(0) {
139 // Make sure that we get added to a machine basicblock
140 LeakDetector::addGarbageObject(this);
141 }
142
143 void MachineInstr::addImplicitDefUseOperands() {
144 if (TID->ImplicitDefs)
145 for (const unsigned *ImpDefs = TID->ImplicitDefs; *ImpDefs; ++ImpDefs)
146 addOperand(MachineOperand::CreateReg(*ImpDefs, true, true));
147 if (TID->ImplicitUses)
148 for (const unsigned *ImpUses = TID->ImplicitUses; *ImpUses; ++ImpUses)
149 addOperand(MachineOperand::CreateReg(*ImpUses, false, true));
150 }
151
152 /// MachineInstr ctor - This constructor create a MachineInstr and add the
153 /// implicit operands. It reserves space for number of operands specified by
154 /// TargetInstrDescriptor or the numOperands if it is not zero. (for
155 /// instructions with variable number of operands).
156 MachineInstr::MachineInstr(const TargetInstrDescriptor &tid, bool NoImp)
157 : TID(&tid), NumImplicitOps(0), parent(0) {
158 if (!NoImp && TID->ImplicitDefs)
159 for (const unsigned *ImpDefs = TID->ImplicitDefs; *ImpDefs; ++ImpDefs)
160 NumImplicitOps++;
161 if (!NoImp && TID->ImplicitUses)
162 for (const unsigned *ImpUses = TID->ImplicitUses; *ImpUses; ++ImpUses)
163 NumImplicitOps++;
164 Operands.reserve(NumImplicitOps + TID->numOperands);
165 if (!NoImp)
166 addImplicitDefUseOperands();
167 // Make sure that we get added to a machine basicblock
168 LeakDetector::addGarbageObject(this);
169 }
170
171 /// MachineInstr ctor - Work exactly the same as the ctor above, except that the
172 /// MachineInstr is created and added to the end of the specified basic block.
173 ///
174 MachineInstr::MachineInstr(MachineBasicBlock *MBB,
175 const TargetInstrDescriptor &tid)
176 : TID(&tid), NumImplicitOps(0), parent(0) {
177 assert(MBB && "Cannot use inserting ctor with null basic block!");
178 if (TID->ImplicitDefs)
179 for (const unsigned *ImpDefs = TID->ImplicitDefs; *ImpDefs; ++ImpDefs)
180 NumImplicitOps++;
181 if (TID->ImplicitUses)
182 for (const unsigned *ImpUses = TID->ImplicitUses; *ImpUses; ++ImpUses)
183 NumImplicitOps++;
184 Operands.reserve(NumImplicitOps + TID->numOperands);
185 addImplicitDefUseOperands();
186 // Make sure that we get added to a machine basicblock
187 LeakDetector::addGarbageObject(this);
188 MBB->push_back(this); // Add instruction to end of basic block!
189 }
190
191 /// MachineInstr ctor - Copies MachineInstr arg exactly
192 ///
193 MachineInstr::MachineInstr(const MachineInstr &MI) {
194 TID = MI.getInstrDescriptor();
195 NumImplicitOps = MI.NumImplicitOps;
196 Operands.reserve(MI.getNumOperands());
197
198 // Add operands
199 for (unsigned i = 0; i != MI.getNumOperands(); ++i) {
200 Operands.push_back(MI.getOperand(i));
201 Operands.back().ParentMI = this;
202 }
203
204 // Set parent, next, and prev to null
205 parent = 0;
206 prev = 0;
207 next = 0;
208 }
209
210
211 MachineInstr::~MachineInstr() {
212 LeakDetector::removeGarbageObject(this);
213 #ifndef NDEBUG
214 for (unsigned i = 0, e = Operands.size(); i != e; ++i)
215 assert(Operands[i].ParentMI == this && "ParentMI mismatch!");
216 #endif
217 }
218
219 /// getOpcode - Returns the opcode of this MachineInstr.
220 ///
221 int MachineInstr::getOpcode() const {
222 return TID->Opcode;
223 }
224
225 /// removeFromParent - This method unlinks 'this' from the containing basic
226 /// block, and returns it, but does not delete it.
227 MachineInstr *MachineInstr::removeFromParent() {
228 assert(getParent() && "Not embedded in a basic block!");
229 getParent()->remove(this);
230 return this;
231 }
232
233
234 /// OperandComplete - Return true if it's illegal to add a new operand
235 ///
236 bool MachineInstr::OperandsComplete() const {
237 unsigned short NumOperands = TID->numOperands;
238 if ((TID->Flags & M_VARIABLE_OPS) == 0 &&
239 getNumOperands()-NumImplicitOps >= NumOperands)
240 return true; // Broken: we have all the operands of this instruction!
241 return false;
242 }
243
244 /// getNumExplicitOperands - Returns the number of non-implicit operands.
245 ///
246 unsigned MachineInstr::getNumExplicitOperands() const {
247 unsigned NumOperands = TID->numOperands;
248 if ((TID->Flags & M_VARIABLE_OPS) == 0)
249 return NumOperands;
250
251 for (unsigned e = getNumOperands(); NumOperands != e; ++NumOperands) {
252 const MachineOperand &MO = getOperand(NumOperands);
253 if (!MO.isRegister() || !MO.isImplicit())
254 NumOperands++;
255 }
256 return NumOperands;
257 }
258
259
176260 /// findRegisterUseOperandIdx() - Returns the MachineOperand that is a use of
177261 /// the specific register or -1 if it is not found. It further tightening
178262 /// the search criteria to a use that kills the register if isKill is true.
266350 cerr << " " << *this;
267351 }
268352
269 /// print - Print the specified machine operand.
270 ///
271 static void print(const MachineOperand &MO, std::ostream &OS,
272 const TargetMachine *TM) {
273 switch (MO.getType()) {
274 case MachineOperand::MO_Register:
275 if (MO.getReg() == 0 || MRegisterInfo::isVirtualRegister(MO.getReg()))
276 OS << "%reg" << MO.getReg();
277 else {
278 // If the instruction is embedded into a basic block, we can find the
279 // target
280 // info for the instruction.
281 if (TM == 0)
282 if (const MachineInstr *MI = MO.getParent())
283 if (const MachineBasicBlock *MBB = MI->getParent())
284 if (const MachineFunction *MF = MBB->getParent())
285 TM = &MF->getTarget();
286
287 if (TM)
288 OS << "%" << TM->getRegisterInfo()->get(MO.getReg()).Name;
289 else
290 OS << "%mreg" << MO.getReg();
291 }
292
293 if (MO.isDef() || MO.isKill() || MO.isDead() || MO.isImplicit()) {
294 OS << "<";
295 bool NeedComma = false;
296 if (MO.isImplicit()) {
297 OS << (MO.isDef() ? "imp-def" : "imp-use");
298 NeedComma = true;
299 } else if (MO.isDef()) {
300 OS << "def";
301 NeedComma = true;
302 }
303 if (MO.isKill() || MO.isDead()) {
304 if (NeedComma) OS << ",";
305 if (MO.isKill()) OS << "kill";
306 if (MO.isDead()) OS << "dead";
307 }
308 OS << ">";
309 }
310 break;
311 case MachineOperand::MO_Immediate:
312 OS << MO.getImm();
313 break;
314 case MachineOperand::MO_MachineBasicBlock:
315 OS << "mbb<"
316 << ((Value*)MO.getMachineBasicBlock()->getBasicBlock())->getName()
317 << "," << (void*)MO.getMachineBasicBlock() << ">";
318 break;
319 case MachineOperand::MO_FrameIndex:
320 OS << "";
321 break;
322 case MachineOperand::MO_ConstantPoolIndex:
323 OS << "
324 if (MO.getOffset()) OS << "+" << MO.getOffset();
325 OS << ">";
326 break;
327 case MachineOperand::MO_JumpTableIndex:
328 OS << "";
329 break;
330 case MachineOperand::MO_GlobalAddress:
331 OS << "getName();
332 if (MO.getOffset()) OS << "+" << MO.getOffset();
333 OS << ">";
334 break;
335 case MachineOperand::MO_ExternalSymbol:
336 OS << "
337 if (MO.getOffset()) OS << "+" << MO.getOffset();
338 OS << ">";
339 break;
340 default:
341 assert(0 && "Unrecognized operand type");
342 }
343 }
344
345353 void MachineInstr::print(std::ostream &OS, const TargetMachine *TM) const {
346354 // Specialize printing if op#0 is definition
347355 unsigned StartOp = 0;
348356 if (getNumOperands() && getOperand(0).isRegister() && getOperand(0).isDef()) {
349 ::print(getOperand(0), OS, TM);
357 getOperand(0).print(OS, TM);
350358 OS << " = ";
351359 ++StartOp; // Don't print this operand again!
352360 }
357365 if (i != StartOp)
358366 OS << ",";
359367 OS << " ";
360 ::print(getOperand(i), OS, TM);
368 getOperand(i).print(OS, TM);
361369 }
362370
363371 OS << "\n";
364372 }
365373
366 void MachineOperand::print(std::ostream &OS) const {
367 ::print(*this, OS, 0);
368 }
369
184184 // merge, unset the isKill marker given the live range has been extended.
185185 int UIdx = ValLREndInst->findRegisterUseOperandIdx(IntB.reg, true);
186186 if (UIdx != -1)
187 ValLREndInst->getOperand(UIdx).unsetIsKill();
187 ValLREndInst->getOperand(UIdx).setIsKill(false);
188188
189189 ++numPeep;
190190 return true;
13021302 MachineOperand &MO = MI->getOperand(i);
13031303 if (MO.isRegister() && MO.isKill() && MO.getReg() &&
13041304 mri_->regsOverlap(rep(MO.getReg()), Reg))
1305 MO.unsetIsKill();
1305 MO.setIsKill(false);
13061306 }
13071307 }
13081308
13261326 MachineOperand &MO = MI->getOperand(i);
13271327 if (MO.isRegister() && MO.isKill() && MO.getReg() &&
13281328 mri_->regsOverlap(rep(MO.getReg()), Reg)) {
1329 MO.unsetIsKill();
1329 MO.setIsKill(false);
13301330 }
13311331 }
13321332
478478 static void InvalidateKill(unsigned Reg, BitVector &RegKills,
479479 std::vector &KillOps) {
480480 if (RegKills[Reg]) {
481 KillOps[Reg]->unsetIsKill();
481 KillOps[Reg]->setIsKill(false);
482482 KillOps[Reg] = NULL;
483483 RegKills.reset(Reg);
484484 }
546546 if (RegKills[Reg]) {
547547 // That can't be right. Register is killed but not re-defined and it's
548548 // being reused. Let's fix that.
549 KillOps[Reg]->unsetIsKill();
549 KillOps[Reg]->setIsKill(false);
550550 KillOps[Reg] = NULL;
551551 RegKills.reset(Reg);
552552 if (i < TID->numOperands &&
151151 bool Reg2IsKill = MI->getOperand(2).isKill();
152152 MI->getOperand(2).setReg(Reg1);
153153 MI->getOperand(1).setReg(Reg2);
154 if (Reg1IsKill)
155 MI->getOperand(2).setIsKill();
156 else
157 MI->getOperand(2).unsetIsKill();
158 if (Reg2IsKill)
159 MI->getOperand(1).setIsKill();
160 else
161 MI->getOperand(1).unsetIsKill();
154 MI->getOperand(2).setIsKill(Reg1IsKill);
155 MI->getOperand(1).setIsKill(Reg2IsKill);
162156
163157 // Swap the mask around.
164158 unsigned MB = MI->getOperand(4).getImm();
4848 bool Reg2IsKill = MI->getOperand(2).isKill();
4949 MI->getOperand(2).setReg(Reg1);
5050 MI->getOperand(1).setReg(Reg2);
51 if (Reg1IsKill)
52 MI->getOperand(2).setIsKill();
53 else
54 MI->getOperand(2).unsetIsKill();
55 if (Reg2IsKill)
56 MI->getOperand(1).setIsKill();
57 else
58 MI->getOperand(1).unsetIsKill();
51 MI->getOperand(2).setIsKill(Reg1IsKill);
52 MI->getOperand(1).setIsKill(Reg2IsKill);
5953 return MI;
6054 }
6155
13011301 for (unsigned i = 1; i != 5; ++i) {
13021302 MachineOperand &MO = NewMIs[0]->getOperand(i);
13031303 if (MO.isRegister())
1304 MO.unsetIsKill();
1304 MO.setIsKill(false);
13051305 }
13061306 }
13071307 }