llvm.org GIT mirror llvm / f7363d5
[AMDGPU] Assembler: refactor parsing of modifiers and immediates. Allow modifiers for imms. Reviewers: nhaustov, tstellarAMD Subscribers: kzhuravl, arsenm Differential Revision: http://reviews.llvm.org/D20166 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@270415 91177308-0d34-0410-b5e6-96231b3b80d8 Sam Kolton 4 years ago
11 changed file(s) with 309 addition(s) and 242 deletion(s). Raw diff Collapse all Expand all
179179 const MCExpr *Expr;
180180 };
181181
182 void addImmOperands(MCInst &Inst, unsigned N) const {
183 Inst.addOperand(MCOperand::createImm(getImm()));
182 void addImmOperands(MCInst &Inst, unsigned N, bool ApplyModifiers = true) const {
183 if (Imm.Type == ImmTyNone && ApplyModifiers && Imm.Modifiers != 0) {
184 // Apply modifiers to immediate value
185 int64_t Val = Imm.Val;
186 bool Negate = Imm.Modifiers & 0x1;
187 bool Abs = Imm.Modifiers & 0x2;
188 if (Imm.IsFPImm) {
189 APFloat F(BitsToFloat(Val));
190 if (Abs) {
191 F.clearSign();
192 }
193 if (Negate) {
194 F.changeSign();
195 }
196 Val = F.bitcastToAPInt().getZExtValue();
197 } else {
198 Val = Abs ? std::abs(Val) : Val;
199 Val = Negate ? -Val : Val;
200 }
201 Inst.addOperand(MCOperand::createImm(Val));
202 } else {
203 Inst.addOperand(MCOperand::createImm(getImm()));
204 }
184205 }
185206
186207 StringRef getToken() const {
204225 addRegOperands(Inst, N);
205226 } else {
206227 Inst.addOperand(MCOperand::createImm(Imm.Modifiers));
207 addImmOperands(Inst, N);
228 addImmOperands(Inst, N, false);
208229 }
209230 }
210231
645666 OperandVector &Operands);
646667 OperandMatchResultTy parseStringWithPrefix(const char *Prefix, StringRef &Value);
647668
669 OperandMatchResultTy parseImm(OperandVector &Operands);
670 OperandMatchResultTy parseRegOrImm(OperandVector &Operands);
671 OperandMatchResultTy parseRegOrImmWithInputMods(OperandVector &Operands);
672
648673 OperandMatchResultTy parseOptionalOperand(OperandVector &Operands, const OptionalOperand& Op, bool AddDefault);
649674 OperandMatchResultTy parseAMDGPUOperand(OperandVector &Operands, StringRef Name);
650675
937962 TRI, &getSTI(), false);
938963 }
939964
965 AMDGPUAsmParser::OperandMatchResultTy
966 AMDGPUAsmParser::parseImm(OperandVector &Operands) {
967 bool Minus = false;
968 if (getLexer().getKind() == AsmToken::Minus) {
969 Minus = true;
970 Parser.Lex();
971 }
972
973 SMLoc S = Parser.getTok().getLoc();
974 switch(getLexer().getKind()) {
975 case AsmToken::Integer: {
976 int64_t IntVal;
977 if (getParser().parseAbsoluteExpression(IntVal))
978 return MatchOperand_ParseFail;
979 if (!isInt<32>(IntVal) && !isUInt<32>(IntVal)) {
980 Error(S, "invalid immediate: only 32-bit values are legal");
981 return MatchOperand_ParseFail;
982 }
983
984 if (Minus)
985 IntVal *= -1;
986 Operands.push_back(AMDGPUOperand::CreateImm(IntVal, S));
987 return MatchOperand_Success;
988 }
989 case AsmToken::Real: {
990 // FIXME: We should emit an error if a double precisions floating-point
991 // value is used. I'm not sure the best way to detect this.
992 int64_t IntVal;
993 if (getParser().parseAbsoluteExpression(IntVal))
994 return MatchOperand_ParseFail;
995
996 APFloat F((float)BitsToDouble(IntVal));
997 if (Minus)
998 F.changeSign();
999 Operands.push_back(
1000 AMDGPUOperand::CreateImm(F.bitcastToAPInt().getZExtValue(), S,
1001 AMDGPUOperand::ImmTyNone, true));
1002 return MatchOperand_Success;
1003 }
1004 default:
1005 return Minus ? MatchOperand_ParseFail : MatchOperand_NoMatch;
1006 }
1007 }
1008
1009 AMDGPUAsmParser::OperandMatchResultTy
1010 AMDGPUAsmParser::parseRegOrImm(OperandVector &Operands) {
1011 auto res = parseImm(Operands);
1012 if (res != MatchOperand_NoMatch) {
1013 return res;
1014 }
1015
1016 if (auto R = parseRegister()) {
1017 assert(R->isReg());
1018 R->Reg.IsForcedVOP3 = isForcedVOP3();
1019 Operands.push_back(std::move(R));
1020 return MatchOperand_Success;
1021 }
1022 return MatchOperand_ParseFail;
1023 }
1024
1025 AMDGPUAsmParser::OperandMatchResultTy
1026 AMDGPUAsmParser::parseRegOrImmWithInputMods(OperandVector &Operands) {
1027 // XXX: During parsing we can't determine if minus sign means
1028 // negate-modifier or negative immediate value.
1029 // By default we suppose it is modifier.
1030 bool Negate = false, Abs = false, Abs2 = false;
1031
1032 if (getLexer().getKind()== AsmToken::Minus) {
1033 Parser.Lex();
1034 Negate = true;
1035 }
1036
1037 if (getLexer().getKind() == AsmToken::Identifier && Parser.getTok().getString() == "abs") {
1038 Parser.Lex();
1039 Abs2 = true;
1040 if (getLexer().isNot(AsmToken::LParen)) {
1041 Error(Parser.getTok().getLoc(), "expected left paren after abs");
1042 return MatchOperand_ParseFail;
1043 }
1044 Parser.Lex();
1045 }
1046
1047 if (getLexer().getKind() == AsmToken::Pipe) {
1048 if (Abs2) {
1049 Error(Parser.getTok().getLoc(), "expected register or immediate");
1050 return MatchOperand_ParseFail;
1051 }
1052 Parser.Lex();
1053 Abs = true;
1054 }
1055
1056 auto Res = parseRegOrImm(Operands);
1057 if (Res != MatchOperand_Success) {
1058 return Res;
1059 }
1060
1061 unsigned Modifiers = 0;
1062 if (Negate) {
1063 Modifiers |= 0x1;
1064 }
1065 if (Abs) {
1066 if (getLexer().getKind() != AsmToken::Pipe) {
1067 Error(Parser.getTok().getLoc(), "expected vertical bar");
1068 return MatchOperand_ParseFail;
1069 }
1070 Parser.Lex();
1071 Modifiers |= 0x2;
1072 }
1073 if (Abs2) {
1074 if (getLexer().isNot(AsmToken::RParen)) {
1075 Error(Parser.getTok().getLoc(), "expected closing parentheses");
1076 return MatchOperand_ParseFail;
1077 }
1078 Parser.Lex();
1079 Modifiers |= 0x2;
1080 }
1081
1082 if (Modifiers) {
1083 AMDGPUOperand &Op = static_cast(*Operands.back());
1084 Op.setModifiers(Modifiers);
1085 }
1086 return MatchOperand_Success;
1087 }
1088
1089
9401090 unsigned AMDGPUAsmParser::checkTargetMatchPredicate(MCInst &Inst) {
9411091
9421092 uint64_t TSFlags = MII.get(Inst.getOpcode()).TSFlags;
12711421 // If we are parsing after we reach EndOfStatement then this means we
12721422 // are appending default values to the Operands list. This is only done
12731423 // by custom parser, so we shouldn't continue on to the generic parsing.
1274 if (ResTy == MatchOperand_Success || ResTy == MatchOperand_ParseFail||
1424 if (ResTy == MatchOperand_Success || ResTy == MatchOperand_ParseFail ||
12751425 getLexer().is(AsmToken::EndOfStatement))
12761426 return ResTy;
12771427
1278 bool Negate = false, Abs = false, Abs2 = false;
1279
1280 if (getLexer().getKind()== AsmToken::Minus) {
1428 ResTy = parseRegOrImm(Operands);
1429
1430 if (ResTy == MatchOperand_Success)
1431 return ResTy;
1432
1433 if (getLexer().getKind() == AsmToken::Identifier) {
1434 const auto &Tok = Parser.getTok();
1435 Operands.push_back(AMDGPUOperand::CreateToken(Tok.getString(), Tok.getLoc()));
12811436 Parser.Lex();
1282 Negate = true;
1283 }
1284
1285 if (getLexer().getKind() == AsmToken::Identifier && Parser.getTok().getString() == "abs") {
1286 Parser.Lex();
1287 Abs2 = true;
1288 if (getLexer().isNot(AsmToken::LParen)) {
1289 Error(Parser.getTok().getLoc(), "expected left paren after abs");
1290 return MatchOperand_ParseFail;
1291 }
1292 Parser.Lex();
1293 }
1294
1295 if (getLexer().getKind() == AsmToken::Pipe) {
1296 Parser.Lex();
1297 Abs = true;
1298 }
1299
1300 switch(getLexer().getKind()) {
1301 case AsmToken::Integer: {
1302 SMLoc S = Parser.getTok().getLoc();
1303 int64_t IntVal;
1304 if (getParser().parseAbsoluteExpression(IntVal))
1305 return MatchOperand_ParseFail;
1306 if (!isInt<32>(IntVal) && !isUInt<32>(IntVal)) {
1307 Error(S, "invalid immediate: only 32-bit values are legal");
1308 return MatchOperand_ParseFail;
1309 }
1310
1311 if (Negate)
1312 IntVal *= -1;
1313 Operands.push_back(AMDGPUOperand::CreateImm(IntVal, S));
1314 return MatchOperand_Success;
1315 }
1316 case AsmToken::Real: {
1317 // FIXME: We should emit an error if a double precisions floating-point
1318 // value is used. I'm not sure the best way to detect this.
1319 SMLoc S = Parser.getTok().getLoc();
1320 int64_t IntVal;
1321 if (getParser().parseAbsoluteExpression(IntVal))
1322 return MatchOperand_ParseFail;
1323
1324 APFloat F((float)BitsToDouble(IntVal));
1325 if (Negate)
1326 F.changeSign();
1327 Operands.push_back(
1328 AMDGPUOperand::CreateImm(F.bitcastToAPInt().getZExtValue(), S));
1329 return MatchOperand_Success;
1330 }
1331 case AsmToken::LBrac:
1332 case AsmToken::Identifier: {
1333 if (auto R = parseRegister()) {
1334 unsigned Modifiers = 0;
1335
1336 if (Negate)
1337 Modifiers |= 0x1;
1338
1339 if (Abs) {
1340 if (getLexer().getKind() != AsmToken::Pipe)
1341 return MatchOperand_ParseFail;
1342 Parser.Lex();
1343 Modifiers |= 0x2;
1344 }
1345 if (Abs2) {
1346 if (getLexer().isNot(AsmToken::RParen)) {
1347 return MatchOperand_ParseFail;
1348 }
1349 Parser.Lex();
1350 Modifiers |= 0x2;
1351 }
1352 assert(R->isReg());
1353 R->Reg.IsForcedVOP3 = isForcedVOP3();
1354 if (Modifiers) {
1355 R->setModifiers(Modifiers);
1356 }
1357 Operands.push_back(std::move(R));
1358 } else {
1359 if (ResTy == MatchOperand_NoMatch) {
1360 const auto &Tok = Parser.getTok();
1361 Operands.push_back(AMDGPUOperand::CreateToken(Tok.getString(),
1362 Tok.getLoc()));
1363 Parser.Lex();
1364 if (getLexer().is(AsmToken::Colon)) {
1365 Parser.Lex();
1366 if (getLexer().is(AsmToken::Identifier)) {
1367 Parser.Lex();
1368 }
1369 }
1370 } else {
1371 return ResTy;
1372 }
1373 }
1374 return MatchOperand_Success;
1375 }
1376 default:
1377 return MatchOperand_NoMatch;
1378 }
1437 return MatchOperand_Success;
1438 }
1439 return MatchOperand_NoMatch;
13791440 }
13801441
13811442 bool AMDGPUAsmParser::ParseInstruction(ParseInstructionInfo &Info,
14031464 // Eat the comma or space if there is one.
14041465 if (getLexer().is(AsmToken::Comma))
14051466 Parser.Lex();
1406
1467
14071468 switch (Res) {
14081469 case MatchOperand_Success: break;
1409 case MatchOperand_ParseFail: return Error(getLexer().getLoc(),
1410 "failed parsing operand.");
1411 case MatchOperand_NoMatch: return Error(getLexer().getLoc(),
1412 "not a valid operand.");
1470 case MatchOperand_ParseFail:
1471 Error(getLexer().getLoc(), "failed parsing operand.");
1472 while (!getLexer().is(AsmToken::EndOfStatement)) {
1473 Parser.Lex();
1474 }
1475 return true;
1476 case MatchOperand_NoMatch:
1477 Error(getLexer().getLoc(), "not a valid operand.");
1478 while (!getLexer().is(AsmToken::EndOfStatement)) {
1479 Parser.Lex();
1480 }
1481 return true;
14131482 }
14141483 }
14151484
21872256 return parseNamedBit("lwe", Operands, AMDGPUOperand::ImmTyLWE);
21882257 }
21892258
2259 void AMDGPUAsmParser::cvtMIMG(MCInst &Inst, const OperandVector &Operands) {
2260 unsigned I = 1;
2261 const MCInstrDesc &Desc = MII.get(Inst.getOpcode());
2262 for (unsigned J = 0; J < Desc.getNumDefs(); ++J) {
2263 ((AMDGPUOperand &)*Operands[I++]).addRegOperands(Inst, 1);
2264 }
2265
2266 OptionalImmIndexMap OptionalIdx;
2267
2268 for (unsigned E = Operands.size(); I != E; ++I) {
2269 AMDGPUOperand &Op = ((AMDGPUOperand &)*Operands[I]);
2270
2271 // Add the register arguments
2272 if (Op.isRegOrImm()) {
2273 Op.addRegOrImmOperands(Inst, 1);
2274 continue;
2275 } else if (Op.isImmModifier()) {
2276 OptionalIdx[Op.getImmTy()] = I;
2277 } else {
2278 assert(false);
2279 }
2280 }
2281
2282 addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyDMask);
2283 addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyUNorm);
2284 addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyGLC);
2285 addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyDA);
2286 addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyR128);
2287 addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyTFE);
2288 addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyLWE);
2289 addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTySLC);
2290 }
2291
2292 void AMDGPUAsmParser::cvtMIMGAtomic(MCInst &Inst, const OperandVector &Operands) {
2293 unsigned I = 1;
2294 const MCInstrDesc &Desc = MII.get(Inst.getOpcode());
2295 for (unsigned J = 0; J < Desc.getNumDefs(); ++J) {
2296 ((AMDGPUOperand &)*Operands[I++]).addRegOperands(Inst, 1);
2297 }
2298
2299 // Add src, same as dst
2300 ((AMDGPUOperand &)*Operands[I]).addRegOperands(Inst, 1);
2301
2302 OptionalImmIndexMap OptionalIdx;
2303
2304 for (unsigned E = Operands.size(); I != E; ++I) {
2305 AMDGPUOperand &Op = ((AMDGPUOperand &)*Operands[I]);
2306
2307 // Add the register arguments
2308 if (Op.isRegOrImm()) {
2309 Op.addRegOrImmOperands(Inst, 1);
2310 continue;
2311 } else if (Op.isImmModifier()) {
2312 OptionalIdx[Op.getImmTy()] = I;
2313 } else {
2314 assert(false);
2315 }
2316 }
2317
2318 addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyDMask);
2319 addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyUNorm);
2320 addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyGLC);
2321 addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyDA);
2322 addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyR128);
2323 addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyTFE);
2324 addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyLWE);
2325 addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTySLC);
2326 }
2327
21902328 AMDGPUOperand::Ptr AMDGPUAsmParser::defaultDMask() const {
21912329 return AMDGPUOperand::CreateImm(0, SMLoc(), AMDGPUOperand::ImmTyDMask);
21922330 }
24032541
24042542 addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyClampSI);
24052543 addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyOModSI);
2406 }
2407
2408 void AMDGPUAsmParser::cvtMIMG(MCInst &Inst, const OperandVector &Operands) {
2409 unsigned I = 1;
2410 const MCInstrDesc &Desc = MII.get(Inst.getOpcode());
2411 for (unsigned J = 0; J < Desc.getNumDefs(); ++J) {
2412 ((AMDGPUOperand &)*Operands[I++]).addRegOperands(Inst, 1);
2413 }
2414
2415 OptionalImmIndexMap OptionalIdx;
2416
2417 for (unsigned E = Operands.size(); I != E; ++I) {
2418 AMDGPUOperand &Op = ((AMDGPUOperand &)*Operands[I]);
2419
2420 // Add the register arguments
2421 if (Op.isRegOrImm()) {
2422 Op.addRegOrImmOperands(Inst, 1);
2423 continue;
2424 } else if (Op.isImmModifier()) {
2425 OptionalIdx[Op.getImmTy()] = I;
2426 } else {
2427 assert(false);
2428 }
2429 }
2430
2431 addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyDMask);
2432 addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyUNorm);
2433 addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyGLC);
2434 addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTySLC);
2435 addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyR128);
2436 addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyTFE);
2437 addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyLWE);
2438 addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyDA);
2439 }
2440
2441 void AMDGPUAsmParser::cvtMIMGAtomic(MCInst &Inst, const OperandVector &Operands) {
2442 unsigned I = 1;
2443 const MCInstrDesc &Desc = MII.get(Inst.getOpcode());
2444 for (unsigned J = 0; J < Desc.getNumDefs(); ++J) {
2445 ((AMDGPUOperand &)*Operands[I++]).addRegOperands(Inst, 1);
2446 }
2447
2448 // Add src, same as dst
2449 ((AMDGPUOperand &)*Operands[I]).addRegOperands(Inst, 1);
2450
2451 OptionalImmIndexMap OptionalIdx;
2452
2453 for (unsigned E = Operands.size(); I != E; ++I) {
2454 AMDGPUOperand &Op = ((AMDGPUOperand &)*Operands[I]);
2455
2456 // Add the register arguments
2457 if (Op.isRegOrImm()) {
2458 Op.addRegOrImmOperands(Inst, 1);
2459 continue;
2460 } else if (Op.isImmModifier()) {
2461 OptionalIdx[Op.getImmTy()] = I;
2462 } else {
2463 assert(false);
2464 }
2465 }
2466
2467 addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyDMask);
2468 addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyUNorm);
2469 addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyGLC);
2470 addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyDA);
2471 addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyR128);
2472 addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyTFE);
2473 addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyLWE);
2474 addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTySLC);
24752544 }
24762545
24772546 //===----------------------------------------------------------------------===//
10971097
10981098 def InputModsMatchClass : AsmOperandClass {
10991099 let Name = "RegOrImmWithInputMods";
1100 let ParserMethod = "parseRegOrImmWithInputMods";
11001101 }
11011102
11021103 def InputModsNoDefault : Operand {
55 ds_add_u32 v2, v4 offset:1000000000
66
77 // offset0 twice
8 // CHECK: error: invalid operand for instruction
8 // CHECK: error: not a valid operand.
99 ds_write2_b32 v2, v4, v6 offset0:4 offset0:8
1010
1111 // offset1 twice
12 // CHECK: error: invalid operand for instruction
12 // CHECK: error: not a valid operand.
1313 ds_write2_b32 v2, v4, v6 offset1:4 offset1:8
1414
1515 // offset0 too big
None // RUN: not llvm-mc -arch=amdgcn -mcpu=tahiti -show-encoding %s 2>&1 | FileCheck -check-prefix=SI -check-prefix=GCN %s
0 // RUN: not llvm-mc -arch=amdgcn -mcpu=tahiti -show-encoding %s 2>&1 | FileCheck -check-prefix=NOSI %s
1 // RUN: not llvm-mc -arch=amdgcn -mcpu=hawaii -show-encoding %s 2>&1 | FileCheck -check-prefix=NOCI %s
2 // RUN: not llvm-mc -arch=amdgcn -mcpu=tonga -show-encoding %s 2>&1 | FileCheck -check-prefix=NOVI %s
13 // RUN: not llvm-mc -arch=amdgcn -mcpu=hawaii -show-encoding %s | FileCheck -check-prefix=CI %s
24 // RUN: not llvm-mc -arch=amdgcn -mcpu=tonga -show-encoding %s | FileCheck -check-prefix=VI %s
35
4 // Add a different RUN line for the failing checks, because when stderr and stdout are mixed the
5 // order things are printed is not deterministic.
6 // RUN: not llvm-mc -arch=amdgcn -mcpu=hawaii -show-encoding %s 2>&1 | FileCheck -check-prefix=GCN %s
7 // RUN: not llvm-mc -arch=amdgcn -mcpu=tonga -show-encoding %s 2>&1 | FileCheck -check-prefix=GCN %s
8
96 s_mov_b64 flat_scratch, -1
10 // SI: error: invalid operand for instruction
7 // NOSI: error: not a valid operand.
118 // CI: s_mov_b64 flat_scratch, -1 ; encoding: [0xc1,0x04,0xe8,0xbe]
129 // VI: s_mov_b64 flat_scratch, -1 ; encoding: [0xc1,0x01,0xe6,0xbe]
1310
1411 s_mov_b32 flat_scratch_lo, -1
15 // SI: error: invalid operand for instruction
12 // NOSI: error: not a valid operand.
1613 // CI: s_mov_b32 flat_scratch_lo, -1 ; encoding: [0xc1,0x03,0xe8,0xbe]
1714 // VI: s_mov_b32 flat_scratch_lo, -1 ; encoding: [0xc1,0x00,0xe6,0xbe]
1815
1916 s_mov_b32 flat_scratch_hi, -1
20 // SI: error: invalid operand for instruction
17 // NOSI: error: not a valid operand.
2118 // CI: s_mov_b32 flat_scratch_hi, -1 ; encoding: [0xc1,0x03,0xe9,0xbe]
2219 // VI: s_mov_b32 flat_scratch_hi, -1 ; encoding: [0xc1,0x00,0xe7,0xbe]
2320
2421
2522 s_mov_b64 flat_scratch_lo, -1
26 // GCN: error: invalid operand for instruction
23 // NOSI: error: not a valid operand.
24 // NOCI: error: invalid operand for instruction
25 // NOVI: error: invalid operand for instruction
2726
2827 s_mov_b64 flat_scratch_hi, -1
29 // GCN: error: invalid operand for instruction
28 // NOSI: error: not a valid operand.
29 // NOCI: error: invalid operand for instruction
30 // NOVI: error: invalid operand for instruction
3031
3132 s_mov_b32 flat_scratch, -1
32 // GCN: error: invalid operand for instruction
33 // NOSI: error: not a valid operand.
34 // NOCI: error: invalid operand for instruction
35 // NOVI: error: invalid operand for instruction
11 // RUN: not llvm-mc -arch=amdgcn -mcpu=tonga %s 2>&1 | FileCheck %s
22
33 s_add_i32 s104, s0, s1
4 // CHECK: error: invalid operand for instruction
4 // CHECK: error: not a valid operand
55
66 s_add_i32 s105, s0, s1
7 // CHECK: error: invalid operand for instruction
7 // CHECK: error: not a valid operand
88
99 v_add_i32 v256, v0, v1
10 // CHECK: error: invalid operand for instruction
10 // CHECK: error: not a valid operand
1111
1212 v_add_i32 v257, v0, v1
13 // CHECK: error: invalid operand for instruction
13 // CHECK: error: not a valid operand
1414
1515 s_mov_b64 s[0:17], -1
16 // CHECK: error: invalid operand for instruction
16 // CHECK: error: not a valid operand
1717
1818 s_mov_b64 s[103:104], -1
19 // CHECK: error: invalid operand for instruction
19 // CHECK: error: not a valid operand
2020
2121 s_mov_b64 s[104:105], -1
22 // CHECK: error: invalid operand for instruction
22 // CHECK: error: not a valid operand
2323
2424 s_load_dwordx4 s[102:105], s[2:3], s4
25 // CHECK: error: invalid operand for instruction
25 // CHECK: error: not a valid operand
2626
2727 s_load_dwordx4 s[104:108], s[2:3], s4
28 // CHECK: error: invalid operand for instruction
28 // CHECK: error: not a valid operand
2929
3030 s_load_dwordx4 s[108:112], s[2:3], s4
31 // CHECK: error: invalid operand for instruction
31 // CHECK: error: not a valid operand
3232
3333 s_load_dwordx4 s[1:4], s[2:3], s4
34 // CHECK: error: invalid operand for instruction
34 // CHECK: error: not a valid operand
3535
3636 s_load_dwordx4 s[1:4], s[2:3], s4
37 // CHECK: error: invalid operand for instruction
37 // CHECK: error: not a valid operand
3838
3939 s_load_dwordx8 s[104:111], s[2:3], s4
40 // CHECK: error: invalid operand for instruction
40 // CHECK: error: not a valid operand
4141
4242 s_load_dwordx8 s[100:107], s[2:3], s4
43 // CHECK: error: invalid operand for instruction
43 // CHECK: error: not a valid operand
4444
4545 s_load_dwordx8 s[108:115], s[2:3], s4
46 // CHECK: error: invalid operand for instruction
46 // CHECK: error: not a valid operand
4747
4848 s_load_dwordx16 s[92:107], s[2:3], s4
49 // CHECK: error: invalid operand for instruction
49 // CHECK: error: not a valid operand
5050
5151 s_load_dwordx16 s[96:111], s[2:3], s4
52 // CHECK: error: invalid operand for instruction
52 // CHECK: error: not a valid operand
5353
5454 s_load_dwordx16 s[100:115], s[2:3], s4
55 // CHECK: error: invalid operand for instruction
55 // CHECK: error: not a valid operand
5656
5757 s_load_dwordx16 s[104:119], s[2:3], s4
58 // CHECK: error: invalid operand for instruction
58 // CHECK: error: not a valid operand
5959
6060 s_load_dwordx16 s[108:123], s[2:3], s4
61 // CHECK: error: invalid operand for instruction
61 // CHECK: error: not a valid operand
11 // RUN: not llvm-mc -arch=amdgcn -mcpu=tonga %s 2>&1 | FileCheck -check-prefix=GCN -check-prefix=VI %s
22
33 s_load_dwordx4 s[100:103], s[2:3], s4
4 // VI: error: invalid operand for instruction
4 // VI: error: not a valid operand
55 // SI: s_load_dwordx4 s[100:103], s[2:3], s4
66
77
88 s_load_dwordx8 s[96:103], s[2:3], s4
9 // VI: error: invalid operand for instruction
9 // VI: error: not a valid operand
1010 // SI: s_load_dwordx8 s[96:103], s[2:3], s4
1111
1212 s_load_dwordx16 s[88:103], s[2:3], s4
13 // VI: error: invalid operand for instruction
13 // VI: error: not a valid operand
1414 // SI: s_load_dwordx16 s[88:103], s[2:3], s4
5757
5858 s_load_dwordx4 s[100:103], s[2:3], s4
5959 // GCN: s_load_dwordx4 s[100:103], s[2:3], s4 ; encoding: [0x04,0x02,0xb2,0xc0]
60 // NOVI: error: invalid operand for instruction
60 // NOVI: error: not a valid operand
6161
6262 s_load_dwordx8 s[8:15], s[2:3], 1
6363 // GCN: s_load_dwordx8 s[8:15], s[2:3], 0x1 ; encoding: [0x01,0x03,0xc4,0xc0]
6969
7070 s_load_dwordx8 s[96:103], s[2:3], s4
7171 // GCN: s_load_dwordx8 s[96:103], s[2:3], s4 ; encoding: [0x04,0x02,0xf0,0xc0]
72 // NOVI: error: invalid operand for instruction
72 // NOVI: error: not a valid operand
7373
7474 s_load_dwordx16 s[16:31], s[2:3], 1
7575 // GCN: s_load_dwordx16 s[16:31], s[2:3], 0x1 ; encoding: [0x01,0x03,0x08,0xc1]
8181
8282 s_load_dwordx16 s[88:103], s[2:3], s4
8383 // GCN: s_load_dwordx16 s[88:103], s[2:3], s4 ; encoding: [0x04,0x02,0x2c,0xc1]
84 // NOVI: error: invalid operand for instruction
84 // NOVI: error: not a valid operand
8585
8686 s_buffer_load_dword s1, s[4:7], 1
8787 // GCN: s_buffer_load_dword s1, s[4:7], 0x1 ; encoding: [0x01,0x85,0x00,0xc2]
117117
118118 s_buffer_load_dwordx4 s[100:103], s[4:7], s4
119119 // GCN: s_buffer_load_dwordx4 s[100:103], s[4:7], s4 ; encoding: [0x04,0x04,0xb2,0xc2]
120 // NOVI: error: invalid operand for instruction
120 // NOVI: error: not a valid operand
121121
122122 s_buffer_load_dwordx8 s[8:15], s[4:7], 1
123123 // GCN: s_buffer_load_dwordx8 s[8:15], s[4:7], 0x1 ; encoding: [0x01,0x05,0xc4,0xc2]
129129
130130 s_buffer_load_dwordx8 s[96:103], s[4:7], s4
131131 // GCN: s_buffer_load_dwordx8 s[96:103], s[4:7], s4 ; encoding: [0x04,0x04,0xf0,0xc2]
132 // NOVI: error: invalid operand for instruction
132 // NOVI: error: not a valid operand
133133
134134 s_buffer_load_dwordx16 s[16:31], s[4:7], 1
135135 // GCN: s_buffer_load_dwordx16 s[16:31], s[4:7], 0x1 ; encoding: [0x01,0x05,0x08,0xc3]
141141
142142 s_buffer_load_dwordx16 s[88:103], s[4:7], s4
143143 // GCN: s_buffer_load_dwordx16 s[88:103], s[4:7], s4 ; encoding: [0x04,0x04,0x2c,0xc3]
144 // NOVI: error: invalid operand for instruction
144 // NOVI: error: not a valid operand
145145
146146 s_dcache_inv
147147 // GCN: s_dcache_inv ; encoding: [0x00,0x00,0xc0,0xc7]
88 // GCN: error: invalid operand for instruction
99
1010 s_mov_b32 s[1:2], s0
11 // GCN: error: invalid operand for instruction
11 // GCN: error: not a valid operand
1212
1313 s_mov_b32 s0, s[1:2]
14 // GCN: error: invalid operand for instruction
14 // GCN: error: not a valid operand
1515
1616 s_mov_b32 s220, s0
17 // GCN: error: invalid operand for instruction
17 // GCN: error: not a valid operand
1818
1919 s_mov_b32 s0, s220
20 // GCN: error: invalid operand for instruction
20 // GCN: error: not a valid operand
2121
2222 s_mov_b64 s1, s[0:1]
2323 // GCN: error: invalid operand for instruction
3333 s_mov_b64 s[0:1], 0xfffffffff
3434 // GCN: error: invalid immediate: only 32-bit values are legal
3535
36 s_mov_b64 s[0:1], 0xfffffffff
37 // GCN: error: invalid immediate: only 32-bit values are legal
38
39 s_mov_b64 s[0:1], 0xfffffffff
40 // GCN: error: invalid immediate: only 32-bit values are legal
41
4236 s_mov_b64 s[0:1], 0x0000000200000000
4337 // GCN: error: invalid immediate: only 32-bit values are legal
4438
4539 // FIXME: This shoudl probably say failed to parse.
4640 s_mov_b32 s
47 // GCN: error: invalid operand for instruction
41 // GCN: error: not a valid operand
4842 // Out of range register
4943
5044 s_mov_b32 s102, 1
51 // VI: error: invalid operand for instruction
52 // SI-NOT: error
45 // VI: error: not a valid operand
46 // SI: s_mov_b32 s102, 1
5347
5448 s_mov_b32 s103, 1
55 // VI: error: invalid operand for instruction
56 // SI-NOT: error
49 // VI: error: not a valid operand
50 // SI: s_mov_b32 s103, 1
5751
5852 s_mov_b64 s[102:103], -1
59 // VI: error: invalid operand for instruction
60 // SI-NOT: error
53 // VI: error: not a valid operand
54 // SI: s_mov_b64 s[102:103], -1
4242
4343 s_mov_b64 s[102:103], -1
4444 // SICI: s_mov_b64 s[102:103], -1 ; encoding: [0xc1,0x04,0xe6,0xbe]
45 // NOVI: error: invalid operand for instruction
45 // NOVI: error: not a valid operand
4646
4747 s_cmov_b32 s1, 200
4848 // SICI: s_cmov_b32 s1, 0xc8 ; encoding: [0xff,0x05,0x81,0xbe,0xc8,0x00,0x00,0x00]
165165
166166 s_add_u32 s101, s102, s103
167167 // SICI: s_add_u32 s101, s102, s103 ; encoding: [0x66,0x67,0x65,0x80]
168 // NOVI: error: invalid operand for instruction
168 // NOVI: error: not a valid operand
338338 // VI: v_div_scale_f32 v24, vcc, v22, 1.0, v22 ; encoding: [0x18,0x6a,0xe0,0xd1,0x16,0xe5,0x59,0x04]
339339
340340 v_div_scale_f32 v24, vcc, v22, v22, -2.0
341 // SICI: v_div_scale_f32 v24, vcc, v22, v22, -2.0 ; encoding: [0x18,0x6a,0xda,0xd2,0x16,0x2d,0xd6,0x03]
342 // VI: v_div_scale_f32 v24, vcc, v22, v22, -2.0 ; encoding: [0x18,0x6a,0xe0,0xd1,0x16,0x2d,0xd6,0x03]
341 // SICI: v_div_scale_f32 v24, vcc, v22, v22, -2.0 ; encoding: [0x18,0x6a,0xda,0xd2,0x16,0x2d,0xd2,0x83]
342 // VI: v_div_scale_f32 v24, vcc, v22, v22, -2.0 ; encoding: [0x18,0x6a,0xe0,0xd1,0x16,0x2d,0xd2,0x83]
343343
344344 v_div_scale_f32 v24, vcc, v22, v22, 0xc0000000
345345 // SICI: v_div_scale_f32 v24, vcc, v22, v22, -2.0 ; encoding: [0x18,0x6a,0xda,0xd2,0x16,0x2d,0xd6,0x03]