llvm.org GIT mirror llvm / f716895
[ARM] Small refactor of tryConvertingToTwoOperandForm (nfc) Also, add more Thumb2 ADD tests requested during review of http://reviews.llvm.org/D11053. Differential Revision: http://reviews.llvm.org/D11130 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@242034 91177308-0d34-0410-b5e6-96231b3b80d8 Scott Douglass 5 years ago
2 changed file(s) with 87 addition(s) and 10 deletion(s). Raw diff Collapse all Expand all
54765476 if (Operands.size() != 6)
54775477 return;
54785478
5479 ARMOperand &Op3 = static_cast(*Operands[3]);
5480 ARMOperand &Op4 = static_cast(*Operands[4]);
5479 const auto &Op3 = static_cast(*Operands[3]);
5480 auto &Op4 = static_cast(*Operands[4]);
54815481 if (!Op3.isReg() || !Op4.isReg())
54825482 return;
5483
5484 auto Op3Reg = Op3.getReg();
5485 auto Op4Reg = Op4.getReg();
54835486
54845487 // For most Thumb2 cases we just generate the 3 operand form and reduce
54855488 // it in processInstruction(), but for ADD involving PC the the 3 operand
54865489 // form won't accept PC so we do the transformation here.
5487 ARMOperand &Op5 = static_cast(*Operands[5]);
5490 auto &Op5 = static_cast(*Operands[5]);
54885491 if (isThumbTwo()) {
54895492 if (Mnemonic != "add" ||
5490 !(Op3.getReg() == ARM::PC || Op4.getReg() == ARM::PC ||
5493 !(Op3Reg == ARM::PC || Op4Reg == ARM::PC ||
54915494 (Op5.isReg() && Op5.getReg() == ARM::PC)))
54925495 return;
54935496 } else if (!isThumbOne())
55025505 // If first 2 operands of a 3 operand instruction are the same
55035506 // then transform to 2 operand version of the same instruction
55045507 // e.g. 'adds r0, r0, #1' transforms to 'adds r0, #1'
5505 bool Transform = Op3.getReg() == Op4.getReg();
5508 bool Transform = Op3Reg == Op4Reg;
55065509
55075510 // For communtative operations, we might be able to transform if we swap
55085511 // Op4 and Op5. The 'ADD Rdm, SP, Rdm' form is already handled specially
55095512 // as tADDrsp.
55105513 const ARMOperand *LastOp = &Op5;
55115514 bool Swap = false;
5512 if (!Transform && Op5.isReg() && Op3.getReg() == Op5.getReg() &&
5513 ((Mnemonic == "add" && Op4.getReg() != ARM::SP) ||
5515 if (!Transform && Op5.isReg() && Op3Reg == Op5.getReg() &&
5516 ((Mnemonic == "add" && Op4Reg != ARM::SP) ||
55145517 Mnemonic == "and" || Mnemonic == "eor" ||
55155518 Mnemonic == "adc" || Mnemonic == "orr")) {
55165519 Swap = true;
4848 adcs r0, r1, r3, lsl #7
4949 adc.w r0, r1, r3, lsr #31
5050 adcs.w r0, r1, r3, asr #32
51 add r2, sp, ip
5251
5352 @ CHECK: adc.w r4, r5, r6 @ encoding: [0x45,0xeb,0x06,0x04]
5453 @ CHECK: adcs.w r4, r5, r6 @ encoding: [0x55,0xeb,0x06,0x04]
5857 @ CHECK: adcs.w r0, r1, r3, lsl #7 @ encoding: [0x51,0xeb,0xc3,0x10]
5958 @ CHECK: adc.w r0, r1, r3, lsr #31 @ encoding: [0x41,0xeb,0xd3,0x70]
6059 @ CHECK: adcs.w r0, r1, r3, asr #32 @ encoding: [0x51,0xeb,0x23,0x00]
61 @ CHECK: add.w r2, sp, r12 @ encoding: [0x0d,0xeb,0x0c,0x02]
6260
6361
6462 @------------------------------------------------------------------------------
114112
115113
116114 @------------------------------------------------------------------------------
117 @ ADD (register)
115 @ ADD (register, not SP) A8.8.6
118116 @------------------------------------------------------------------------------
119117 add r1, r2, r8
120118 add r5, r9, r2, asr #32
121119 adds r7, r3, r1, lsl #31
122120 adds.w r0, r3, r6, lsr #25
123121 add.w r4, r8, r1, ror #12
122 adds r1, r1, r7 // T1
123 it eq
124 addeq r1, r3, r5 // T1
125 it eq
126 addeq r1, r1, r5 // T1
127 it eq
128 addseq r1, r3, r5 // T3
129 it eq
130 addseq r1, r1, r5 // T3
124131 add r10, r8
125132 add r10, r10, r8
133 it eq
134 addeq r1, r10 // T2
135 it eq
136 addseq r1, r10 // T3
126137
127138 @ CHECK: add.w r1, r2, r8 @ encoding: [0x02,0xeb,0x08,0x01]
128139 @ CHECK: add.w r5, r9, r2, asr #32 @ encoding: [0x09,0xeb,0x22,0x05]
129140 @ CHECK: adds.w r7, r3, r1, lsl #31 @ encoding: [0x13,0xeb,0xc1,0x77]
130141 @ CHECK: adds.w r0, r3, r6, lsr #25 @ encoding: [0x13,0xeb,0x56,0x60]
131142 @ CHECK: add.w r4, r8, r1, ror #12 @ encoding: [0x08,0xeb,0x31,0x34]
143 @ CHECK: adds r1, r1, r7 @ encoding: [0xc9,0x19]
144 @ CHECK: it eq @ encoding: [0x08,0xbf]
145 @ CHECK: addeq r1, r3, r5 @ encoding: [0x59,0x19]
146 @ CHECK: it eq @ encoding: [0x08,0xbf]
147 @ CHECK: addeq r1, r1, r5 @ encoding: [0x49,0x19]
148 @ CHECK: it eq @ encoding: [0x08,0xbf]
149 @ CHECK: addseq.w r1, r3, r5 @ encoding: [0x13,0xeb,0x05,0x01]
150 @ CHECK: it eq @ encoding: [0x08,0xbf]
151 @ CHECK: addseq.w r1, r1, r5 @ encoding: [0x11,0xeb,0x05,0x01]
132152 @ CHECK: add r10, r8 @ encoding: [0xc2,0x44]
133153 @ CHECK: add r10, r8 @ encoding: [0xc2,0x44]
154 @ CHECK: it eq @ encoding: [0x08,0xbf]
155 @ CHECK: addeq r1, r10 @ encoding: [0x51,0x44]
156 @ CHECK: it eq @ encoding: [0x08,0xbf]
157 @ CHECK: addseq.w r1, r1, r10 @ encoding: [0x11,0xeb,0x0a,0x01]
158
159 @------------------------------------------------------------------------------
160 @ ADD (SP plus immediate) A8.8.9
161 @------------------------------------------------------------------------------
162 it eq
163 @ CHECK: it eq @ encoding: [0x08,0xbf]
164 addeq r7, sp, #1020 // T1
165 @ CHECK: addeq r7, sp, #1020 @ encoding: [0xff,0xaf]
166
167 it eq
168 @ CHECK: it eq @ encoding: [0x08,0xbf]
169 addeq sp, sp, #508 // T2
170 @ FIXME: ARMARM says 'addeq sp, sp, #508'
171 @ CHECK: addeq sp, #508 @ encoding: [0x7f,0xb0]
172
173 add r7, sp, #15 // T3
174 @ CHECK: add.w r7, sp, #15 @ encoding: [0x0d,0xf1,0x0f,0x07]
175 adds r7, sp, #16 // T3
176 @ CHECK: adds.w r7, sp, #16 @ encoding: [0x1d,0xf1,0x10,0x07]
177 add r8, sp, #16 // T3
178 @ CHECK: add.w r8, sp, #16 @ encoding: [0x0d,0xf1,0x10,0x08]
179
180 addw r6, sp, #1020 // T4
181 @ CHECK: addw r6, sp, #1020 @ encoding: [0x0d,0xf2,0xfc,0x36]
182 add r6, sp, #1019 // T4
183 @ CHECK: addw r6, sp, #1019 @ encoding: [0x0d,0xf2,0xfb,0x36]
184
185 @------------------------------------------------------------------------------
186 @ ADD (SP plus register) A8.8.10
187 @------------------------------------------------------------------------------
188 it eq
189 @ CHECK: it eq @ encoding: [0x08,0xbf]
190 addeq r8, sp, r8 // T1
191 @ CHECK: addeq r8, sp, r8 @ encoding: [0xe8,0x44]
192 it eq
193 @ CHECK: it eq @ encoding: [0x08,0xbf]
194 addeq r8, sp // T1
195 @ CHECK: addeq r8, sp @ encoding: [0xe8,0x44]
196
197 it eq
198 @ CHECK: it eq @ encoding: [0x08,0xbf]
199 addeq sp, r9 // T2
200 @ CHECK: addeq sp, r9 @ encoding: [0xcd,0x44]
201
202 add r2, sp, ip // T3
203 @ CHECK: add.w r2, sp, r12 @ encoding: [0x0d,0xeb,0x0c,0x02]
204 it eq
205 @ CHECK: it eq @ encoding: [0x08,0xbf]
206 addeq r2, sp, ip // T3
207 @ CHECK: addeq.w r2, sp, r12 @ encoding: [0x0d,0xeb,0x0c,0x02]
134208
135209
136210 @------------------------------------------------------------------------------