llvm.org GIT mirror llvm / f711939
Instead of adding dependence edges between terminator instructions and every other instruction in their blocks to keep the terminator instructions at the end, teach the post-RA scheduler how to operate on ranges of instructions, and exclude terminators from the range of instructions that get scheduled. Also, exclude mid-block labels, such as EH_LABEL instructions, and schedule code before them separately from code after them. This fixes problems with the post-RA scheduler moving code past EH_LABELs. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62366 91177308-0d34-0410-b5e6-96231b3b80d8 Dan Gohman 11 years ago
7 changed file(s) with 71 addition(s) and 27 deletion(s). Raw diff Collapse all Expand all
417417 public:
418418 SelectionDAG *DAG; // DAG of the current basic block
419419 MachineBasicBlock *BB; // Current basic block
420 MachineBasicBlock::iterator Begin; // The beginning of the range to be scheduled.
421 MachineBasicBlock::iterator End; // The end of the range to be scheduled.
420422 const TargetMachine &TM; // Target processor
421423 const TargetInstrInfo *TII; // Target instruction information
422424 const TargetRegisterInfo *TRI; // Target processor register info
439441
440442 /// Run - perform scheduling.
441443 ///
442 void Run(SelectionDAG *DAG, MachineBasicBlock *MBB);
444 void Run(SelectionDAG *DAG, MachineBasicBlock *MBB,
445 MachineBasicBlock::iterator Begin,
446 MachineBasicBlock::iterator End);
443447
444448 /// BuildSchedGraph - Build SUnits and set up their Preds and Succs
445449 /// to form the scheduling dependency graph.
186186 // Loop over all of the basic blocks
187187 for (MachineFunction::iterator MBB = Fn.begin(), MBBe = Fn.end();
188188 MBB != MBBe; ++MBB) {
189
190 Scheduler.Run(0, MBB);
191
189 // Schedule each sequence of instructions not interrupted by a label
190 // or anything else that effectively needs to shut down scheduling.
191 MachineBasicBlock::iterator Current = MBB->begin(), End = MBB->end();
192 for (MachineBasicBlock::iterator MI = Current; MI != End; ++MI)
193 if (MI->getDesc().isTerminator() || MI->isLabel()) {
194 Scheduler.Run(0, MBB, Current, MI);
195 Scheduler.EmitSchedule();
196 Current = next(MI);
197 }
198
199 Scheduler.Run(0, MBB, Current, End);
192200 Scheduler.EmitSchedule();
193201 }
194202
4545
4646 /// Run - perform scheduling.
4747 ///
48 void ScheduleDAG::Run(SelectionDAG *dag, MachineBasicBlock *bb) {
48 void ScheduleDAG::Run(SelectionDAG *dag, MachineBasicBlock *bb,
49 MachineBasicBlock::iterator begin,
50 MachineBasicBlock::iterator end) {
51 assert((!dag || begin == end) &&
52 "An instruction range was given for SelectionDAG scheduling!");
53
4954 SUnits.clear();
5055 Sequence.clear();
5156 DAG = dag;
5257 BB = bb;
58 Begin = begin;
59 End = end;
5360
5461 Schedule();
5562
3232 }
3333
3434 void ScheduleDAG::EmitNoop() {
35 TII->insertNoop(*BB, BB->end());
35 TII->insertNoop(*BB, End);
3636 }
3737
3838 void ScheduleDAG::EmitPhysRegCopy(SUnit *SU,
5353 break;
5454 }
5555 }
56 TII->copyRegToReg(*BB, BB->end(), Reg, VRI->second,
56 TII->copyRegToReg(*BB, End, Reg, VRI->second,
5757 SU->CopyDstRC, SU->CopySrcRC);
5858 } else {
5959 // Copy from physical register.
6262 bool isNew = VRBaseMap.insert(std::make_pair(SU, VRBase)).second;
6363 isNew = isNew; // Silence compiler warning.
6464 assert(isNew && "Node emitted out of order - early");
65 TII->copyRegToReg(*BB, BB->end(), VRBase, I->getReg(),
65 TII->copyRegToReg(*BB, End, VRBase, I->getReg(),
6666 SU->CopyDstRC, SU->CopySrcRC);
6767 }
6868 break;
111111 std::map MemDefs;
112112 std::map > MemUses;
113113
114 // If we have an SUnit which is representing a terminator instruction, we
115 // can use it as a place-holder successor for inter-block dependencies.
116 SUnit *Terminator = 0;
117
114118 // Terminators can perform control transfers, we we need to make sure that
115 // all the work of the block is done before the terminator.
116 SUnit *Terminator = 0;
119 // all the work of the block is done before the terminator. Labels can
120 // mark points of interest for various types of meta-data (eg. EH data),
121 // and we need to make sure nothing is scheduled around them.
122 SUnit *SchedulingBarrier = 0;
117123
118124 LoopDependencies LoopRegs(MLI, MDT);
119125
136142 unsigned SpecialAddressLatency =
137143 TM.getSubtarget().getSpecialAddressLatency();
138144
139 for (MachineBasicBlock::iterator MII = BB->end(), MIE = BB->begin();
145 for (MachineBasicBlock::iterator MII = End, MIE = Begin;
140146 MII != MIE; --MII) {
141147 MachineInstr *MI = prior(MII);
142148 const TargetInstrDesc &TID = MI->getDesc();
367373 }
368374 }
369375
370 // Add chain edges from the terminator to ensure that all the work of the
371 // block is completed before any control transfers.
372 if (Terminator && SU->Succs.empty())
373 Terminator->addPred(SDep(SU, SDep::Order, SU->Latency));
376 // Add chain edges from terminators and labels to ensure that no
377 // instructions are scheduled past them.
378 if (SchedulingBarrier && SU->Succs.empty())
379 SchedulingBarrier->addPred(SDep(SU, SDep::Order, SU->Latency));
380 // If we encounter a mid-block label, we need to go back and add
381 // dependencies on SUnits we've already processed to prevent the
382 // label from moving downward.
383 if (MI->isLabel())
384 for (SUnit *I = SU; I != &SUnits[0]; --I) {
385 SUnit *SuccSU = SU-1;
386 SuccSU->addPred(SDep(SU, SDep::Order, SU->Latency));
387 MachineInstr *SuccMI = SuccSU->getInstr();
388 if (SuccMI->getDesc().isTerminator() || SuccMI->isLabel())
389 break;
390 }
391 // If this instruction obstructs all scheduling, remember it.
374392 if (TID.isTerminator() || MI->isLabel())
393 SchedulingBarrier = SU;
394 // If this instruction is a terminator, remember it.
395 if (TID.isTerminator())
375396 Terminator = SU;
376397 }
377398
412433 MachineBasicBlock *ScheduleDAGInstrs::EmitSchedule() {
413434 // For MachineInstr-based scheduling, we're rescheduling the instructions in
414435 // the block, so start by removing them from the block.
415 while (!BB->empty())
416 BB->remove(BB->begin());
436 while (Begin != End) {
437 MachineBasicBlock::iterator I = Begin;
438 ++Begin;
439 BB->remove(I);
440 }
417441
418442 // Then re-insert them according to the given schedule.
419443 for (unsigned i = 0, e = Sequence.size(); i != e; i++) {
424448 continue;
425449 }
426450
427 BB->push_back(SU->getInstr());
451 BB->insert(End, SU->getInstr());
428452 }
429453
430454 return BB;
126126 // Create the reg, emit the copy.
127127 VRBase = MRI.createVirtualRegister(DstRC);
128128 bool Emitted =
129 TII->copyRegToReg(*BB, BB->end(), VRBase, SrcReg, DstRC, SrcRC);
129 TII->copyRegToReg(*BB, End, VRBase, SrcReg, DstRC, SrcRC);
130130 Emitted = Emitted; // Silence compiler warning.
131131 assert(Emitted && "Unable to issue a copy instruction!");
132132 }
409409 MI->addOperand(MachineOperand::CreateReg(VRBase, true));
410410 AddOperand(MI, Node->getOperand(0), 0, 0, VRBaseMap);
411411 MI->addOperand(MachineOperand::CreateImm(SubIdx));
412 BB->push_back(MI);
412 BB->insert(End, MI);
413413 } else if (Opc == TargetInstrInfo::INSERT_SUBREG ||
414414 Opc == TargetInstrInfo::SUBREG_TO_REG) {
415415 SDValue N0 = Node->getOperand(0);
444444 // Add the subregster being inserted
445445 AddOperand(MI, N1, 0, 0, VRBaseMap);
446446 MI->addOperand(MachineOperand::CreateImm(SubIdx));
447 BB->push_back(MI);
447 BB->insert(End, MI);
448448 } else
449449 assert(0 && "Node is not insert_subreg, extract_subreg, or subreg_to_reg");
450450
504504 for (unsigned i = NodeOperands; i != MemOperandsEnd; ++i)
505505 AddMemOperand(MI, cast(Node->getOperand(i))->MO);
506506
507 if (II.usesCustomDAGSchedInsertionHook())
507 if (II.usesCustomDAGSchedInsertionHook()) {
508508 // Insert this instruction into the basic block using a target
509509 // specific inserter which may returns a new basic block.
510510 BB = TLI->EmitInstrWithCustomInserter(MI, BB);
511 else
512 BB->push_back(MI);
511 Begin = End = BB->end();
512 } else
513 BB->insert(End, MI);
513514
514515 // Additional results must be an physical register def.
515516 if (HasPhysRegOuts) {
558559 else
559560 DstTRC = TRI->getPhysicalRegisterRegClass(DestReg,
560561 Node->getOperand(1).getValueType());
561 TII->copyRegToReg(*BB, BB->end(), DestReg, SrcReg, DstTRC, SrcTRC);
562 TII->copyRegToReg(*BB, End, DestReg, SrcReg, DstTRC, SrcTRC);
562563 break;
563564 }
564565 case ISD::CopyFromReg: {
613614 break;
614615 }
615616 }
616 BB->push_back(MI);
617 BB->insert(End, MI);
617618 break;
618619 }
619620 }
10731073 }
10741074
10751075 ScheduleDAG *Scheduler = Ctor(this, Fast);
1076 Scheduler->Run(CurDAG, BB);
1076 Scheduler->Run(CurDAG, BB, BB->end(), BB->end());
10771077
10781078 return Scheduler;
10791079 }