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Fix PR4567. Thumb1 target was using the wrong instruction to handle sp = sub fp, #c. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@76401 91177308-0d34-0410-b5e6-96231b3b80d8 Evan Cheng 10 years ago
2 changed file(s) with 15 addition(s) and 3 deletion(s). Raw diff Collapse all Expand all
243243 Make use of hi register variants of cmp: tCMPhir / tCMPZhir.
244244
245245 //===---------------------------------------------------------------------===//
246
247 Thumb1 immediate field sometimes keep pre-scaled values. See
248 Thumb1RegisterInfo::eliminateFrameIndex. This is inconsistent from ARM and
249 Thumb2.
230230 if (DestReg != BaseReg)
231231 DstNotEqBase = true;
232232 NumBits = 8;
233 Opc = isSub ? ARM::tSUBi8 : ARM::tADDi8;
234 NeedPred = NeedCC = true;
233 if (DestReg == ARM::SP) {
234 Opc = isSub ? ARM::tSUBspi : ARM::tADDspi;
235 assert(isMul4 && "Thumb sp inc / dec size must be multiple of 4!");
236 NumBits = 7;
237 Scale = 4;
238 } else {
239 Opc = isSub ? ARM::tSUBi8 : ARM::tADDi8;
240 NumBits = 8;
241 NeedPred = NeedCC = true;
242 }
235243 isTwoAddr = true;
236244 }
237245
446454 removeOperands(MI, i);
447455 MachineInstrBuilder MIB(&MI);
448456 AddDefaultPred(AddDefaultT1CC(MIB).addReg(FrameReg)
449 .addImm(Offset/Scale));
457 .addImm(Offset / Scale));
450458 } else {
451459 MI.getOperand(i).ChangeToRegister(FrameReg, false);
452460 MI.getOperand(i+1).ChangeToImmediate(Offset / Scale);