llvm.org GIT mirror llvm / f6f8198
Use virtual base registers on PPC On PowerPC, non-vector loads and stores have r+i forms; however, in functions with large stack frames these were not being used to access slots far from the stack pointer because such slots were out of range for the signed 16-bit immediate offset field. This increases register pressure because we need a separate register for each offset (when the r+r form is used). By enabling virtual base registers, we can deal with large stack frames without unduly increasing register pressure. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@179105 91177308-0d34-0410-b5e6-96231b3b80d8 Hal Finkel 7 years ago
4 changed file(s) with 216 addition(s) and 15 deletion(s). Raw diff Collapse all Expand all
453453 return false;
454454 }
455455
456 // Figure out if the offset in the instruction is shifted right two bits. This
457 // is true for instructions like "STD", which the machine implicitly adds two
458 // low zeros to.
459 static bool usesIXAddr(const MachineInstr &MI) {
460 unsigned OpC = MI.getOpcode();
461
462 switch (OpC) {
463 default:
464 return false;
465 case PPC::LWA:
466 case PPC::LD:
467 case PPC::STD:
468 return true;
469 }
470 }
471
472 // Return the OffsetOperandNo given the FIOperandNum (and the instruction).
473 static unsigned getOffsetONFromFION(const MachineInstr &MI,
474 unsigned FIOperandNum) {
475 // Take into account whether it's an add or mem instruction
476 unsigned OffsetOperandNo = (FIOperandNum == 2) ? 1 : 2;
477 if (MI.isInlineAsm())
478 OffsetOperandNo = FIOperandNum-1;
479
480 return OffsetOperandNo;
481 }
482
456483 void
457484 PPCRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
458485 int SPAdj, unsigned FIOperandNum,
470497 const TargetFrameLowering *TFI = MF.getTarget().getFrameLowering();
471498 DebugLoc dl = MI.getDebugLoc();
472499
473 // Take into account whether it's an add or mem instruction
474 unsigned OffsetOperandNo = (FIOperandNum == 2) ? 1 : 2;
475 if (MI.isInlineAsm())
476 OffsetOperandNo = FIOperandNum-1;
500 unsigned OffsetOperandNo = getOffsetONFromFION(MI, FIOperandNum);
477501
478502 // Get the frame index.
479503 int FrameIndex = MI.getOperand(FIOperandNum).getIndex();
515539 (is64Bit ? PPC::X1 : PPC::R1),
516540 false);
517541
518 // Figure out if the offset in the instruction is shifted right two bits. This
519 // is true for instructions like "STD", which the machine implicitly adds two
520 // low zeros to.
521 bool isIXAddr = false;
522 switch (OpC) {
523 case PPC::LWA:
524 case PPC::LD:
525 case PPC::STD:
526 isIXAddr = true;
527 break;
528 }
542 // Figure out if the offset in the instruction is shifted right two bits.
543 bool isIXAddr = usesIXAddr(MI);
529544
530545 // If the instruction is not present in ImmToIdxMap, then it has no immediate
531546 // form (and must be r+r).
617632 unsigned PPCRegisterInfo::getEHHandlerRegister() const {
618633 return !Subtarget.isPPC64() ? PPC::R4 : PPC::X4;
619634 }
635
636 /// Returns true if the instruction's frame index
637 /// reference would be better served by a base register other than FP
638 /// or SP. Used by LocalStackFrameAllocation to determine which frame index
639 /// references it should create new base registers for.
640 bool PPCRegisterInfo::
641 needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const {
642 assert(Offset < 0 && "Local offset must be negative");
643
644 unsigned FIOperandNum = 0;
645 while (!MI->getOperand(FIOperandNum).isFI()) {
646 ++FIOperandNum;
647 assert(FIOperandNum < MI->getNumOperands() &&
648 "Instr doesn't have FrameIndex operand!");
649 }
650
651 unsigned OffsetOperandNo = getOffsetONFromFION(*MI, FIOperandNum);
652
653 if (!usesIXAddr(*MI))
654 Offset += MI->getOperand(OffsetOperandNo).getImm();
655 else
656 Offset += MI->getOperand(OffsetOperandNo).getImm() << 2;
657
658 // It's the load/store FI references that cause issues, as it can be difficult
659 // to materialize the offset if it won't fit in the literal field. Estimate
660 // based on the size of the local frame and some conservative assumptions
661 // about the rest of the stack frame (note, this is pre-regalloc, so
662 // we don't know everything for certain yet) whether this offset is likely
663 // to be out of range of the immediate. Return true if so.
664
665 // We only generate virtual base registers for loads and stores that have
666 // an r+i form. Return false for everything else.
667 unsigned OpC = MI->getOpcode();
668 if (!ImmToIdxMap.count(OpC))
669 return false;
670
671 // Don't generate a new virtual base register just to add zero to it.
672 if ((OpC == PPC::ADDI || OpC == PPC::ADDI8) &&
673 MI->getOperand(2).getImm() == 0)
674 return false;
675
676 MachineBasicBlock &MBB = *MI->getParent();
677 MachineFunction &MF = *MBB.getParent();
678
679 const PPCFrameLowering *PPCFI =
680 static_cast(MF.getTarget().getFrameLowering());
681 unsigned StackEst =
682 PPCFI->determineFrameLayout(MF, false, true);
683
684 // If we likely don't need a stack frame, then we probably don't need a
685 // virtual base register either.
686 if (!StackEst)
687 return false;
688
689 // Estimate an offset from the stack pointer.
690 // The incoming offset is relating to the SP at the start of the function,
691 // but when we access the local it'll be relative to the SP after local
692 // allocation, so adjust our SP-relative offset by that allocation size.
693 Offset += StackEst;
694
695 // The frame pointer will point to the end of the stack, so estimate the
696 // offset as the difference between the object offset and the FP location.
697 return !isFrameOffsetLegal(MI, Offset);
698 }
699
700 /// Insert defining instruction(s) for BaseReg to
701 /// be a pointer to FrameIdx at the beginning of the basic block.
702 void PPCRegisterInfo::
703 materializeFrameBaseRegister(MachineBasicBlock *MBB,
704 unsigned BaseReg, int FrameIdx,
705 int64_t Offset) const {
706 unsigned ADDriOpc = Subtarget.isPPC64() ? PPC::ADDI8 : PPC::ADDI;
707
708 MachineBasicBlock::iterator Ins = MBB->begin();
709 DebugLoc DL; // Defaults to "unknown"
710 if (Ins != MBB->end())
711 DL = Ins->getDebugLoc();
712
713 const MCInstrDesc &MCID = TII.get(ADDriOpc);
714 MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
715 const MachineFunction &MF = *MBB->getParent();
716 MRI.constrainRegClass(BaseReg, TII.getRegClass(MCID, 0, this, MF));
717
718 BuildMI(*MBB, Ins, DL, MCID, BaseReg)
719 .addFrameIndex(FrameIdx).addImm(Offset);
720 }
721
722 void
723 PPCRegisterInfo::resolveFrameIndex(MachineBasicBlock::iterator I,
724 unsigned BaseReg, int64_t Offset) const {
725 MachineInstr &MI = *I;
726
727 unsigned FIOperandNum = 0;
728 while (!MI.getOperand(FIOperandNum).isFI()) {
729 ++FIOperandNum;
730 assert(FIOperandNum < MI.getNumOperands() &&
731 "Instr doesn't have FrameIndex operand!");
732 }
733
734 MI.getOperand(FIOperandNum).ChangeToRegister(BaseReg, false);
735 unsigned OffsetOperandNo = getOffsetONFromFION(MI, FIOperandNum);
736
737 bool isIXAddr = usesIXAddr(MI);
738 if (!isIXAddr)
739 Offset += MI.getOperand(OffsetOperandNo).getImm();
740 else
741 Offset += MI.getOperand(OffsetOperandNo).getImm() << 2;
742
743 // Figure out if the offset in the instruction is shifted right two bits.
744 if (isIXAddr)
745 Offset >>= 2; // The actual encoded value has the low two bits zero.
746
747 MI.getOperand(OffsetOperandNo).ChangeToImmediate(Offset);
748 }
749
750 bool PPCRegisterInfo::isFrameOffsetLegal(const MachineInstr *MI,
751 int64_t Offset) const {
752 return MI->getOpcode() == PPC::DBG_VALUE || // DBG_VALUE is always Reg+Imm
753 (isInt<16>(Offset) && (!usesIXAddr(*MI) || (Offset & 3) == 0));
754 }
755
6060 return true;
6161 }
6262
63 virtual bool requiresVirtualBaseRegisters(const MachineFunction &MF) const {
64 return true;
65 }
66
6367 void lowerDynamicAlloc(MachineBasicBlock::iterator II) const;
6468 void lowerCRSpilling(MachineBasicBlock::iterator II,
6569 unsigned FrameIndex) const;
7680 int SPAdj, unsigned FIOperandNum,
7781 RegScavenger *RS = NULL) const;
7882
83 // Support for virtual base registers.
84 bool needsFrameBaseReg(MachineInstr *MI, int64_t Offset) const;
85 void materializeFrameBaseRegister(MachineBasicBlock *MBB,
86 unsigned BaseReg, int FrameIdx,
87 int64_t Offset) const;
88 void resolveFrameIndex(MachineBasicBlock::iterator I,
89 unsigned BaseReg, int64_t Offset) const;
90 bool isFrameOffsetLegal(const MachineInstr *MI, int64_t Offset) const;
91
7992 // Debug information queries.
8093 unsigned getFrameRegister(const MachineFunction &MF) const;
8194
0 ; RUN: llc < %s -march=ppc64 | FileCheck %s
1
2 ; Temporarily XFAIL this test until LSA stops creating single-use
3 ; virtual base registers.
4 ; XFAIL: *
15
26 %struct.__db_region = type { %struct.__mutex_t, [4 x i8], %struct.anon, i32, [1 x i32] }
37 %struct.__mutex_t = type { i32 }
0 ; RUN: llc < %s -mtriple=powerpc64-unknown-linux-gnu -mcpu=pwr7 | FileCheck %s
1 target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64"
2 target triple = "powerpc64-unknown-linux-gnu"
3
4 define signext i32 @foo() #0 {
5 entry:
6 %v = alloca [8200 x i32], align 4
7 %w = alloca [8200 x i32], align 4
8 %q = alloca [8200 x i32], align 4
9 %0 = bitcast [8200 x i32]* %v to i8*
10 call void @llvm.lifetime.start(i64 32800, i8* %0) #0
11 %1 = bitcast [8200 x i32]* %w to i8*
12 call void @llvm.lifetime.start(i64 32800, i8* %1) #0
13 %2 = bitcast [8200 x i32]* %q to i8*
14 call void @llvm.lifetime.start(i64 32800, i8* %2) #0
15 %arraydecay = getelementptr inbounds [8200 x i32]* %q, i64 0, i64 0
16 %arraydecay1 = getelementptr inbounds [8200 x i32]* %v, i64 0, i64 0
17 %arraydecay2 = getelementptr inbounds [8200 x i32]* %w, i64 0, i64 0
18 call void @bar(i32* %arraydecay, i32* %arraydecay1, i32* %arraydecay2) #0
19 %3 = load i32* %arraydecay2, align 4, !tbaa !0
20 %arrayidx3 = getelementptr inbounds [8200 x i32]* %w, i64 0, i64 1
21 %4 = load i32* %arrayidx3, align 4, !tbaa !0
22
23 ; CHECK: @foo
24 ; CHECK-NOT: lwzx
25 ; CHECK: lwz {{[0-9]+}}, 4([[REG:[0-9]+]])
26 ; CHECK: lwz {{[0-9]+}}, 0([[REG]])
27 ; CHECK: blr
28
29 %add = add nsw i32 %4, %3
30 call void @llvm.lifetime.end(i64 32800, i8* %2) #0
31 call void @llvm.lifetime.end(i64 32800, i8* %1) #0
32 call void @llvm.lifetime.end(i64 32800, i8* %0) #0
33 ret i32 %add
34 }
35
36 declare void @llvm.lifetime.start(i64, i8* nocapture) #0
37
38 declare void @bar(i32*, i32*, i32*)
39
40 declare void @llvm.lifetime.end(i64, i8* nocapture) #0
41
42 attributes #0 = { nounwind }
43
44 !0 = metadata !{metadata !"int", metadata !1}
45 !1 = metadata !{metadata !"omnipotent char", metadata !2}
46 !2 = metadata !{metadata !"Simple C/C++ TBAA"}
47