llvm.org GIT mirror llvm / f6cd582
[CodeGen] Print live-out register lists as liveout(...) in both MIR and debug output Work towards the unification of MIR and debug output by printing `liveout(...)` instead of `<regliveout>`. Only debug syntax is affected. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320683 91177308-0d34-0410-b5e6-96231b3b80d8 Francis Visoiu Mistrih 2 years ago
3 changed file(s) with 38 addition(s) and 19 deletion(s). Raw diff Collapse all Expand all
796796 case MachineOperand::MO_TargetIndex:
797797 case MachineOperand::MO_JumpTableIndex:
798798 case MachineOperand::MO_ExternalSymbol:
799 case MachineOperand::MO_GlobalAddress: {
799 case MachineOperand::MO_GlobalAddress:
800 case MachineOperand::MO_RegisterLiveOut: {
800801 unsigned TiedOperandIdx = 0;
801802 if (ShouldPrintRegisterTies && Op.isReg() && Op.isTied() && !Op.isDef())
802803 TiedOperandIdx = Op.getParent()->findTiedOperandIdx(OpIdx);
826827 OS << StringRef(TRI->getRegMaskNames()[RegMaskInfo->second]).lower();
827828 else
828829 printCustomRegMask(Op.getRegMask(), OS, TRI);
829 break;
830 }
831 case MachineOperand::MO_RegisterLiveOut: {
832 const uint32_t *RegMask = Op.getRegLiveOut();
833 OS << "liveout(";
834 bool IsCommaNeeded = false;
835 for (unsigned Reg = 0, E = TRI->getNumRegs(); Reg < E; ++Reg) {
836 if (RegMask[Reg / 32] & (1U << (Reg % 32))) {
837 if (IsCommaNeeded)
838 OS << ", ";
839 OS << printReg(Reg, TRI);
840 IsCommaNeeded = true;
841 }
842 }
843 OS << ")";
844830 break;
845831 }
846832 case MachineOperand::MO_Metadata:
636636 OS << ">";
637637 break;
638638 }
639 case MachineOperand::MO_RegisterLiveOut:
640 OS << "";
641 break;
639 case MachineOperand::MO_RegisterLiveOut: {
640 const uint32_t *RegMask = getRegLiveOut();
641 OS << "liveout(";
642 if (!TRI) {
643 OS << "";
644 } else {
645 bool IsCommaNeeded = false;
646 for (unsigned Reg = 0, E = TRI->getNumRegs(); Reg < E; ++Reg) {
647 if (RegMask[Reg / 32] & (1U << (Reg % 32))) {
648 if (IsCommaNeeded)
649 OS << ", ";
650 OS << printReg(Reg, TRI);
651 IsCommaNeeded = true;
652 }
653 }
654 }
655 OS << ")";
656 break;
657 }
642658 case MachineOperand::MO_Metadata:
643659 OS << '<';
644660 getMetadata()->printAsOperand(OS, MST);
271271 }
272272 }
273273
274 TEST(MachineOperandTest, PrintRegisterLiveOut) {
275 // Create a MachineOperand with a register live out list and print it.
276 uint32_t Mask = 0;
277 MachineOperand MO = MachineOperand::CreateRegLiveOut(&Mask);
278
279 // Checking some preconditions on the newly created
280 // MachineOperand.
281 ASSERT_TRUE(MO.isRegLiveOut());
282 ASSERT_TRUE(MO.getRegLiveOut() == &Mask);
283
284 std::string str;
285 // Print a MachineOperand containing a register live out list without a TRI.
286 raw_string_ostream OS(str);
287 MO.print(OS, /*TRI=*/nullptr, /*IntrinsicInfo=*/nullptr);
288 ASSERT_TRUE(OS.str() == "liveout()");
289 }
290
274291 } // end namespace