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AMDGPU/GlobalISel: Mark 32-bit float constants as legal Reviewers: arsenm Reviewed By: arsenm Subscribers: kzhuravl, wdng, nhaehnle, yaxunl, rovka, kristof.beyls, igorb, dstuttard, tpr, t-tye, llvm-commits Differential Revision: https://reviews.llvm.org/D33212 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@304003 91177308-0d34-0410-b5e6-96231b3b80d8 Tom Stellard 2 years ago
3 changed file(s) with 26 addition(s) and 0 deletion(s). Raw diff Collapse all Expand all
3535 setAction({G_CONSTANT, S32}, Legal);
3636 setAction({G_CONSTANT, S64}, Legal);
3737
38 setAction({G_FCONSTANT, S32}, Legal);
39
3840 setAction({G_GEP, P1}, Legal);
3941 setAction({G_GEP, P2}, Legal);
4042 setAction({G_GEP, 1, S64}, Legal);
23302330 bool SIInstrInfo::verifyInstruction(const MachineInstr &MI,
23312331 StringRef &ErrInfo) const {
23322332 uint16_t Opcode = MI.getOpcode();
2333
2334 if (SIInstrInfo::isGenericOpcode(MI.getOpcode()))
2335 return true;
2336
23332337 const MachineRegisterInfo &MRI = MI.getParent()->getParent()->getRegInfo();
23342338 int Src0Idx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::src0);
23352339 int Src1Idx = AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::src1);
11
22 --- |
33 define void @test_constant() {
4 entry:
5 ret void
6 }
7
8 define void @test_fconstant() {
49 entry:
510 ret void
611 }
1722
1823 %0(s32) = G_CONSTANT i32 5
1924 ...
25
26 ---
27 name: test_fconstant
28 registers:
29 - { id: 0, class: _ }
30 - { id: 1, class: _ }
31 body: |
32 bb.0.entry:
33 ; CHECK-LABEL: name: test_fconstant
34 ; CHECK: %0(s32) = G_FCONSTANT float 1.000000e+00
35 ; CHECK: %1(s32) = G_FCONSTANT float 7.5
36
37 %0(s32) = G_FCONSTANT float 1.0
38 %1(s32) = G_FCONSTANT float 7.5
39 ...