llvm.org GIT mirror llvm / f67ce49
AMDGPU: Fix trailing whitespace git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@272364 91177308-0d34-0410-b5e6-96231b3b80d8 Matt Arsenault 3 years ago
10 changed file(s) with 40 addition(s) and 40 deletion(s). Raw diff Collapse all Expand all
2929 field bits<64> SoftFail = 0;
3030
3131 let DecoderNamespace = Namespace;
32
32
3333 let TSFlags{63} = isRegisterLoad;
3434 let TSFlags{62} = isRegisterStore;
3535 }
123123
124124 void addImmOperands(MCInst &Inst, unsigned N, bool ApplyModifiers = true) const {
125125 if (Imm.Type == ImmTyNone && ApplyModifiers && Imm.Modifiers != 0) {
126 // Apply modifiers to immediate value
126 // Apply modifiers to immediate value
127127 int64_t Val = Imm.Val;
128128 bool Negate = Imm.Modifiers & 0x1;
129129 bool Abs = Imm.Modifiers & 0x2;
561561 MCTargetStreamer &TS = *getParser().getStreamer().getTargetStreamer();
562562 return static_cast(TS);
563563 }
564
564
565565 void setForcedEncodingSize(unsigned Size) { ForcedEncodingSize = Size; }
566566 void setForcedDPP(bool ForceDPP_) { ForcedDPP = ForceDPP_; }
567567 void setForcedSDWA(bool ForceSDWA_) { ForcedSDWA = ForceSDWA_; }
637637 AMDGPUOperand::Ptr defaultLWE() const;
638638 AMDGPUOperand::Ptr defaultSMRDOffset() const;
639639 AMDGPUOperand::Ptr defaultSMRDLiteralOffset() const;
640
640
641641 AMDGPUOperand::Ptr defaultClampSI() const;
642642 AMDGPUOperand::Ptr defaultOModSI() const;
643
643
644644 OperandMatchResultTy parseOModOperand(OperandVector &Operands);
645645
646646 void cvtId(MCInst &Inst, const OperandVector &Operands);
942942 if (Minus)
943943 F.changeSign();
944944 Operands.push_back(
945 AMDGPUOperand::CreateImm(F.bitcastToAPInt().getZExtValue(), S,
945 AMDGPUOperand::CreateImm(F.bitcastToAPInt().getZExtValue(), S,
946946 AMDGPUOperand::ImmTyNone, true));
947947 return MatchOperand_Success;
948948 }
969969
970970 AMDGPUAsmParser::OperandMatchResultTy
971971 AMDGPUAsmParser::parseRegOrImmWithInputMods(OperandVector &Operands) {
972 // XXX: During parsing we can't determine if minus sign means
972 // XXX: During parsing we can't determine if minus sign means
973973 // negate-modifier or negative immediate value.
974974 // By default we suppose it is modifier.
975975 bool Negate = false, Abs = false, Abs2 = false;
10231023 Parser.Lex();
10241024 Modifiers |= 0x2;
10251025 }
1026
1026
10271027 if (Modifiers) {
10281028 AMDGPUOperand &Op = static_cast(*Operands.back());
10291029 Op.setModifiers(Modifiers);
14021402 // Add the instruction mnemonic
14031403 Name = parseMnemonicSuffix(Name);
14041404 Operands.push_back(AMDGPUOperand::CreateToken(Name, NameLoc));
1405
1405
14061406 while (!getLexer().is(AsmToken::EndOfStatement)) {
14071407 AMDGPUAsmParser::OperandMatchResultTy Res = parseOperand(Operands, Name);
14081408
14091409 // Eat the comma or space if there is one.
14101410 if (getLexer().is(AsmToken::Comma))
14111411 Parser.Lex();
1412
1412
14131413 switch (Res) {
14141414 case MatchOperand_Success: break;
1415 case MatchOperand_ParseFail:
1415 case MatchOperand_ParseFail:
14161416 Error(getLexer().getLoc(), "failed parsing operand.");
14171417 while (!getLexer().is(AsmToken::EndOfStatement)) {
14181418 Parser.Lex();
14191419 }
14201420 return true;
1421 case MatchOperand_NoMatch:
1421 case MatchOperand_NoMatch:
14221422 Error(getLexer().getLoc(), "not a valid operand.");
14231423 while (!getLexer().is(AsmToken::EndOfStatement)) {
14241424 Parser.Lex();
15261526 }
15271527 }
15281528
1529 AMDGPUAsmParser::OperandMatchResultTy
1529 AMDGPUAsmParser::OperandMatchResultTy
15301530 AMDGPUAsmParser::parseStringWithPrefix(StringRef Prefix, StringRef &Value) {
15311531 if (getLexer().isNot(AsmToken::Identifier)) {
15321532 return MatchOperand_NoMatch;
15401540 if (getLexer().isNot(AsmToken::Colon)) {
15411541 return MatchOperand_ParseFail;
15421542 }
1543
1543
15441544 Parser.Lex();
15451545 if (getLexer().isNot(AsmToken::Identifier)) {
15461546 return MatchOperand_ParseFail;
25372537 SMLoc S = Parser.getTok().getLoc();
25382538 StringRef Value;
25392539 AMDGPUAsmParser::OperandMatchResultTy res;
2540
2540
25412541 res = parseStringWithPrefix(Prefix, Value);
25422542 if (res != MatchOperand_Success) {
25432543 return res;
25442544 }
2545
2545
25462546 int64_t Int;
25472547 Int = StringSwitch(Value)
25482548 .Case("BYTE_0", 0)
25632563 return MatchOperand_Success;
25642564 }
25652565
2566 AMDGPUAsmParser::OperandMatchResultTy
2566 AMDGPUAsmParser::OperandMatchResultTy
25672567 AMDGPUAsmParser::parseSDWADstUnused(OperandVector &Operands) {
25682568 SMLoc S = Parser.getTok().getLoc();
25692569 StringRef Value;
26872687 unsigned AMDGPUAsmParser::validateTargetOperandClass(MCParsedAsmOperand &Op,
26882688 unsigned Kind) {
26892689 // Tokens like "glc" would be parsed as immediate operands in ParseOperand().
2690 // But MatchInstructionImpl() expects to meet token and fails to validate
2690 // But MatchInstructionImpl() expects to meet token and fails to validate
26912691 // operand. This method checks if we are given immediate operand but expect to
26922692 // get corresponding token.
26932693 AMDGPUOperand &Operand = (AMDGPUOperand&)Op;
123123 do {
124124 // ToDo: better to switch encoding length using some bit predicate
125125 // but it is unknown yet, so try all we can
126
126
127127 // Try to decode DPP and SDWA first to solve conflict with VOP1 and VOP2
128128 // encodings
129129 if (Bytes.size() >= 8) {
511511 std::vector FetchClauses, AluClauses;
512512 std::vector LastAlu(1);
513513 std::vector ToPopAfter;
514
514
515515 for (MachineBasicBlock::iterator I = MBB.begin(), E = MBB.end();
516516 I != E;) {
517517 if (TII->usesTextureCache(I) || TII->usesVertexCache(I)) {
613613 DEBUG(dbgs() << CfCount << ":"; MIb->dump(););
614614 CfCount++;
615615 }
616
616
617617 MachineInstr *IfOrElseInst = IfThenElseStack.back();
618618 IfThenElseStack.pop_back();
619619 CounterPropagateAddr(IfOrElseInst, CfCount);
275275 BuildMI(MBB, ClauseHead, MBB.findDebugLoc(ClauseHead), TII->get(Opcode))
276276 // We don't use the ADDR field until R600ControlFlowFinalizer pass, where
277277 // it is safe to assume it is 0. However if we always put 0 here, the ifcvt
278 // pass may assume that identical ALU clause starter at the beginning of a
278 // pass may assume that identical ALU clause starter at the beginning of a
279279 // true and false branch can be factorized which is not the case.
280280 .addImm(Address++) // ADDR
281281 .addImm(KCacheBanks.empty()?0:KCacheBanks[0].first) // KB0
88 //
99 // R600 has a VLIW architecture. On pre-cayman cards there are 5 instruction
1010 // slots ALU.X, ALU.Y, ALU.Z, ALU.W, and TRANS. For cayman cards, the TRANS
11 // slot has been removed.
11 // slot has been removed.
1212 //
1313 //===----------------------------------------------------------------------===//
1414
319319 } else {
320320 llvm_unreachable("Unhandled loop condition!");
321321 }
322 return 0;
322 return nullptr;
323323 }
324324
325325 /// \brief Handle a back edge (loop)
238238 #define C_00B84C_LDS_SIZE 0xFF007FFF
239239 #define S_00B84C_EXCP_EN(x) (((x) & 0x7F) << 24)
240240 #define G_00B84C_EXCP_EN(x) (((x) >> 24) & 0x7F)
241 #define C_00B84C_EXCP_EN
241 #define C_00B84C_EXCP_EN
242242
243243 #define R_0286CC_SPI_PS_INPUT_ENA 0x0286CC
244244 #define R_0286D0_SPI_PS_INPUT_ADDR 0x0286D0
3737
3838 // -amdgpu-fast-fdiv - Command line option to enable faster 2.5 ulp fdiv.
3939 static cl::opt EnableAMDGPUFastFDIV(
40 "amdgpu-fast-fdiv",
41 cl::desc("Enable faster 2.5 ulp fdiv"),
40 "amdgpu-fast-fdiv",
41 cl::desc("Enable faster 2.5 ulp fdiv"),
4242 cl::init(false));
4343
4444 static unsigned findFirstFreeSGPR(CCState &CCInfo) {
491491
492492 bool SITargetLowering::isNoopAddrSpaceCast(unsigned SrcAS,
493493 unsigned DestAS) const {
494 return isFlatGlobalAddrSpace(SrcAS) && isFlatGlobalAddrSpace(DestAS);
494 return isFlatGlobalAddrSpace(SrcAS) && isFlatGlobalAddrSpace(DestAS);
495495 }
496496
497497
19881988 SDValue Mul = DAG.getNode(ISD::FMUL, SL, MVT::f32, LHS, r0);
19891989
19901990 return DAG.getNode(ISD::FMUL, SL, MVT::f32, r3, Mul);
1991 }
1992
1991 }
1992
19931993 // Generates more precise fpdiv32.
19941994 const SDValue One = DAG.getConstantFP(1.0, SL, MVT::f32);
1995
1995
19961996 SDVTList ScaleVT = DAG.getVTList(MVT::f32, MVT::i1);
1997
1997
19981998 SDValue DenominatorScaled = DAG.getNode(AMDGPUISD::DIV_SCALE, SL, ScaleVT, RHS, RHS, LHS);
19991999 SDValue NumeratorScaled = DAG.getNode(AMDGPUISD::DIV_SCALE, SL, ScaleVT, LHS, RHS, LHS);
2000
2000
20012001 SDValue ApproxRcp = DAG.getNode(AMDGPUISD::RCP, SL, MVT::f32, DenominatorScaled);
2002
2002
20032003 SDValue NegDivScale0 = DAG.getNode(ISD::FNEG, SL, MVT::f32, DenominatorScaled);
2004
2004
20052005 SDValue Fma0 = DAG.getNode(ISD::FMA, SL, MVT::f32, NegDivScale0, ApproxRcp, One);
20062006 SDValue Fma1 = DAG.getNode(ISD::FMA, SL, MVT::f32, Fma0, ApproxRcp, ApproxRcp);
2007
2007
20082008 SDValue Mul = DAG.getNode(ISD::FMUL, SL, MVT::f32, NumeratorScaled, Fma1);
2009
2009
20102010 SDValue Fma2 = DAG.getNode(ISD::FMA, SL, MVT::f32, NegDivScale0, Mul, NumeratorScaled);
20112011 SDValue Fma3 = DAG.getNode(ISD::FMA, SL, MVT::f32, Fma2, Fma1, Mul);
20122012 SDValue Fma4 = DAG.getNode(ISD::FMA, SL, MVT::f32, NegDivScale0, Fma3, NumeratorScaled);
2013
2013
20142014 SDValue Scale = NumeratorScaled.getValue(1);
20152015 SDValue Fmas = DAG.getNode(AMDGPUISD::DIV_FMAS, SL, MVT::f32, Fma4, Fma1, Fma3, Scale);
2016
2016
20172017 return DAG.getNode(AMDGPUISD::DIV_FIXUP, SL, MVT::f32, Fmas, RHS, LHS);
20182018 }
20192019
120120 //===----------------------------------------------------------------------===//
121121
122122 def : Pat <
123 (int_amdgcn_mov_dpp i32:$src, imm:$dpp_ctrl, imm:$row_mask, imm:$bank_mask,
123 (int_amdgcn_mov_dpp i32:$src, imm:$dpp_ctrl, imm:$row_mask, imm:$bank_mask,
124124 imm:$bound_ctrl),
125125 (V_MOV_B32_dpp $src, (as_i32imm $dpp_ctrl), (as_i32imm $row_mask),
126126 (as_i32imm $bank_mask), (as_i1imm $bound_ctrl))