llvm.org GIT mirror llvm / f6145af
[X86] Add OpSize32 to XBEGIN_4. Add XBEGIN_2 with OpSize16. Requires new AsmParserOperand types that detect 16-bit and 32/64-bit mode so that we choose the right instruction based on default sizing without predicates. This is necessary since predicates mess up the disassembler table building. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@225256 91177308-0d34-0410-b5e6-96231b3b80d8 Craig Topper 4 years ago
6 changed file(s) with 47 addition(s) and 9 deletion(s). Raw diff Collapse all Expand all
251251 bool isAbsMem() const {
252252 return Kind == Memory && !getMemSegReg() && !getMemBaseReg() &&
253253 !getMemIndexReg() && getMemScale() == 1;
254 }
255
256 bool isAbsMem16() const {
257 return isAbsMem() && Mem.ModeSize == 16;
258 }
259
260 bool isAbsMem32() const {
261 return isAbsMem() && Mem.ModeSize != 16;
254262 }
255263
256264 bool isSrcIdx() const {
5959 def JMP_1 : Ii8PCRel<0xEB, RawFrm, (outs), (ins brtarget8:$dst),
6060 "jmp\t$dst", [(br bb:$dst)], IIC_JMP_REL>;
6161 let hasSideEffects = 0, isCodeGenOnly = 1, ForceDisassemble = 1 in {
62 def JMP_2 : Ii16PCRel<0xE9, RawFrm, (outs), (ins brtarget:$dst),
62 def JMP_2 : Ii16PCRel<0xE9, RawFrm, (outs), (ins brtarget16:$dst),
6363 "jmp\t$dst", [], IIC_JMP_REL>, OpSize16;
64 def JMP_4 : Ii32PCRel<0xE9, RawFrm, (outs), (ins brtarget:$dst),
64 def JMP_4 : Ii32PCRel<0xE9, RawFrm, (outs), (ins brtarget32:$dst),
6565 "jmp\t$dst", [], IIC_JMP_REL>, OpSize32;
6666 }
6767 }
7272 def _1 : Ii8PCRel
7373 [(X86brcond bb:$dst, Cond, EFLAGS)], IIC_Jcc>;
7474 let hasSideEffects = 0, isCodeGenOnly = 1, ForceDisassemble = 1 in {
75 def _2 : Ii16PCRel:$dst), asm,
75 def _2 : Ii16PCRel16:$dst), asm,
7676 [], IIC_Jcc>, OpSize16, TB;
77 def _4 : Ii32PCRel:$dst), asm,
77 def _4 : Ii32PCRel32:$dst), asm,
7878 [], IIC_Jcc>, TB, OpSize32;
7979 }
8080 }
374374 def brtarget : Operand;
375375 def brtarget8 : Operand;
376376
377 }
378
379 // Special parsers to detect mode to disambiguate.
380 def X86AbsMem16AsmOperand : AsmOperandClass {
381 let Name = "AbsMem16";
382 let RenderMethod = "addAbsMemOperands";
383 let SuperClasses = [X86AbsMemAsmOperand];
384 }
385
386 def X86AbsMem32AsmOperand : AsmOperandClass {
387 let Name = "AbsMem32";
388 let RenderMethod = "addAbsMemOperands";
389 let SuperClasses = [X86AbsMemAsmOperand];
390 }
391
392 // Branch targets have OtherVT type and print as pc-relative values.
393 let OperandType = "OPERAND_PCREL",
394 PrintMethod = "printPCRelImm" in {
395 let ParserMatchClass = X86AbsMem16AsmOperand in
396 def brtarget16 : Operand;
397 let ParserMatchClass = X86AbsMem32AsmOperand in
398 def brtarget32 : Operand;
377399 }
378400
379401 let RenderMethod = "addSrcIdxOperands" in {
2222 "# XBEGIN", [(set GR32:$dst, (int_x86_xbegin))]>,
2323 Requires<[HasRTM]>;
2424
25 let isBranch = 1, isTerminator = 1, Defs = [EAX] in
26 def XBEGIN_4 : Ii32PCRel<0xc7, MRM_F8, (outs), (ins brtarget:$dst),
27 "xbegin\t$dst", []>, Requires<[HasRTM]>;
25 let isBranch = 1, isTerminator = 1, Defs = [EAX] in {
26 def XBEGIN_2 : Ii16PCRel<0xc7, MRM_F8, (outs), (ins brtarget16:$dst),
27 "xbegin\t$dst", []>, OpSize16, Requires<[HasRTM]>;
28 def XBEGIN_4 : Ii32PCRel<0xc7, MRM_F8, (outs), (ins brtarget32:$dst),
29 "xbegin\t$dst", []>, OpSize32, Requires<[HasRTM]>;
30 }
2831
2932 def XEND : I<0x01, MRM_D5, (outs), (ins),
3033 "xend", [(int_x86_xend)]>, TB, Requires<[HasRTM]>;
106106 # CHECK: xbegin 53
107107 0xc7 0xf8 0x35 0x00 0x00 0x00
108108
109 # CHECK: xbegin 53
110 0x66 0xc7 0xf8 0x35 0x00
111
109112 # CHECK: xend
110113 0x0f 0x01 0xd5
111114
955955 TYPE("SSECC", TYPE_IMM3)
956956 TYPE("AVXCC", TYPE_IMM5)
957957 TYPE("AVX512RC", TYPE_IMM32)
958 TYPE("brtarget", TYPE_RELv)
958 TYPE("brtarget32", TYPE_RELv)
959 TYPE("brtarget16", TYPE_RELv)
959960 TYPE("brtarget8", TYPE_REL8)
960961 TYPE("f80mem", TYPE_M80FP)
961962 TYPE("lea32mem", TYPE_LEA)
12111212 ENCODING("i64i32imm_pcrel", ENCODING_ID)
12121213 ENCODING("i16imm_pcrel", ENCODING_IW)
12131214 ENCODING("i32imm_pcrel", ENCODING_ID)
1214 ENCODING("brtarget", ENCODING_Iv)
1215 ENCODING("brtarget32", ENCODING_Iv)
1216 ENCODING("brtarget16", ENCODING_Iv)
12151217 ENCODING("brtarget8", ENCODING_IB)
12161218 ENCODING("i64imm", ENCODING_IO)
12171219 ENCODING("offset16_8", ENCODING_Ia)