llvm.org GIT mirror llvm / f602040
Fixed a bug in printing "cmp" pseudo ops. > This IR code > %res = call <8 x float> @llvm.x86.avx.cmp.ps.256(<8 x float> %a0, <8 x float> %a1, i8 14) > fails with assertion: > > llc: X86ATTInstPrinter.cpp:62: void llvm::X86ATTInstPrinter::printSSECC(const llvm::MCInst*, unsigned int, llvm::raw_ostream&): Assertion `0 && "Invalid ssecc argument!"' failed. > 0 llc 0x0000000001355803 > 1 llc 0x0000000001355dc9 > 2 libpthread.so.0 0x00007f79a30575d0 > 3 libc.so.6 0x00007f79a23a1945 gsignal + 53 > 4 libc.so.6 0x00007f79a23a2f21 abort + 385 > 5 libc.so.6 0x00007f79a239a810 __assert_fail + 240 > 6 llc 0x00000000011858d5 llvm::X86ATTInstPrinter::printSSECC(llvm::MCInst const*, unsigned int, llvm::raw_ostream&) + 119 I added the full testing for all possible pseudo-ops of cmp. I extended X86AsmPrinter.cpp and X86IntelInstPrinter.cpp. You'l also see lines alignments (unrelated to this fix) in X86IselLowering.cpp from my previous check-in. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@150068 91177308-0d34-0410-b5e6-96231b3b80d8 Elena Demikhovsky 8 years ago
5 changed file(s) with 184 addition(s) and 42 deletion(s). Raw diff Collapse all Expand all
5959 raw_ostream &O) {
6060 switch (MI->getOperand(Op).getImm()) {
6161 default: llvm_unreachable("Invalid ssecc argument!");
62 case 0: O << "eq"; break;
63 case 1: O << "lt"; break;
64 case 2: O << "le"; break;
65 case 3: O << "unord"; break;
66 case 4: O << "neq"; break;
67 case 5: O << "nlt"; break;
68 case 6: O << "nle"; break;
69 case 7: O << "ord"; break;
62 case 0: O << "eq"; break;
63 case 1: O << "lt"; break;
64 case 2: O << "le"; break;
65 case 3: O << "unord"; break;
66 case 4: O << "neq"; break;
67 case 5: O << "nlt"; break;
68 case 6: O << "nle"; break;
69 case 7: O << "ord"; break;
70 case 8: O << "eq_uq"; break;
71 case 9: O << "nge"; break;
72 case 0xa: O << "ngt"; break;
73 case 0xb: O << "false"; break;
74 case 0xc: O << "neq_oq"; break;
75 case 0xd: O << "ge"; break;
76 case 0xe: O << "gt"; break;
77 case 0xf: O << "true"; break;
78 case 0x10: O << "eq_os"; break;
79 case 0x11: O << "lt_oq"; break;
80 case 0x12: O << "le_oq"; break;
81 case 0x13: O << "unord_s"; break;
82 case 0x14: O << "neq_us"; break;
83 case 0x15: O << "nlt_uq"; break;
84 case 0x16: O << "nle_uq"; break;
85 case 0x17: O << "ord_s"; break;
86 case 0x18: O << "eq_us"; break;
87 case 0x19: O << "nge_uq"; break;
88 case 0x1a: O << "ngt_uq"; break;
89 case 0x1b: O << "false_os"; break;
90 case 0x1c: O << "neq_os"; break;
91 case 0x1d: O << "ge_oq"; break;
92 case 0x1e: O << "gt_oq"; break;
93 case 0x1f: O << "true_us"; break;
7094 }
7195 }
7296
4949 raw_ostream &O) {
5050 switch (MI->getOperand(Op).getImm()) {
5151 default: llvm_unreachable("Invalid ssecc argument!");
52 case 0: O << "eq"; break;
53 case 1: O << "lt"; break;
54 case 2: O << "le"; break;
55 case 3: O << "unord"; break;
56 case 4: O << "neq"; break;
57 case 5: O << "nlt"; break;
58 case 6: O << "nle"; break;
59 case 7: O << "ord"; break;
52 case 0: O << "eq"; break;
53 case 1: O << "lt"; break;
54 case 2: O << "le"; break;
55 case 3: O << "unord"; break;
56 case 4: O << "neq"; break;
57 case 5: O << "nlt"; break;
58 case 6: O << "nle"; break;
59 case 7: O << "ord"; break;
60 case 8: O << "eq_uq"; break;
61 case 9: O << "nge"; break;
62 case 0xa: O << "ngt"; break;
63 case 0xb: O << "false"; break;
64 case 0xc: O << "neq_oq"; break;
65 case 0xd: O << "ge"; break;
66 case 0xe: O << "gt"; break;
67 case 0xf: O << "true"; break;
68 case 0x10: O << "eq_os"; break;
69 case 0x11: O << "lt_oq"; break;
70 case 0x12: O << "le_oq"; break;
71 case 0x13: O << "unord_s"; break;
72 case 0x14: O << "neq_us"; break;
73 case 0x15: O << "nlt_uq"; break;
74 case 0x16: O << "nle_uq"; break;
75 case 0x17: O << "ord_s"; break;
76 case 0x18: O << "eq_us"; break;
77 case 0x19: O << "nge_uq"; break;
78 case 0x1a: O << "ngt_uq"; break;
79 case 0x1b: O << "false_os"; break;
80 case 0x1c: O << "neq_os"; break;
81 case 0x1d: O << "ge_oq"; break;
82 case 0x1e: O << "gt_oq"; break;
83 case 0x1f: O << "true_us"; break;
84
6085 }
6186 }
6287
265265 unsigned char value = MI->getOperand(Op).getImm();
266266 assert(value <= 7 && "Invalid ssecc argument!");
267267 switch (value) {
268 case 0: O << "eq"; break;
269 case 1: O << "lt"; break;
270 case 2: O << "le"; break;
271 case 3: O << "unord"; break;
272 case 4: O << "neq"; break;
273 case 5: O << "nlt"; break;
274 case 6: O << "nle"; break;
275 case 7: O << "ord"; break;
268 case 0: O << "eq"; break;
269 case 1: O << "lt"; break;
270 case 2: O << "le"; break;
271 case 3: O << "unord"; break;
272 case 4: O << "neq"; break;
273 case 5: O << "nlt"; break;
274 case 6: O << "nle"; break;
275 case 7: O << "ord"; break;
276 case 8: O << "eq_uq"; break;
277 case 9: O << "nge"; break;
278 case 0xa: O << "ngt"; break;
279 case 0xb: O << "false"; break;
280 case 0xc: O << "neq_oq"; break;
281 case 0xd: O << "ge"; break;
282 case 0xe: O << "gt"; break;
283 case 0xf: O << "true"; break;
284 case 0x10: O << "eq_os"; break;
285 case 0x11: O << "lt_oq"; break;
286 case 0x12: O << "le_oq"; break;
287 case 0x13: O << "unord_s"; break;
288 case 0x14: O << "neq_us"; break;
289 case 0x15: O << "nlt_uq"; break;
290 case 0x16: O << "nle_uq"; break;
291 case 0x17: O << "ord_s"; break;
292 case 0x18: O << "eq_us"; break;
293 case 0x19: O << "nge_uq"; break;
294 case 0x1a: O << "ngt_uq"; break;
295 case 0x1b: O << "false_os"; break;
296 case 0x1c: O << "neq_os"; break;
297 case 0x1d: O << "ge_oq"; break;
298 case 0x1e: O << "gt_oq"; break;
299 case 0x1f: O << "true_us"; break;
276300 }
277301 }
278302
1459614596 if (!DCI.isBeforeLegalizeOps())
1459714597 return SDValue();
1459814598
14599 if (!Subtarget->hasAVX()) return SDValue();
14600
14601 // Optimize vectors in AVX mode
14602 // Sign extend v8i16 to v8i32 and
14603 // v4i32 to v4i64
14604 //
14605 // Divide input vector into two parts
14606 // for v4i32 the shuffle mask will be { 0, 1, -1, -1} {2, 3, -1, -1}
14607 // use vpmovsx instruction to extend v4i32 -> v2i64; v8i16 -> v4i32
14608 // concat the vectors to original VT
14599 if (!Subtarget->hasAVX())
14600 return SDValue();
14601
14602 // Optimize vectors in AVX mode
14603 // Sign extend v8i16 to v8i32 and
14604 // v4i32 to v4i64
14605 //
14606 // Divide input vector into two parts
14607 // for v4i32 the shuffle mask will be { 0, 1, -1, -1} {2, 3, -1, -1}
14608 // use vpmovsx instruction to extend v4i32 -> v2i64; v8i16 -> v4i32
14609 // concat the vectors to original VT
1460914610
1461014611 EVT VT = N->getValueType(0);
1461114612 SDValue Op = N->getOperand(0);
1461214613 EVT OpVT = Op.getValueType();
1461314614 DebugLoc dl = N->getDebugLoc();
1461414615
14615 if (((VT == MVT::v4i64) && (OpVT == MVT::v4i32)) ||
14616 ((VT == MVT::v8i32) && (OpVT == MVT::v8i16))) {
14616 if ((VT == MVT::v4i64 && OpVT == MVT::v4i32) ||
14617 (VT == MVT::v8i32 && OpVT == MVT::v8i16)) {
1461714618
1461814619 unsigned NumElems = OpVT.getVectorNumElements();
1461914620 SmallVector ShufMask1(NumElems, -1);
14620 for (unsigned i=0; i< NumElems/2; i++) ShufMask1[i] = i;
14621 for (unsigned i = 0; i < NumElems/2; i++) ShufMask1[i] = i;
1462114622
1462214623 SDValue OpLo = DAG.getVectorShuffle(OpVT, dl, Op, DAG.getUNDEF(OpVT),
14623 ShufMask1.data());
14624 ShufMask1.data());
1462414625
1462514626 SmallVector ShufMask2(NumElems, -1);
14626 for (unsigned i=0; i< NumElems/2; i++) ShufMask2[i] = i+NumElems/2;
14627 for (unsigned i = 0; i < NumElems/2; i++) ShufMask2[i] = i + NumElems/2;
1462714628
1462814629 SDValue OpHi = DAG.getVectorShuffle(OpVT, dl, Op, DAG.getUNDEF(OpVT),
14629 ShufMask2.data());
14630 ShufMask2.data());
1463014631
1463114632 EVT HalfVT = EVT::getVectorVT(*DAG.getContext(), VT.getScalarType(),
14632 VT.getVectorNumElements()/2);
14633
14633 VT.getVectorNumElements()/2);
14634
1463414635 OpLo = DAG.getNode(X86ISD::VSEXT_MOVL, dl, HalfVT, OpLo);
1463514636 OpHi = DAG.getNode(X86ISD::VSEXT_MOVL, dl, HalfVT, OpHi);
1463614637
17631763 define <8 x float> @test_x86_avx_cmp_ps_256(<8 x float> %a0, <8 x float> %a1) {
17641764 ; CHECK: vcmpordps
17651765 %res = call <8 x float> @llvm.x86.avx.cmp.ps.256(<8 x float> %a0, <8 x float> %a1, i8 7) ; <<8 x float>> [#uses=1]
1766 ret <8 x float> %res
1767 }
1768
1769 define <8 x float> @test_x86_avx_cmp_ps_256_pseudo_op(<8 x float> %a0, <8 x float> %a1) {
1770 ; CHECK: vcmpeqps
1771 %a2 = call <8 x float> @llvm.x86.avx.cmp.ps.256(<8 x float> %a0, <8 x float> %a1, i8 0) ; <<8 x float>> [#uses=1]
1772 ; CHECK: vcmpltps
1773 %a3 = call <8 x float> @llvm.x86.avx.cmp.ps.256(<8 x float> %a0, <8 x float> %a2, i8 1) ; <<8 x float>> [#uses=1]
1774 ; CHECK: vcmpleps
1775 %a4 = call <8 x float> @llvm.x86.avx.cmp.ps.256(<8 x float> %a0, <8 x float> %a3, i8 2) ; <<8 x float>> [#uses=1]
1776 ; CHECK: vcmpunordps
1777 %a5 = call <8 x float> @llvm.x86.avx.cmp.ps.256(<8 x float> %a0, <8 x float> %a4, i8 3) ; <<8 x float>> [#uses=1]
1778 ; CHECK: vcmpneqps
1779 %a6 = call <8 x float> @llvm.x86.avx.cmp.ps.256(<8 x float> %a0, <8 x float> %a5, i8 4) ; <<8 x float>> [#uses=1]
1780 ; CHECK: vcmpnltps
1781 %a7 = call <8 x float> @llvm.x86.avx.cmp.ps.256(<8 x float> %a0, <8 x float> %a6, i8 5) ; <<8 x float>> [#uses=1]
1782 ; CHECK: vcmpnleps
1783 %a8 = call <8 x float> @llvm.x86.avx.cmp.ps.256(<8 x float> %a0, <8 x float> %a7, i8 6) ; <<8 x float>> [#uses=1]
1784 ; CHECK: vcmpordps
1785 %a9 = call <8 x float> @llvm.x86.avx.cmp.ps.256(<8 x float> %a0, <8 x float> %a8, i8 7) ; <<8 x float>> [#uses=1]
1786 ; CHECK: vcmpeq_uqps
1787 %a10 = call <8 x float> @llvm.x86.avx.cmp.ps.256(<8 x float> %a0, <8 x float> %a9, i8 8) ; <<8 x float>> [#uses=1]
1788 ; CHECK: vcmpngeps
1789 %a11 = call <8 x float> @llvm.x86.avx.cmp.ps.256(<8 x float> %a0, <8 x float> %a10, i8 9) ; <<8 x float>> [#uses=1]
1790 ; CHECK: vcmpngtps
1791 %a12 = call <8 x float> @llvm.x86.avx.cmp.ps.256(<8 x float> %a0, <8 x float> %a11, i8 10) ; <<8 x float>> [#uses=1]
1792 ; CHECK: vcmpfalseps
1793 %a13 = call <8 x float> @llvm.x86.avx.cmp.ps.256(<8 x float> %a0, <8 x float> %a12, i8 11) ; <<8 x float>> [#uses=1]
1794 ; CHECK: vcmpneq_oqps
1795 %a14 = call <8 x float> @llvm.x86.avx.cmp.ps.256(<8 x float> %a0, <8 x float> %a13, i8 12) ; <<8 x float>> [#uses=1]
1796 ; CHECK: vcmpgeps
1797 %a15 = call <8 x float> @llvm.x86.avx.cmp.ps.256(<8 x float> %a0, <8 x float> %a14, i8 13) ; <<8 x float>> [#uses=1]
1798 ; CHECK: vcmpgtps
1799 %a16 = call <8 x float> @llvm.x86.avx.cmp.ps.256(<8 x float> %a0, <8 x float> %a15, i8 14) ; <<8 x float>> [#uses=1]
1800 ; CHECK: vcmptrueps
1801 %a17 = call <8 x float> @llvm.x86.avx.cmp.ps.256(<8 x float> %a0, <8 x float> %a16, i8 15) ; <<8 x float>> [#uses=1]
1802 ; CHECK: vcmpeq_osps
1803 %a18 = call <8 x float> @llvm.x86.avx.cmp.ps.256(<8 x float> %a0, <8 x float> %a17, i8 16) ; <<8 x float>> [#uses=1]
1804 ; CHECK: vcmplt_oqps
1805 %a19 = call <8 x float> @llvm.x86.avx.cmp.ps.256(<8 x float> %a0, <8 x float> %a18, i8 17) ; <<8 x float>> [#uses=1]
1806 ; CHECK: vcmple_oqps
1807 %a20 = call <8 x float> @llvm.x86.avx.cmp.ps.256(<8 x float> %a0, <8 x float> %a19, i8 18) ; <<8 x float>> [#uses=1]
1808 ; CHECK: vcmpunord_sps
1809 %a21 = call <8 x float> @llvm.x86.avx.cmp.ps.256(<8 x float> %a0, <8 x float> %a20, i8 19) ; <<8 x float>> [#uses=1]
1810 ; CHECK: vcmpneq_usps
1811 %a22 = call <8 x float> @llvm.x86.avx.cmp.ps.256(<8 x float> %a0, <8 x float> %a21, i8 20) ; <<8 x float>> [#uses=1]
1812 ; CHECK: vcmpnlt_uqps
1813 %a23 = call <8 x float> @llvm.x86.avx.cmp.ps.256(<8 x float> %a0, <8 x float> %a22, i8 21) ; <<8 x float>> [#uses=1]
1814 ; CHECK: vcmpnle_uqps
1815 %a24 = call <8 x float> @llvm.x86.avx.cmp.ps.256(<8 x float> %a0, <8 x float> %a23, i8 22) ; <<8 x float>> [#uses=1]
1816 ; CHECK: vcmpord_sps
1817 %a25 = call <8 x float> @llvm.x86.avx.cmp.ps.256(<8 x float> %a0, <8 x float> %a24, i8 23) ; <<8 x float>> [#uses=1]
1818 ; CHECK: vcmpeq_usps
1819 %a26 = call <8 x float> @llvm.x86.avx.cmp.ps.256(<8 x float> %a0, <8 x float> %a25, i8 24) ; <<8 x float>> [#uses=1]
1820 ; CHECK: vcmpnge_uqps
1821 %a27 = call <8 x float> @llvm.x86.avx.cmp.ps.256(<8 x float> %a0, <8 x float> %a26, i8 25) ; <<8 x float>> [#uses=1]
1822 ; CHECK: vcmpngt_uqps
1823 %a28 = call <8 x float> @llvm.x86.avx.cmp.ps.256(<8 x float> %a0, <8 x float> %a27, i8 26) ; <<8 x float>> [#uses=1]
1824 ; CHECK: vcmpfalse_osps
1825 %a29 = call <8 x float> @llvm.x86.avx.cmp.ps.256(<8 x float> %a0, <8 x float> %a28, i8 27) ; <<8 x float>> [#uses=1]
1826 ; CHECK: vcmpneq_osps
1827 %a30 = call <8 x float> @llvm.x86.avx.cmp.ps.256(<8 x float> %a0, <8 x float> %a29, i8 28) ; <<8 x float>> [#uses=1]
1828 ; CHECK: vcmpge_oqps
1829 %a31 = call <8 x float> @llvm.x86.avx.cmp.ps.256(<8 x float> %a0, <8 x float> %a30, i8 29) ; <<8 x float>> [#uses=1]
1830 ; CHECK: vcmpgt_oqps
1831 %a32 = call <8 x float> @llvm.x86.avx.cmp.ps.256(<8 x float> %a0, <8 x float> %a31, i8 30) ; <<8 x float>> [#uses=1]
1832 ; CHECK: vcmptrue_usps
1833 %res = call <8 x float> @llvm.x86.avx.cmp.ps.256(<8 x float> %a0, <8 x float> %a32, i8 31) ; <<8 x float>> [#uses=1]
17661834 ret <8 x float> %res
17671835 }
17681836 declare <8 x float> @llvm.x86.avx.cmp.ps.256(<8 x float>, <8 x float>, i8) nounwind readnone