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[SLPVectorizer] add tests for bogus reductions; NFC https://bugs.llvm.org/show_bug.cgi?id=42708 https://bugs.llvm.org/show_bug.cgi?id=43146 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@372393 91177308-0d34-0410-b5e6-96231b3b80d8 Sanjay Patel a month ago
1 changed file(s) with 334 addition(s) and 0 deletion(s). Raw diff Collapse all Expand all
0 ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
1 ; RUN: opt < %s -slp-vectorizer -S -mtriple=x86_64-- -mattr=avx2 | FileCheck %s
2
3 %v8i8 = type { i8, i8, i8, i8, i8, i8, i8, i8 }
4
5 ; https://bugs.llvm.org/show_bug.cgi?id=43146
6
7 define i64 @load_bswap(%v8i8* %p) {
8 ; CHECK-LABEL: @load_bswap(
9 ; CHECK-NEXT: [[G0:%.*]] = getelementptr inbounds [[V8I8:%.*]], %v8i8* [[P:%.*]], i64 0, i32 0
10 ; CHECK-NEXT: [[G1:%.*]] = getelementptr inbounds [[V8I8]], %v8i8* [[P]], i64 0, i32 1
11 ; CHECK-NEXT: [[G2:%.*]] = getelementptr inbounds [[V8I8]], %v8i8* [[P]], i64 0, i32 2
12 ; CHECK-NEXT: [[G3:%.*]] = getelementptr inbounds [[V8I8]], %v8i8* [[P]], i64 0, i32 3
13 ; CHECK-NEXT: [[G4:%.*]] = getelementptr inbounds [[V8I8]], %v8i8* [[P]], i64 0, i32 4
14 ; CHECK-NEXT: [[G5:%.*]] = getelementptr inbounds [[V8I8]], %v8i8* [[P]], i64 0, i32 5
15 ; CHECK-NEXT: [[G6:%.*]] = getelementptr inbounds [[V8I8]], %v8i8* [[P]], i64 0, i32 6
16 ; CHECK-NEXT: [[G7:%.*]] = getelementptr inbounds [[V8I8]], %v8i8* [[P]], i64 0, i32 7
17 ; CHECK-NEXT: [[TMP1:%.*]] = bitcast i8* [[G0]] to <4 x i8>*
18 ; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i8>, <4 x i8>* [[TMP1]], align 1
19 ; CHECK-NEXT: [[T4:%.*]] = load i8, i8* [[G4]]
20 ; CHECK-NEXT: [[T5:%.*]] = load i8, i8* [[G5]]
21 ; CHECK-NEXT: [[T6:%.*]] = load i8, i8* [[G6]]
22 ; CHECK-NEXT: [[T7:%.*]] = load i8, i8* [[G7]]
23 ; CHECK-NEXT: [[TMP3:%.*]] = zext <4 x i8> [[TMP2]] to <4 x i64>
24 ; CHECK-NEXT: [[Z4:%.*]] = zext i8 [[T4]] to i64
25 ; CHECK-NEXT: [[Z5:%.*]] = zext i8 [[T5]] to i64
26 ; CHECK-NEXT: [[Z6:%.*]] = zext i8 [[T6]] to i64
27 ; CHECK-NEXT: [[Z7:%.*]] = zext i8 [[T7]] to i64
28 ; CHECK-NEXT: [[TMP4:%.*]] = shl nuw <4 x i64> [[TMP3]],
29 ; CHECK-NEXT: [[SH4:%.*]] = shl nuw nsw i64 [[Z4]], 24
30 ; CHECK-NEXT: [[SH5:%.*]] = shl nuw nsw i64 [[Z5]], 16
31 ; CHECK-NEXT: [[SH6:%.*]] = shl nuw nsw i64 [[Z6]], 8
32 ; CHECK-NEXT: [[OR01:%.*]] = or i64 undef, undef
33 ; CHECK-NEXT: [[OR012:%.*]] = or i64 [[OR01]], undef
34 ; CHECK-NEXT: [[OR0123:%.*]] = or i64 [[OR012]], undef
35 ; CHECK-NEXT: [[OR01234:%.*]] = or i64 [[OR0123]], [[SH4]]
36 ; CHECK-NEXT: [[OR012345:%.*]] = or i64 [[OR01234]], [[SH5]]
37 ; CHECK-NEXT: [[OR0123456:%.*]] = or i64 [[OR012345]], [[SH6]]
38 ; CHECK-NEXT: [[RDX_SHUF:%.*]] = shufflevector <4 x i64> [[TMP4]], <4 x i64> undef, <4 x i32>
39 ; CHECK-NEXT: [[BIN_RDX:%.*]] = or <4 x i64> [[TMP4]], [[RDX_SHUF]]
40 ; CHECK-NEXT: [[RDX_SHUF1:%.*]] = shufflevector <4 x i64> [[BIN_RDX]], <4 x i64> undef, <4 x i32>
41 ; CHECK-NEXT: [[BIN_RDX2:%.*]] = or <4 x i64> [[BIN_RDX]], [[RDX_SHUF1]]
42 ; CHECK-NEXT: [[TMP5:%.*]] = extractelement <4 x i64> [[BIN_RDX2]], i32 0
43 ; CHECK-NEXT: [[TMP6:%.*]] = or i64 [[TMP5]], [[SH4]]
44 ; CHECK-NEXT: [[TMP7:%.*]] = or i64 [[TMP6]], [[SH5]]
45 ; CHECK-NEXT: [[TMP8:%.*]] = or i64 [[TMP7]], [[SH6]]
46 ; CHECK-NEXT: [[OP_EXTRA:%.*]] = or i64 [[TMP8]], [[Z7]]
47 ; CHECK-NEXT: [[OR01234567:%.*]] = or i64 [[OR0123456]], [[Z7]]
48 ; CHECK-NEXT: ret i64 [[OP_EXTRA]]
49 ;
50 %g0 = getelementptr inbounds %v8i8, %v8i8* %p, i64 0, i32 0
51 %g1 = getelementptr inbounds %v8i8, %v8i8* %p, i64 0, i32 1
52 %g2 = getelementptr inbounds %v8i8, %v8i8* %p, i64 0, i32 2
53 %g3 = getelementptr inbounds %v8i8, %v8i8* %p, i64 0, i32 3
54 %g4 = getelementptr inbounds %v8i8, %v8i8* %p, i64 0, i32 4
55 %g5 = getelementptr inbounds %v8i8, %v8i8* %p, i64 0, i32 5
56 %g6 = getelementptr inbounds %v8i8, %v8i8* %p, i64 0, i32 6
57 %g7 = getelementptr inbounds %v8i8, %v8i8* %p, i64 0, i32 7
58
59 %t0 = load i8, i8* %g0
60 %t1 = load i8, i8* %g1
61 %t2 = load i8, i8* %g2
62 %t3 = load i8, i8* %g3
63 %t4 = load i8, i8* %g4
64 %t5 = load i8, i8* %g5
65 %t6 = load i8, i8* %g6
66 %t7 = load i8, i8* %g7
67
68 %z0 = zext i8 %t0 to i64
69 %z1 = zext i8 %t1 to i64
70 %z2 = zext i8 %t2 to i64
71 %z3 = zext i8 %t3 to i64
72 %z4 = zext i8 %t4 to i64
73 %z5 = zext i8 %t5 to i64
74 %z6 = zext i8 %t6 to i64
75 %z7 = zext i8 %t7 to i64
76
77 %sh0 = shl nuw i64 %z0, 56
78 %sh1 = shl nuw nsw i64 %z1, 48
79 %sh2 = shl nuw nsw i64 %z2, 40
80 %sh3 = shl nuw nsw i64 %z3, 32
81 %sh4 = shl nuw nsw i64 %z4, 24
82 %sh5 = shl nuw nsw i64 %z5, 16
83 %sh6 = shl nuw nsw i64 %z6, 8
84 ; %sh7 = shl nuw nsw i64 %z7, 0 <-- missing phantom shift
85
86 %or01 = or i64 %sh0, %sh1
87 %or012 = or i64 %or01, %sh2
88 %or0123 = or i64 %or012, %sh3
89 %or01234 = or i64 %or0123, %sh4
90 %or012345 = or i64 %or01234, %sh5
91 %or0123456 = or i64 %or012345, %sh6
92 %or01234567 = or i64 %or0123456, %z7
93 ret i64 %or01234567
94 }
95
96 define i64 @load_bswap_nop_shift(%v8i8* %p) {
97 ; CHECK-LABEL: @load_bswap_nop_shift(
98 ; CHECK-NEXT: [[G0:%.*]] = getelementptr inbounds [[V8I8:%.*]], %v8i8* [[P:%.*]], i64 0, i32 0
99 ; CHECK-NEXT: [[G1:%.*]] = getelementptr inbounds [[V8I8]], %v8i8* [[P]], i64 0, i32 1
100 ; CHECK-NEXT: [[G2:%.*]] = getelementptr inbounds [[V8I8]], %v8i8* [[P]], i64 0, i32 2
101 ; CHECK-NEXT: [[G3:%.*]] = getelementptr inbounds [[V8I8]], %v8i8* [[P]], i64 0, i32 3
102 ; CHECK-NEXT: [[G4:%.*]] = getelementptr inbounds [[V8I8]], %v8i8* [[P]], i64 0, i32 4
103 ; CHECK-NEXT: [[G5:%.*]] = getelementptr inbounds [[V8I8]], %v8i8* [[P]], i64 0, i32 5
104 ; CHECK-NEXT: [[G6:%.*]] = getelementptr inbounds [[V8I8]], %v8i8* [[P]], i64 0, i32 6
105 ; CHECK-NEXT: [[G7:%.*]] = getelementptr inbounds [[V8I8]], %v8i8* [[P]], i64 0, i32 7
106 ; CHECK-NEXT: [[TMP1:%.*]] = bitcast i8* [[G0]] to <8 x i8>*
107 ; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i8>, <8 x i8>* [[TMP1]], align 1
108 ; CHECK-NEXT: [[TMP3:%.*]] = zext <8 x i8> [[TMP2]] to <8 x i64>
109 ; CHECK-NEXT: [[TMP4:%.*]] = shl nuw <8 x i64> [[TMP3]],
110 ; CHECK-NEXT: [[OR01:%.*]] = or i64 undef, undef
111 ; CHECK-NEXT: [[OR012:%.*]] = or i64 [[OR01]], undef
112 ; CHECK-NEXT: [[OR0123:%.*]] = or i64 [[OR012]], undef
113 ; CHECK-NEXT: [[OR01234:%.*]] = or i64 [[OR0123]], undef
114 ; CHECK-NEXT: [[OR012345:%.*]] = or i64 [[OR01234]], undef
115 ; CHECK-NEXT: [[OR0123456:%.*]] = or i64 [[OR012345]], undef
116 ; CHECK-NEXT: [[RDX_SHUF:%.*]] = shufflevector <8 x i64> [[TMP4]], <8 x i64> undef, <8 x i32>
117 ; CHECK-NEXT: [[BIN_RDX:%.*]] = or <8 x i64> [[TMP4]], [[RDX_SHUF]]
118 ; CHECK-NEXT: [[RDX_SHUF1:%.*]] = shufflevector <8 x i64> [[BIN_RDX]], <8 x i64> undef, <8 x i32>
119 ; CHECK-NEXT: [[BIN_RDX2:%.*]] = or <8 x i64> [[BIN_RDX]], [[RDX_SHUF1]]
120 ; CHECK-NEXT: [[RDX_SHUF3:%.*]] = shufflevector <8 x i64> [[BIN_RDX2]], <8 x i64> undef, <8 x i32>
121 ; CHECK-NEXT: [[BIN_RDX4:%.*]] = or <8 x i64> [[BIN_RDX2]], [[RDX_SHUF3]]
122 ; CHECK-NEXT: [[TMP5:%.*]] = extractelement <8 x i64> [[BIN_RDX4]], i32 0
123 ; CHECK-NEXT: [[OR01234567:%.*]] = or i64 [[OR0123456]], undef
124 ; CHECK-NEXT: ret i64 [[TMP5]]
125 ;
126 %g0 = getelementptr inbounds %v8i8, %v8i8* %p, i64 0, i32 0
127 %g1 = getelementptr inbounds %v8i8, %v8i8* %p, i64 0, i32 1
128 %g2 = getelementptr inbounds %v8i8, %v8i8* %p, i64 0, i32 2
129 %g3 = getelementptr inbounds %v8i8, %v8i8* %p, i64 0, i32 3
130 %g4 = getelementptr inbounds %v8i8, %v8i8* %p, i64 0, i32 4
131 %g5 = getelementptr inbounds %v8i8, %v8i8* %p, i64 0, i32 5
132 %g6 = getelementptr inbounds %v8i8, %v8i8* %p, i64 0, i32 6
133 %g7 = getelementptr inbounds %v8i8, %v8i8* %p, i64 0, i32 7
134
135 %t0 = load i8, i8* %g0
136 %t1 = load i8, i8* %g1
137 %t2 = load i8, i8* %g2
138 %t3 = load i8, i8* %g3
139 %t4 = load i8, i8* %g4
140 %t5 = load i8, i8* %g5
141 %t6 = load i8, i8* %g6
142 %t7 = load i8, i8* %g7
143
144 %z0 = zext i8 %t0 to i64
145 %z1 = zext i8 %t1 to i64
146 %z2 = zext i8 %t2 to i64
147 %z3 = zext i8 %t3 to i64
148 %z4 = zext i8 %t4 to i64
149 %z5 = zext i8 %t5 to i64
150 %z6 = zext i8 %t6 to i64
151 %z7 = zext i8 %t7 to i64
152
153 %sh0 = shl nuw i64 %z0, 56
154 %sh1 = shl nuw nsw i64 %z1, 48
155 %sh2 = shl nuw nsw i64 %z2, 40
156 %sh3 = shl nuw nsw i64 %z3, 32
157 %sh4 = shl nuw nsw i64 %z4, 24
158 %sh5 = shl nuw nsw i64 %z5, 16
159 %sh6 = shl nuw nsw i64 %z6, 8
160 %sh7 = shl nuw nsw i64 %z7, 0
161
162 %or01 = or i64 %sh0, %sh1
163 %or012 = or i64 %or01, %sh2
164 %or0123 = or i64 %or012, %sh3
165 %or01234 = or i64 %or0123, %sh4
166 %or012345 = or i64 %or01234, %sh5
167 %or0123456 = or i64 %or012345, %sh6
168 %or01234567 = or i64 %or0123456, %sh7
169 ret i64 %or01234567
170 }
171
172 ; https://bugs.llvm.org/show_bug.cgi?id=42708
173
174 define i64 @load64le(i8* %arg) {
175 ; CHECK-LABEL: @load64le(
176 ; CHECK-NEXT: [[G1:%.*]] = getelementptr inbounds i8, i8* [[ARG:%.*]], i64 1
177 ; CHECK-NEXT: [[G2:%.*]] = getelementptr inbounds i8, i8* [[ARG]], i64 2
178 ; CHECK-NEXT: [[G3:%.*]] = getelementptr inbounds i8, i8* [[ARG]], i64 3
179 ; CHECK-NEXT: [[G4:%.*]] = getelementptr inbounds i8, i8* [[ARG]], i64 4
180 ; CHECK-NEXT: [[G5:%.*]] = getelementptr inbounds i8, i8* [[ARG]], i64 5
181 ; CHECK-NEXT: [[G6:%.*]] = getelementptr inbounds i8, i8* [[ARG]], i64 6
182 ; CHECK-NEXT: [[G7:%.*]] = getelementptr inbounds i8, i8* [[ARG]], i64 7
183 ; CHECK-NEXT: [[LD0:%.*]] = load i8, i8* [[ARG]], align 1
184 ; CHECK-NEXT: [[TMP1:%.*]] = bitcast i8* [[G1]] to <4 x i8>*
185 ; CHECK-NEXT: [[TMP2:%.*]] = load <4 x i8>, <4 x i8>* [[TMP1]], align 1
186 ; CHECK-NEXT: [[LD5:%.*]] = load i8, i8* [[G5]], align 1
187 ; CHECK-NEXT: [[LD6:%.*]] = load i8, i8* [[G6]], align 1
188 ; CHECK-NEXT: [[LD7:%.*]] = load i8, i8* [[G7]], align 1
189 ; CHECK-NEXT: [[Z0:%.*]] = zext i8 [[LD0]] to i64
190 ; CHECK-NEXT: [[TMP3:%.*]] = zext <4 x i8> [[TMP2]] to <4 x i64>
191 ; CHECK-NEXT: [[Z5:%.*]] = zext i8 [[LD5]] to i64
192 ; CHECK-NEXT: [[Z6:%.*]] = zext i8 [[LD6]] to i64
193 ; CHECK-NEXT: [[Z7:%.*]] = zext i8 [[LD7]] to i64
194 ; CHECK-NEXT: [[TMP4:%.*]] = shl nuw nsw <4 x i64> [[TMP3]],
195 ; CHECK-NEXT: [[S5:%.*]] = shl nuw nsw i64 [[Z5]], 40
196 ; CHECK-NEXT: [[S6:%.*]] = shl nuw nsw i64 [[Z6]], 48
197 ; CHECK-NEXT: [[S7:%.*]] = shl nuw i64 [[Z7]], 56
198 ; CHECK-NEXT: [[O1:%.*]] = or i64 undef, [[Z0]]
199 ; CHECK-NEXT: [[O2:%.*]] = or i64 [[O1]], undef
200 ; CHECK-NEXT: [[O3:%.*]] = or i64 [[O2]], undef
201 ; CHECK-NEXT: [[O4:%.*]] = or i64 [[O3]], undef
202 ; CHECK-NEXT: [[O5:%.*]] = or i64 [[O4]], [[S5]]
203 ; CHECK-NEXT: [[O6:%.*]] = or i64 [[O5]], [[S6]]
204 ; CHECK-NEXT: [[RDX_SHUF:%.*]] = shufflevector <4 x i64> [[TMP4]], <4 x i64> undef, <4 x i32>
205 ; CHECK-NEXT: [[BIN_RDX:%.*]] = or <4 x i64> [[TMP4]], [[RDX_SHUF]]
206 ; CHECK-NEXT: [[RDX_SHUF1:%.*]] = shufflevector <4 x i64> [[BIN_RDX]], <4 x i64> undef, <4 x i32>
207 ; CHECK-NEXT: [[BIN_RDX2:%.*]] = or <4 x i64> [[BIN_RDX]], [[RDX_SHUF1]]
208 ; CHECK-NEXT: [[TMP5:%.*]] = extractelement <4 x i64> [[BIN_RDX2]], i32 0
209 ; CHECK-NEXT: [[TMP6:%.*]] = or i64 [[TMP5]], [[S5]]
210 ; CHECK-NEXT: [[TMP7:%.*]] = or i64 [[TMP6]], [[S6]]
211 ; CHECK-NEXT: [[TMP8:%.*]] = or i64 [[TMP7]], [[S7]]
212 ; CHECK-NEXT: [[OP_EXTRA:%.*]] = or i64 [[TMP8]], [[Z0]]
213 ; CHECK-NEXT: [[O7:%.*]] = or i64 [[O6]], [[S7]]
214 ; CHECK-NEXT: ret i64 [[OP_EXTRA]]
215 ;
216 %g1 = getelementptr inbounds i8, i8* %arg, i64 1
217 %g2 = getelementptr inbounds i8, i8* %arg, i64 2
218 %g3 = getelementptr inbounds i8, i8* %arg, i64 3
219 %g4 = getelementptr inbounds i8, i8* %arg, i64 4
220 %g5 = getelementptr inbounds i8, i8* %arg, i64 5
221 %g6 = getelementptr inbounds i8, i8* %arg, i64 6
222 %g7 = getelementptr inbounds i8, i8* %arg, i64 7
223
224 %ld0 = load i8, i8* %arg, align 1
225 %ld1 = load i8, i8* %g1, align 1
226 %ld2 = load i8, i8* %g2, align 1
227 %ld3 = load i8, i8* %g3, align 1
228 %ld4 = load i8, i8* %g4, align 1
229 %ld5 = load i8, i8* %g5, align 1
230 %ld6 = load i8, i8* %g6, align 1
231 %ld7 = load i8, i8* %g7, align 1
232
233 %z0 = zext i8 %ld0 to i64
234 %z1 = zext i8 %ld1 to i64
235 %z2 = zext i8 %ld2 to i64
236 %z3 = zext i8 %ld3 to i64
237 %z4 = zext i8 %ld4 to i64
238 %z5 = zext i8 %ld5 to i64
239 %z6 = zext i8 %ld6 to i64
240 %z7 = zext i8 %ld7 to i64
241
242 ; %s0 = shl nuw nsw i64 %z0, 0 <-- missing phantom shift
243 %s1 = shl nuw nsw i64 %z1, 8
244 %s2 = shl nuw nsw i64 %z2, 16
245 %s3 = shl nuw nsw i64 %z3, 24
246 %s4 = shl nuw nsw i64 %z4, 32
247 %s5 = shl nuw nsw i64 %z5, 40
248 %s6 = shl nuw nsw i64 %z6, 48
249 %s7 = shl nuw i64 %z7, 56
250
251 %o1 = or i64 %s1, %z0
252 %o2 = or i64 %o1, %s2
253 %o3 = or i64 %o2, %s3
254 %o4 = or i64 %o3, %s4
255 %o5 = or i64 %o4, %s5
256 %o6 = or i64 %o5, %s6
257 %o7 = or i64 %o6, %s7
258 ret i64 %o7
259 }
260
261 define i64 @load64le_nop_shift(i8* %arg) {
262 ; CHECK-LABEL: @load64le_nop_shift(
263 ; CHECK-NEXT: [[G1:%.*]] = getelementptr inbounds i8, i8* [[ARG:%.*]], i64 1
264 ; CHECK-NEXT: [[G2:%.*]] = getelementptr inbounds i8, i8* [[ARG]], i64 2
265 ; CHECK-NEXT: [[G3:%.*]] = getelementptr inbounds i8, i8* [[ARG]], i64 3
266 ; CHECK-NEXT: [[G4:%.*]] = getelementptr inbounds i8, i8* [[ARG]], i64 4
267 ; CHECK-NEXT: [[G5:%.*]] = getelementptr inbounds i8, i8* [[ARG]], i64 5
268 ; CHECK-NEXT: [[G6:%.*]] = getelementptr inbounds i8, i8* [[ARG]], i64 6
269 ; CHECK-NEXT: [[G7:%.*]] = getelementptr inbounds i8, i8* [[ARG]], i64 7
270 ; CHECK-NEXT: [[TMP1:%.*]] = bitcast i8* [[ARG]] to <8 x i8>*
271 ; CHECK-NEXT: [[TMP2:%.*]] = load <8 x i8>, <8 x i8>* [[TMP1]], align 1
272 ; CHECK-NEXT: [[TMP3:%.*]] = zext <8 x i8> [[TMP2]] to <8 x i64>
273 ; CHECK-NEXT: [[TMP4:%.*]] = shl nuw <8 x i64> [[TMP3]],
274 ; CHECK-NEXT: [[O1:%.*]] = or i64 undef, undef
275 ; CHECK-NEXT: [[O2:%.*]] = or i64 [[O1]], undef
276 ; CHECK-NEXT: [[O3:%.*]] = or i64 [[O2]], undef
277 ; CHECK-NEXT: [[O4:%.*]] = or i64 [[O3]], undef
278 ; CHECK-NEXT: [[O5:%.*]] = or i64 [[O4]], undef
279 ; CHECK-NEXT: [[O6:%.*]] = or i64 [[O5]], undef
280 ; CHECK-NEXT: [[RDX_SHUF:%.*]] = shufflevector <8 x i64> [[TMP4]], <8 x i64> undef, <8 x i32>
281 ; CHECK-NEXT: [[BIN_RDX:%.*]] = or <8 x i64> [[TMP4]], [[RDX_SHUF]]
282 ; CHECK-NEXT: [[RDX_SHUF1:%.*]] = shufflevector <8 x i64> [[BIN_RDX]], <8 x i64> undef, <8 x i32>
283 ; CHECK-NEXT: [[BIN_RDX2:%.*]] = or <8 x i64> [[BIN_RDX]], [[RDX_SHUF1]]
284 ; CHECK-NEXT: [[RDX_SHUF3:%.*]] = shufflevector <8 x i64> [[BIN_RDX2]], <8 x i64> undef, <8 x i32>
285 ; CHECK-NEXT: [[BIN_RDX4:%.*]] = or <8 x i64> [[BIN_RDX2]], [[RDX_SHUF3]]
286 ; CHECK-NEXT: [[TMP5:%.*]] = extractelement <8 x i64> [[BIN_RDX4]], i32 0
287 ; CHECK-NEXT: [[O7:%.*]] = or i64 [[O6]], undef
288 ; CHECK-NEXT: ret i64 [[TMP5]]
289 ;
290 %g1 = getelementptr inbounds i8, i8* %arg, i64 1
291 %g2 = getelementptr inbounds i8, i8* %arg, i64 2
292 %g3 = getelementptr inbounds i8, i8* %arg, i64 3
293 %g4 = getelementptr inbounds i8, i8* %arg, i64 4
294 %g5 = getelementptr inbounds i8, i8* %arg, i64 5
295 %g6 = getelementptr inbounds i8, i8* %arg, i64 6
296 %g7 = getelementptr inbounds i8, i8* %arg, i64 7
297
298 %ld0 = load i8, i8* %arg, align 1
299 %ld1 = load i8, i8* %g1, align 1
300 %ld2 = load i8, i8* %g2, align 1
301 %ld3 = load i8, i8* %g3, align 1
302 %ld4 = load i8, i8* %g4, align 1
303 %ld5 = load i8, i8* %g5, align 1
304 %ld6 = load i8, i8* %g6, align 1
305 %ld7 = load i8, i8* %g7, align 1
306
307 %z0 = zext i8 %ld0 to i64
308 %z1 = zext i8 %ld1 to i64
309 %z2 = zext i8 %ld2 to i64
310 %z3 = zext i8 %ld3 to i64
311 %z4 = zext i8 %ld4 to i64
312 %z5 = zext i8 %ld5 to i64
313 %z6 = zext i8 %ld6 to i64
314 %z7 = zext i8 %ld7 to i64
315
316 %s0 = shl nuw nsw i64 %z0, 0
317 %s1 = shl nuw nsw i64 %z1, 8
318 %s2 = shl nuw nsw i64 %z2, 16
319 %s3 = shl nuw nsw i64 %z3, 24
320 %s4 = shl nuw nsw i64 %z4, 32
321 %s5 = shl nuw nsw i64 %z5, 40
322 %s6 = shl nuw nsw i64 %z6, 48
323 %s7 = shl nuw i64 %z7, 56
324
325 %o1 = or i64 %s1, %s0
326 %o2 = or i64 %o1, %s2
327 %o3 = or i64 %o2, %s3
328 %o4 = or i64 %o3, %s4
329 %o5 = or i64 %o4, %s5
330 %o6 = or i64 %o5, %s6
331 %o7 = or i64 %o6, %s7
332 ret i64 %o7
333 }