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Add notes on instruction selection pass git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193 91177308-0d34-0410-b5e6-96231b3b80d8 Chris Lattner 18 years ago
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0 Date: Sun, 8 Jul 2001 09:37:22 -0500
1 From: Vikram S. Adve
2 To: Ruchira Sasanka
3 Cc: Chris Lattner
4 Subject: machine instruction operands
5
6 Ruchira,
7
8 When generating machine instructions, I have to make several choices about
9 operands. For cases were a register is required, there are 3 cases:
10
11 1. The register is for a Value* that is already in the VM code.
12
13 2. The register is for a value that is not in the VM code, usually because 2
14 machine instructions get generated for a single VM instruction (and the
15 register holds the result of the first m/c instruction and is used by the
16 second m/c instruction).
17
18 3. The register is a pre-determined machine register.
19
20 E.g, for this VM instruction:
21 ptr = alloca type, numElements
22 I have to generate 2 machine instructions:
23 reg = mul constant, numElements
24 ptr = add %sp, reg
25
26 Each machine instruction is of class MachineInstr.
27 It has a vector of operands. All register operands have type MO_REGISTER.
28 The 3 types of register operands are marked using this enum:
29
30 enum VirtualRegisterType {
31 MO_VMVirtualReg, // virtual register for *value
32 MO_MInstrVirtualReg, // virtual register for result of *minstr
33 MO_MachineReg // pre-assigned machine register `regNum'
34 } vregType;
35
36 Here's how this affects register allocation:
37
38 1. MO_VMVirtualReg is the standard case: you just do the register
39 allocation.
40
41 2. MO_MInstrVirtualReg is the case where there is a hidden register being
42 used. You should decide how you want to handle it, e.g., do you want do
43 create a Value object during the preprocessing phase to make the value
44 explicit (like for address register for the RETURN instruction).
45
46 3. For case MO_MachineReg, you don't need to do anything, at least for
47 SPARC. The only machine regs I am using so far are %g0 and %sp.
48
49 --Vikram
50
0 Date: Sun, 8 Jul 2001 10:02:20 -0500
1 From: Vikram S. Adve
2 To: vadve@cs.uiuc.edu, Ruchira Sasanka
3 Cc: Chris Lattner
4 Subject: RE: machine instruction operands
5
6 I got interrupted and forgot to explain the example. In that case:
7
8 reg will be the 3rd operand of MUL and it will be of type
9 MO_MInstrVirtualReg. The field MachineInstr* minstr will point to the
10 instruction that computes reg.
11
12 numElements will be an immediate constant, not a register.
13
14 %sp will be operand 1 of ADD and it will be of type MO_MachineReg. The
15 field regNum identifies the register.
16
17 numElements will be operand 2 of ADD and it will be of type
18 MO_VMVirtualReg. The field Value* value identifies the value.
19
20 ptr will be operand 3 of ADD will also be %sp, i.e., of
21 type MO_MachineReg. regNum identifies the register.
22
23 --Vikram
24