llvm.org GIT mirror llvm / f595141
Revert 107840 107839 107813 107804 107800 107797 107791. Debug info intrinsics win for now. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107850 91177308-0d34-0410-b5e6-96231b3b80d8 Dan Gohman 10 years ago
22 changed file(s) with 373 addition(s) and 546 deletion(s). Raw diff Collapse all Expand all
187187 /// CheckReturn - Analyze the return values of a function, returning
188188 /// true if the return can be performed without sret-demotion, and
189189 /// false otherwise.
190 bool CheckReturn(const SmallVectorImpl<ISD::OutputArg> &ArgsFlags,
190 bool CheckReturn(const SmallVectorImpl<EVT> &OutTys,
191 const SmallVectorImpl &ArgsFlags,
191192 CCAssignFn Fn);
192193
193194 /// AnalyzeCallOperands - Analyze the outgoing arguments to a call,
1818 #include "llvm/ADT/SmallSet.h"
1919 #endif
2020 #include "llvm/CodeGen/ValueTypes.h"
21 #include "llvm/CodeGen/MachineBasicBlock.h"
2221
2322 namespace llvm {
2423
4443 /// lowering, but runs quickly.
4544 class FastISel {
4645 protected:
46 MachineBasicBlock *MBB;
4747 DenseMap LocalValueMap;
4848 FunctionLoweringInfo &FuncInfo;
4949 MachineRegisterInfo &MRI;
5555 const TargetInstrInfo &TII;
5656 const TargetLowering &TLI;
5757 const TargetRegisterInfo &TRI;
58 MachineBasicBlock::iterator LastLocalValue;
58 bool IsBottomUp;
5959
6060 public:
61 /// getLastLocalValue - Return the position of the last instruction
62 /// emitted for materializing constants for use in the current block.
63 MachineBasicBlock::iterator getLastLocalValue() { return LastLocalValue; }
64
6561 /// startNewBlock - Set the current block to which generated machine
6662 /// instructions will be appended, and clear the local CSE map.
6763 ///
68 void startNewBlock();
64 void startNewBlock(MachineBasicBlock *mbb) {
65 setCurrentBlock(mbb);
66 LocalValueMap.clear();
67 }
68
69 /// setCurrentBlock - Set the current block to which generated machine
70 /// instructions will be appended.
71 ///
72 void setCurrentBlock(MachineBasicBlock *mbb) {
73 MBB = mbb;
74 }
6975
7076 /// getCurDebugLoc() - Return current debug location information.
7177 DebugLoc getCurDebugLoc() const { return DL; }
2424 #endif
2525 #include "llvm/CodeGen/ValueTypes.h"
2626 #include "llvm/CodeGen/ISDOpcodes.h"
27 #include "llvm/CodeGen/MachineBasicBlock.h"
2827 #include "llvm/Support/CallSite.h"
2928 #include
3029
7978 /// ArgDbgValues - A list of DBG_VALUE instructions created during isel for
8079 /// function arguments that are inserted after scheduling is completed.
8180 SmallVector ArgDbgValues;
82
83 /// MBB - The current block.
84 MachineBasicBlock *MBB;
85
86 /// MBB - The current insert position inside the current block.
87 MachineBasicBlock::iterator InsertPt;
8881
8982 #ifndef NDEBUG
9083 SmallSet CatchInfoLost;
279279 SDNode *MorphNode(SDNode *Node, unsigned TargetOpc, SDVTList VTs,
280280 const SDValue *Ops, unsigned NumOps, unsigned EmitNodeInfo);
281281
282 void PrepareEHLandingPad();
282 void PrepareEHLandingPad(MachineBasicBlock *BB);
283283 void SelectAllBasicBlocks(const Function &Fn);
284 void FinishBasicBlock();
285
286 void SelectBasicBlock(BasicBlock::const_iterator Begin,
287 BasicBlock::const_iterator End,
288 bool &HadTailCall);
289 void CodeGenAndEmitDAG();
284 void FinishBasicBlock(MachineBasicBlock *BB);
285
286 MachineBasicBlock *SelectBasicBlock(MachineBasicBlock *BB,
287 BasicBlock::const_iterator Begin,
288 BasicBlock::const_iterator End,
289 bool &HadTailCall);
290 MachineBasicBlock *CodeGenAndEmitDAG(MachineBasicBlock *BB);
290291 void LowerArguments(const BasicBlock *BB);
291292
292293 void ComputeLiveOutVRegInfo();
2323
2424 #include "llvm/CallingConv.h"
2525 #include "llvm/InlineAsm.h"
26 #include "llvm/Attributes.h"
2726 #include "llvm/CodeGen/SelectionDAGNodes.h"
2827 #include "llvm/CodeGen/RuntimeLibcalls.h"
2928 #include "llvm/ADT/APFloat.h"
11591158 /// registers. If false is returned, an sret-demotion is performed.
11601159 ///
11611160 virtual bool CanLowerReturn(CallingConv::ID CallConv, bool isVarArg,
1162 const SmallVectorImpl<ISD::OutputArg> &Outs,
1161 const SmallVectorImpl<EVT> &OutTys,
1162 const SmallVectorImpl &ArgsFlags,
11631163 LLVMContext &Context) const
11641164 {
11651165 // Return true by default to get preexisting behavior.
16551655 /// optimization.
16561656 bool benefitFromCodePlacementOpt;
16571657 };
1658
1659 /// GetReturnInfo - Given an LLVM IR type and return type attributes,
1660 /// compute the return value EVTs and flags, and optionally also
1661 /// the offsets, if the return value is being lowered to memory.
1662 void GetReturnInfo(const Type* ReturnType, Attributes attr,
1663 SmallVectorImpl &Outs,
1664 const TargetLowering &TLI,
1665 SmallVectorImpl *Offsets = 0);
1666
16671658 } // end llvm namespace
16681659
16691660 #endif
7979
8080 /// CheckReturn - Analyze the return values of a function, returning true if
8181 /// the return can be performed without sret-demotion, and false otherwise.
82 bool CCState::CheckReturn(const SmallVectorImpl<ISD::OutputArg> &Outs,
82 bool CCState::CheckReturn(const SmallVectorImpl<EVT> &OutTys,
83 const SmallVectorImpl &ArgsFlags,
8384 CCAssignFn Fn) {
8485 // Determine which register each value should be copied into.
85 for (unsigned i = 0, e = Outs.size(); i != e; ++i) {
86 EVT VT = Outs[i].VT;
87 ISD::ArgFlagsTy ArgFlags = Outs[i].Flags;
86 for (unsigned i = 0, e = OutTys.size(); i != e; ++i) {
87 EVT VT = OutTys[i];
88 ISD::ArgFlagsTy ArgFlags = ArgsFlags[i];
8889 if (Fn(i, VT, VT, CCValAssign::Full, ArgFlags, *this))
8990 return false;
9091 }
328328 if (OptLevel != CodeGenOpt::None)
329329 PM.add(createOptimizePHIsPass());
330330
331 // Delete dead machine instructions regardless of optimization level.
332 //
333 // At -O0, fast-isel frequently creates dead instructions.
334 //
335 // With optimization, dead code should already be eliminated. However
336 // there is one known exception: lowered code for arguments that are only
337 // used by tail calls, where the tail calls reuse the incoming stack
338 // arguments directly (see t11 in test/CodeGen/X86/sibcall.ll).
339 PM.add(createDeadMachineInstructionElimPass());
340 printAndVerify(PM, "After codegen DCE pass",
341 /* allowDoubleDefs= */ true);
342
331343 if (OptLevel != CodeGenOpt::None) {
332 // With optimization, dead code should already be eliminated. However
333 // there is one known exception: lowered code for arguments that are only
334 // used by tail calls, where the tail calls reuse the incoming stack
335 // arguments directly (see t11 in test/CodeGen/X86/sibcall.ll).
336 PM.add(createDeadMachineInstructionElimPass());
337 printAndVerify(PM, "After codegen DCE pass",
338 /* allowDoubleDefs= */ true);
339
340344 PM.add(createOptimizeExtsPass());
341345 if (!DisableMachineLICM)
342346 PM.add(createMachineLICMPass());
5656 #include "llvm/Support/ErrorHandling.h"
5757 using namespace llvm;
5858
59 /// startNewBlock - Set the current block to which generated machine
60 /// instructions will be appended, and clear the local CSE map.
61 ///
62 void FastISel::startNewBlock() {
63 LocalValueMap.clear();
64
65 // Start out as end(), meaining no local-value instructions have
66 // been emitted.
67 LastLocalValue = FuncInfo.MBB->end();
68 }
69
7059 bool FastISel::hasTrivialKill(const Value *V) const {
7160 // Don't consider constants or arguments to have trivial kills.
7261 const Instruction *I = dyn_cast(V);
119108
120109 // In bottom-up mode, just create the virtual register which will be used
121110 // to hold the value. It will be materialized later.
122 if (isa(V) &&
123 (!isa(V) ||
124 !FuncInfo.StaticAllocaMap.count(cast(V)))) {
111 if (IsBottomUp) {
125112 Reg = createResultReg(TLI.getRegClassFor(VT));
126 FuncInfo.ValueMap[V] = Reg;
113 if (isa(V))
114 FuncInfo.ValueMap[V] = Reg;
115 else
116 LocalValueMap[V] = Reg;
127117 return Reg;
128118 }
129119
178168 Reg = lookUpRegForValue(Op);
179169 } else if (isa(V)) {
180170 Reg = createResultReg(TLI.getRegClassFor(VT));
181 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
182 TII.get(TargetOpcode::IMPLICIT_DEF), Reg);
171 BuildMI(MBB, DL, TII.get(TargetOpcode::IMPLICIT_DEF), Reg);
183172 }
184173
185174 // If target-independent code couldn't handle the value, give target-specific
189178
190179 // Don't cache constant materializations in the general ValueMap.
191180 // To do so would require tracking what uses they dominate.
192 if (Reg != 0) {
181 if (Reg != 0)
193182 LocalValueMap[V] = Reg;
194 LastLocalValue = MRI.getVRegDef(Reg);
195 }
196183 return Reg;
197184 }
198185
221208
222209 unsigned &AssignedReg = FuncInfo.ValueMap[I];
223210 if (AssignedReg == 0)
224 // Use the new register.
225211 AssignedReg = Reg;
226212 else if (Reg != AssignedReg) {
227 // We already have a register for this value. Replace uses of
228 // the existing register with uses of the new one.
229 MRI.replaceRegWith(AssignedReg, Reg);
230 // Replace uses of the existing register in PHINodesToUpdate too.
231 for (unsigned i = 0, e = FuncInfo.PHINodesToUpdate.size(); i != e; ++i)
232 if (FuncInfo.PHINodesToUpdate[i].second == AssignedReg)
233 FuncInfo.PHINodesToUpdate[i].second = Reg;
234 // And update the ValueMap.
235 AssignedReg = Reg;
236 }
237
213 const TargetRegisterClass *RegClass = MRI.getRegClass(Reg);
214 TII.copyRegToReg(*MBB, MBB->end(), AssignedReg,
215 Reg, RegClass, RegClass, DL);
216 }
238217 return AssignedReg;
239218 }
240219
454433 if (!V) {
455434 // Currently the optimizer can produce this; insert an undef to
456435 // help debugging. Probably the optimizer should not do this.
457 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
458 .addReg(0U).addImm(DI->getOffset())
459 .addMetadata(DI->getVariable());
436 BuildMI(MBB, DL, II).addReg(0U).addImm(DI->getOffset()).
437 addMetadata(DI->getVariable());
460438 } else if (const ConstantInt *CI = dyn_cast(V)) {
461 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
462 .addImm(CI->getZExtValue()).addImm(DI->getOffset())
463 .addMetadata(DI->getVariable());
439 BuildMI(MBB, DL, II).addImm(CI->getZExtValue()).addImm(DI->getOffset()).
440 addMetadata(DI->getVariable());
464441 } else if (const ConstantFP *CF = dyn_cast(V)) {
465 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
466 .addFPImm(CF).addImm(DI->getOffset())
467 .addMetadata(DI->getVariable());
442 BuildMI(MBB, DL, II).addFPImm(CF).addImm(DI->getOffset()).
443 addMetadata(DI->getVariable());
468444 } else if (unsigned Reg = lookUpRegForValue(V)) {
469 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
470 .addReg(Reg, RegState::Debug).addImm(DI->getOffset())
471 .addMetadata(DI->getVariable());
445 BuildMI(MBB, DL, II).addReg(Reg, RegState::Debug).addImm(DI->getOffset()).
446 addMetadata(DI->getVariable());
472447 } else {
473448 // We can't yet handle anything else here because it would require
474449 // generating code, thus altering codegen because of debug info.
475450 // Insert an undef so we can see what we dropped.
476 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
477 .addReg(0U).addImm(DI->getOffset())
478 .addMetadata(DI->getVariable());
451 BuildMI(MBB, DL, II).addReg(0U).addImm(DI->getOffset()).
452 addMetadata(DI->getVariable());
479453 }
480454 return true;
481455 }
484458 switch (TLI.getOperationAction(ISD::EXCEPTIONADDR, VT)) {
485459 default: break;
486460 case TargetLowering::Expand: {
487 assert(FuncInfo.MBB->isLandingPad() &&
488 "Call to eh.exception not in landing pad!");
461 assert(MBB->isLandingPad() && "Call to eh.exception not in landing pad!");
489462 unsigned Reg = TLI.getExceptionAddressRegister();
490463 const TargetRegisterClass *RC = TLI.getRegClassFor(VT);
491464 unsigned ResultReg = createResultReg(RC);
492 bool InsertedCopy = TII.copyRegToReg(*FuncInfo.MBB, FuncInfo.InsertPt,
493 ResultReg, Reg, RC, RC, DL);
465 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
466 Reg, RC, RC, DL);
494467 assert(InsertedCopy && "Can't copy address registers!");
495468 InsertedCopy = InsertedCopy;
496469 UpdateValueMap(I, ResultReg);
504477 switch (TLI.getOperationAction(ISD::EHSELECTION, VT)) {
505478 default: break;
506479 case TargetLowering::Expand: {
507 if (FuncInfo.MBB->isLandingPad())
508 AddCatchInfo(*cast(I), &FuncInfo.MF->getMMI(), FuncInfo.MBB);
480 if (MBB->isLandingPad())
481 AddCatchInfo(*cast(I), &FuncInfo.MF->getMMI(), MBB);
509482 else {
510483 #ifndef NDEBUG
511484 FuncInfo.CatchInfoLost.insert(cast(I));
512485 #endif
513486 // FIXME: Mark exception selector register as live in. Hack for PR1508.
514487 unsigned Reg = TLI.getExceptionSelectorRegister();
515 if (Reg) FuncInfo.MBB->addLiveIn(Reg);
488 if (Reg) MBB->addLiveIn(Reg);
516489 }
517490
518491 unsigned Reg = TLI.getExceptionSelectorRegister();
519492 EVT SrcVT = TLI.getPointerTy();
520493 const TargetRegisterClass *RC = TLI.getRegClassFor(SrcVT);
521494 unsigned ResultReg = createResultReg(RC);
522 bool InsertedCopy = TII.copyRegToReg(*FuncInfo.MBB, FuncInfo.InsertPt,
523 ResultReg, Reg, RC, RC, DL);
495 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg, Reg,
496 RC, RC, DL);
524497 assert(InsertedCopy && "Can't copy address registers!");
525498 InsertedCopy = InsertedCopy;
526499
639612 TargetRegisterClass* DstClass = TLI.getRegClassFor(DstVT);
640613 ResultReg = createResultReg(DstClass);
641614
642 bool InsertedCopy = TII.copyRegToReg(*FuncInfo.MBB, FuncInfo.InsertPt,
643 ResultReg, Op0,
644 DstClass, SrcClass, DL);
615 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
616 Op0, DstClass, SrcClass, DL);
645617 if (!InsertedCopy)
646618 ResultReg = 0;
647619 }
689661 /// the CFG.
690662 void
691663 FastISel::FastEmitBranch(MachineBasicBlock *MSucc, DebugLoc DL) {
692 if (FuncInfo.MBB->isLayoutSuccessor(MSucc)) {
664 if (MBB->isLayoutSuccessor(MSucc)) {
693665 // The unconditional fall-through case, which needs no instructions.
694666 } else {
695667 // The unconditional branch case.
696 TII.InsertBranch(*FuncInfo.MBB, MSucc, NULL,
697 SmallVector(), DL);
698 }
699 FuncInfo.MBB->addSuccessor(MSucc);
668 TII.InsertBranch(*MBB, MSucc, NULL, SmallVector(), DL);
669 }
670 MBB->addSuccessor(MSucc);
700671 }
701672
702673 /// SelectFNeg - Emit an FNeg operation.
755726 BasicBlock::iterator ScanFrom = LI;
756727 if (const Value *V = FindAvailableLoadedValue(LI->getPointerOperand(),
757728 LI->getParent(), ScanFrom)) {
758 if (!isa(V) ||
759 cast(V)->getParent() == LI->getParent() ||
760 (isa(V) && FuncInfo.StaticAllocaMap.count(cast(V)))) {
761729 unsigned ResultReg = getRegForValue(V);
762730 if (ResultReg != 0) {
763731 UpdateValueMap(I, ResultReg);
764732 return true;
765 }
766733 }
767734 }
768735 }
886853 }
887854
888855 FastISel::FastISel(FunctionLoweringInfo &funcInfo)
889 : FuncInfo(funcInfo),
856 : MBB(0),
857 FuncInfo(funcInfo),
890858 MRI(FuncInfo.MF->getRegInfo()),
891859 MFI(*FuncInfo.MF->getFrameInfo()),
892860 MCP(*FuncInfo.MF->getConstantPool()),
894862 TD(*TM.getTargetData()),
895863 TII(*TM.getInstrInfo()),
896864 TLI(*TM.getTargetLowering()),
897 TRI(*TM.getRegisterInfo()) {
865 TRI(*TM.getRegisterInfo()),
866 IsBottomUp(false) {
898867 }
899868
900869 FastISel::~FastISel() {}
1023992 unsigned ResultReg = createResultReg(RC);
1024993 const TargetInstrDesc &II = TII.get(MachineInstOpcode);
1025994
1026 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg);
995 BuildMI(MBB, DL, II, ResultReg);
1027996 return ResultReg;
1028997 }
1029998
10341003 const TargetInstrDesc &II = TII.get(MachineInstOpcode);
10351004
10361005 if (II.getNumDefs() >= 1)
1037 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
1038 .addReg(Op0, Op0IsKill * RegState::Kill);
1006 BuildMI(MBB, DL, II, ResultReg).addReg(Op0, Op0IsKill * RegState::Kill);
10391007 else {
1040 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
1041 .addReg(Op0, Op0IsKill * RegState::Kill);
1042 bool InsertedCopy = TII.copyRegToReg(*FuncInfo.MBB, FuncInfo.InsertPt,
1043 ResultReg, II.ImplicitDefs[0],
1044 RC, RC, DL);
1008 BuildMI(MBB, DL, II).addReg(Op0, Op0IsKill * RegState::Kill);
1009 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
1010 II.ImplicitDefs[0], RC, RC, DL);
10451011 if (!InsertedCopy)
10461012 ResultReg = 0;
10471013 }
10571023 const TargetInstrDesc &II = TII.get(MachineInstOpcode);
10581024
10591025 if (II.getNumDefs() >= 1)
1060 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
1026 BuildMI(MBB, DL, II, ResultReg)
10611027 .addReg(Op0, Op0IsKill * RegState::Kill)
10621028 .addReg(Op1, Op1IsKill * RegState::Kill);
10631029 else {
1064 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
1030 BuildMI(MBB, DL, II)
10651031 .addReg(Op0, Op0IsKill * RegState::Kill)
10661032 .addReg(Op1, Op1IsKill * RegState::Kill);
1067 bool InsertedCopy = TII.copyRegToReg(*FuncInfo.MBB, FuncInfo.InsertPt,
1068 ResultReg, II.ImplicitDefs[0],
1069 RC, RC, DL);
1033 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
1034 II.ImplicitDefs[0], RC, RC, DL);
10701035 if (!InsertedCopy)
10711036 ResultReg = 0;
10721037 }
10811046 const TargetInstrDesc &II = TII.get(MachineInstOpcode);
10821047
10831048 if (II.getNumDefs() >= 1)
1084 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
1049 BuildMI(MBB, DL, II, ResultReg)
10851050 .addReg(Op0, Op0IsKill * RegState::Kill)
10861051 .addImm(Imm);
10871052 else {
1088 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
1053 BuildMI(MBB, DL, II)
10891054 .addReg(Op0, Op0IsKill * RegState::Kill)
10901055 .addImm(Imm);
1091 bool InsertedCopy = TII.copyRegToReg(*FuncInfo.MBB, FuncInfo.InsertPt,
1092 ResultReg, II.ImplicitDefs[0],
1093 RC, RC, DL);
1056 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
1057 II.ImplicitDefs[0], RC, RC, DL);
10941058 if (!InsertedCopy)
10951059 ResultReg = 0;
10961060 }
11051069 const TargetInstrDesc &II = TII.get(MachineInstOpcode);
11061070
11071071 if (II.getNumDefs() >= 1)
1108 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
1072 BuildMI(MBB, DL, II, ResultReg)
11091073 .addReg(Op0, Op0IsKill * RegState::Kill)
11101074 .addFPImm(FPImm);
11111075 else {
1112 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
1076 BuildMI(MBB, DL, II)
11131077 .addReg(Op0, Op0IsKill * RegState::Kill)
11141078 .addFPImm(FPImm);
1115 bool InsertedCopy = TII.copyRegToReg(*FuncInfo.MBB, FuncInfo.InsertPt,
1116 ResultReg, II.ImplicitDefs[0],
1117 RC, RC, DL);
1079 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
1080 II.ImplicitDefs[0], RC, RC, DL);
11181081 if (!InsertedCopy)
11191082 ResultReg = 0;
11201083 }
11301093 const TargetInstrDesc &II = TII.get(MachineInstOpcode);
11311094
11321095 if (II.getNumDefs() >= 1)
1133 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
1096 BuildMI(MBB, DL, II, ResultReg)
11341097 .addReg(Op0, Op0IsKill * RegState::Kill)
11351098 .addReg(Op1, Op1IsKill * RegState::Kill)
11361099 .addImm(Imm);
11371100 else {
1138 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
1101 BuildMI(MBB, DL, II)
11391102 .addReg(Op0, Op0IsKill * RegState::Kill)
11401103 .addReg(Op1, Op1IsKill * RegState::Kill)
11411104 .addImm(Imm);
1142 bool InsertedCopy = TII.copyRegToReg(*FuncInfo.MBB, FuncInfo.InsertPt,
1143 ResultReg, II.ImplicitDefs[0],
1144 RC, RC, DL);
1105 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
1106 II.ImplicitDefs[0], RC, RC, DL);
11451107 if (!InsertedCopy)
11461108 ResultReg = 0;
11471109 }
11551117 const TargetInstrDesc &II = TII.get(MachineInstOpcode);
11561118
11571119 if (II.getNumDefs() >= 1)
1158 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg).addImm(Imm);
1120 BuildMI(MBB, DL, II, ResultReg).addImm(Imm);
11591121 else {
1160 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II).addImm(Imm);
1161 bool InsertedCopy = TII.copyRegToReg(*FuncInfo.MBB, FuncInfo.InsertPt,
1162 ResultReg, II.ImplicitDefs[0],
1163 RC, RC, DL);
1122 BuildMI(MBB, DL, II).addImm(Imm);
1123 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
1124 II.ImplicitDefs[0], RC, RC, DL);
11641125 if (!InsertedCopy)
11651126 ResultReg = 0;
11661127 }
11761137 const TargetInstrDesc &II = TII.get(TargetOpcode::EXTRACT_SUBREG);
11771138
11781139 if (II.getNumDefs() >= 1)
1179 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II, ResultReg)
1140 BuildMI(MBB, DL, II, ResultReg)
11801141 .addReg(Op0, Op0IsKill * RegState::Kill)
11811142 .addImm(Idx);
11821143 else {
1183 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II)
1144 BuildMI(MBB, DL, II)
11841145 .addReg(Op0, Op0IsKill * RegState::Kill)
11851146 .addImm(Idx);
1186 bool InsertedCopy = TII.copyRegToReg(*FuncInfo.MBB, FuncInfo.InsertPt,
1187 ResultReg, II.ImplicitDefs[0],
1188 RC, RC, DL);
1147 bool InsertedCopy = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
1148 II.ImplicitDefs[0], RC, RC, DL);
11891149 if (!InsertedCopy)
11901150 ResultReg = 0;
11911151 }
7777 MF = &mf;
7878 RegInfo = &MF->getRegInfo();
7979
80 // Check whether the function can return without sret-demotion.
81 SmallVector Outs;
82 GetReturnInfo(Fn->getReturnType(),
83 Fn->getAttributes().getRetAttributes(), Outs, TLI);
84 CanLowerReturn = TLI.CanLowerReturn(Fn->getCallingConv(), Fn->isVarArg(),
85 Outs, Fn->getContext());
86
8780 // Create a vreg for each argument register that is not dead and is used
8881 // outside of the entry block for the function.
8982 for (Function::const_arg_iterator AI = Fn->arg_begin(), E = Fn->arg_end();
731731 if (II.usesCustomInsertionHook()) {
732732 // Insert this instruction into the basic block using a target
733733 // specific inserter which may returns a new basic block.
734 MachineBasicBlock *NewMBB = TLI->EmitInstrWithCustomInserter(MI, MBB);
735 if (NewMBB != MBB) {
736 MBB = NewMBB;
737 InsertPos = NewMBB->end();
738 }
734 MBB = TLI->EmitInstrWithCustomInserter(MI, MBB);
735 InsertPos = MBB->end();
739736 return;
740737 }
741738
950950
951951 // If this is an instruction which fast-isel has deferred, select it now.
952952 if (const Instruction *Inst = dyn_cast(V)) {
953 unsigned InReg = FuncInfo.InitializeRegForValue(Inst);
954 RegsForValue RFV(*DAG.getContext(), TLI, InReg, Inst->getType());
955 SDValue Chain = DAG.getEntryNode();
956 return RFV.getCopyFromRegs(DAG, FuncInfo, getCurDebugLoc(), Chain, NULL);
953 assert(Inst->isSafeToSpeculativelyExecute() &&
954 "Instruction with side effects deferred!");
955 visit(*Inst);
956 DenseMap::iterator NIt = NodeMap.find(Inst);
957 if (NIt != NodeMap.end() && NIt->second.getNode())
958 return NIt->second;
957959 }
958960
959961 llvm_unreachable("Can't get register for value!");
960962 return SDValue();
963 }
964
965 /// Get the EVTs and ArgFlags collections that represent the legalized return
966 /// type of the given function. This does not require a DAG or a return value,
967 /// and is suitable for use before any DAGs for the function are constructed.
968 static void getReturnInfo(const Type* ReturnType,
969 Attributes attr, SmallVectorImpl &OutVTs,
970 SmallVectorImpl &OutFlags,
971 const TargetLowering &TLI,
972 SmallVectorImpl *Offsets = 0) {
973 SmallVector ValueVTs;
974 ComputeValueVTs(TLI, ReturnType, ValueVTs);
975 unsigned NumValues = ValueVTs.size();
976 if (NumValues == 0) return;
977 unsigned Offset = 0;
978
979 for (unsigned j = 0, f = NumValues; j != f; ++j) {
980 EVT VT = ValueVTs[j];
981 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
982
983 if (attr & Attribute::SExt)
984 ExtendKind = ISD::SIGN_EXTEND;
985 else if (attr & Attribute::ZExt)
986 ExtendKind = ISD::ZERO_EXTEND;
987
988 // FIXME: C calling convention requires the return type to be promoted to
989 // at least 32-bit. But this is not necessary for non-C calling
990 // conventions. The frontend should mark functions whose return values
991 // require promoting with signext or zeroext attributes.
992 if (ExtendKind != ISD::ANY_EXTEND && VT.isInteger()) {
993 EVT MinVT = TLI.getRegisterType(ReturnType->getContext(), MVT::i32);
994 if (VT.bitsLT(MinVT))
995 VT = MinVT;
996 }
997
998 unsigned NumParts = TLI.getNumRegisters(ReturnType->getContext(), VT);
999 EVT PartVT = TLI.getRegisterType(ReturnType->getContext(), VT);
1000 unsigned PartSize = TLI.getTargetData()->getTypeAllocSize(
1001 PartVT.getTypeForEVT(ReturnType->getContext()));
1002
1003 // 'inreg' on function refers to return value
1004 ISD::ArgFlagsTy Flags = ISD::ArgFlagsTy();
1005 if (attr & Attribute::InReg)
1006 Flags.setInReg();
1007
1008 // Propagate extension type if any
1009 if (attr & Attribute::SExt)
1010 Flags.setSExt();
1011 else if (attr & Attribute::ZExt)
1012 Flags.setZExt();
1013
1014 for (unsigned i = 0; i < NumParts; ++i) {
1015 OutVTs.push_back(PartVT);
1016 OutFlags.push_back(Flags);
1017 if (Offsets)
1018 {
1019 Offsets->push_back(Offset);
1020 Offset += PartSize;
1021 }
1022 }
1023 }
9611024 }
9621025
9631026 void SelectionDAGBuilder::visitRet(const ReturnInst &I) {
12561319 }
12571320
12581321 void SelectionDAGBuilder::visitBr(const BranchInst &I) {
1259 MachineBasicBlock *BrMBB = FuncInfo.MBB;
1322 MachineBasicBlock *BrMBB = FuncInfo.MBBMap[I.getParent()];
12601323
12611324 // Update machine-CFG edges.
12621325 MachineBasicBlock *Succ0MBB = FuncInfo.MBBMap[I.getSuccessor(0)];
15821645 }
15831646
15841647 void SelectionDAGBuilder::visitInvoke(const InvokeInst &I) {
1585 MachineBasicBlock *InvokeMBB = FuncInfo.MBB;
1648 MachineBasicBlock *InvokeMBB = FuncInfo.MBBMap[I.getParent()];
15861649
15871650 // Retrieve successors.
15881651 MachineBasicBlock *Return = FuncInfo.MBBMap[I.getSuccessor(0)];
21102173 }
21112174
21122175 void SelectionDAGBuilder::visitSwitch(const SwitchInst &SI) {
2113 MachineBasicBlock *SwitchMBB = FuncInfo.MBB;
2176 MachineBasicBlock *SwitchMBB = FuncInfo.MBBMap[SI.getParent()];
21142177
21152178 // Figure out which block is immediately after the current one.
21162179 MachineBasicBlock *NextBlock = 0;
21762239 }
21772240
21782241 void SelectionDAGBuilder::visitIndirectBr(const IndirectBrInst &I) {
2179 MachineBasicBlock *IndirectBrMBB = FuncInfo.MBB;
2242 MachineBasicBlock *IndirectBrMBB = FuncInfo.MBBMap[I.getParent()];
21802243
21812244 // Update machine-CFG edges with unique successors.
21822245 SmallVector succs;
38363899 if (DV.isInlinedFnArgument(MF.getFunction()))
38373900 return false;
38383901
3839 MachineBasicBlock *MBB = FuncInfo.MBB;
3902 MachineBasicBlock *MBB = FuncInfo.MBBMap[DI.getParent()];
38403903 if (MBB != &MF.front())
38413904 return false;
38423905
40994162 }
41004163 case Intrinsic::eh_exception: {
41014164 // Insert the EXCEPTIONADDR instruction.
4102 assert(FuncInfo.MBB->isLandingPad() &&
4165 assert(FuncInfo.MBBMap[I.getParent()]->isLandingPad() &&
41034166 "Call to eh.exception not in landing pad!");
41044167 SDVTList VTs = DAG.getVTList(TLI.getPointerTy(), MVT::Other);
41054168 SDValue Ops[1];
41114174 }
41124175
41134176 case Intrinsic::eh_selector: {
4114 MachineBasicBlock *CallMBB = FuncInfo.MBB;
4177 MachineBasicBlock *CallMBB = FuncInfo.MBBMap[I.getParent()];
41154178 MachineModuleInfo &MMI = DAG.getMachineFunction().getMMI();
41164179 if (CallMBB->isLandingPad())
41174180 AddCatchInfo(I, &MMI, CallMBB);
41214184 #endif
41224185 // FIXME: Mark exception selector register as live in. Hack for PR1508.
41234186 unsigned Reg = TLI.getExceptionSelectorRegister();
4124 if (Reg) FuncInfo.MBB->addLiveIn(Reg);
4187 if (Reg) FuncInfo.MBBMap[I.getParent()]->addLiveIn(Reg);
41254188 }
41264189
41274190 // Insert the EHSELECTION instruction.
44954558 Args.reserve(CS.arg_size());
44964559
44974560 // Check whether the function can return without sret-demotion.
4498 SmallVector<ISD::OutputArg, 4> Outs;
4561 SmallVector<EVT, 4> OutVTs;
4562 SmallVector OutsFlags;
44994563 SmallVector Offsets;
4500 GetReturnInfo(RetTy, CS.getAttributes().getRetAttributes(),
4501 Outs, TLI, &Offsets);
4564 getReturnInfo(RetTy, CS.getAttributes().getRetAttributes(),
4565 OutVTs, OutsFlags, TLI, &Offsets);
45024566
45034567 bool CanLowerReturn = TLI.CanLowerReturn(CS.getCallingConv(),
4504 FTy->isVarArg(), Outs, FTy->getContext());
4568 FTy->isVarArg(), OutVTs, OutsFlags, FTy->getContext());
45054569
45064570 SDValue DemoteStackSlot;
45074571
45944658 ComputeValueVTs(TLI, PtrRetTy, PVTs);
45954659 assert(PVTs.size() == 1 && "Pointers should fit in one register");
45964660 EVT PtrVT = PVTs[0];
4597 unsigned NumValues = Outs.size();
4661 unsigned NumValues = OutVTs.size();
45984662 SmallVector Values(NumValues);
45994663 SmallVector Chains(NumValues);
46004664
46024666 SDValue Add = DAG.getNode(ISD::ADD, getCurDebugLoc(), PtrVT,
46034667 DemoteStackSlot,
46044668 DAG.getConstant(Offsets[i], PtrVT));
4605 SDValue L = DAG.getLoad(Outs[i].VT, getCurDebugLoc(), Result.second,
4669 SDValue L = DAG.getLoad(OutVTs[i], getCurDebugLoc(), Result.second,
46064670 Add, NULL, Offsets[i], false, false, 1);
46074671 Values[i] = L;
46084672 Chains[i] = L.getValue(1);
58945958 SmallVector Ins;
58955959
58965960 // Check whether the function can return without sret-demotion.
5897 SmallVector Outs;
5898 GetReturnInfo(F.getReturnType(), F.getAttributes().getRetAttributes(),
5899 Outs, TLI);
5900
5961 SmallVector OutVTs;
5962 SmallVector OutsFlags;
5963 getReturnInfo(F.getReturnType(), F.getAttributes().getRetAttributes(),
5964 OutVTs, OutsFlags, TLI);
5965
5966 FuncInfo->CanLowerReturn = TLI.CanLowerReturn(F.getCallingConv(),
5967 F.isVarArg(),
5968 OutVTs, OutsFlags,
5969 F.getContext());
59015970 if (!FuncInfo->CanLowerReturn) {
59025971 // Put in an sret pointer parameter before all the other parameters.
59035972 SmallVector ValueVTs;
318318 return true;
319319 }
320320
321 void
322 SelectionDAGISel::SelectBasicBlock(BasicBlock::const_iterator Begin,
321 MachineBasicBlock *
322 SelectionDAGISel::SelectBasicBlock(MachineBasicBlock *BB,
323 BasicBlock::const_iterator Begin,
323324 BasicBlock::const_iterator End,
324325 bool &HadTailCall) {
325326 // Lower all of the non-terminator instructions. If a call is emitted
334335 SDB->clear();
335336
336337 // Final step, emit the lowered DAG as machine code.
337 CodeGenAndEmitDAG();
338 return CodeGenAndEmitDAG(BB);
338339 }
339340
340341 namespace {
423424 } while (!Worklist.empty());
424425 }
425426
426 void SelectionDAGISel::CodeGenAndEmitDAG() {
427 MachineBasicBlock *SelectionDAGISel::CodeGenAndEmitDAG(MachineBasicBlock *BB) {
427428 std::string GroupName;
428429 if (TimePassesIsEnabled)
429430 GroupName = "Instruction Selection and Scheduling";
432433 ViewDAGCombine2 || ViewDAGCombineLT || ViewISelDAGs || ViewSchedDAGs ||
433434 ViewSUnitDAGs)
434435 BlockName = MF->getFunction()->getNameStr() + ":" +
435 FuncInfo->MBB->getBasicBlock()->getNameStr();
436 BB->getBasicBlock()->getNameStr();
436437
437438 DEBUG(dbgs() << "Initial selection DAG:\n"; CurDAG->dump());
438439
539540 {
540541 NamedRegionTimer T("Instruction Scheduling", GroupName,
541542 TimePassesIsEnabled);
542 Scheduler->Run(CurDAG, FuncInfo->MBB, FuncInfo->InsertPt);
543 Scheduler->Run(CurDAG, BB, BB->end());
543544 }
544545
545546 if (ViewSUnitDAGs) Scheduler->viewGraph();
548549 // inserted into.
549550 {
550551 NamedRegionTimer T("Instruction Creation", GroupName, TimePassesIsEnabled);
551 FuncInfo->MBB = Scheduler->EmitSchedule();
552 FuncInfo->InsertPt = Scheduler->InsertPos;
552 BB = Scheduler->EmitSchedule();
553553 }
554554
555555 // Free the scheduler state.
561561
562562 // Free the SelectionDAG state, now that we're finished with it.
563563 CurDAG->clear();
564
565 return BB;
564566 }
565567
566568 void SelectionDAGISel::DoInstructionSelection() {
622624
623625 /// PrepareEHLandingPad - Emit an EH_LABEL, set up live-in registers, and
624626 /// do other setup for EH landing-pad blocks.
625 void SelectionDAGISel::PrepareEHLandingPad() {
627 void SelectionDAGISel::PrepareEHLandingPad(MachineBasicBlock *BB) {
626628 // Add a label to mark the beginning of the landing pad. Deletion of the
627629 // landing pad can thus be detected via the MachineModuleInfo.
628 MCSymbol *Label = MF->getMMI().addLandingPad(FuncInfo->MBB);
630 MCSymbol *Label = MF->getMMI().addLandingPad(BB);
629631
630632 const TargetInstrDesc &II = TM.getInstrInfo()->get(TargetOpcode::EH_LABEL);
631 BuildMI(*FuncInfo->MBB, FuncInfo->InsertPt, SDB->getCurDebugLoc(), II)
632 .addSym(Label);
633 BuildMI(BB, SDB->getCurDebugLoc(), II).addSym(Label);
633634
634635 // Mark exception register as live in.
635636 unsigned Reg = TLI.getExceptionAddressRegister();
636 if (Reg) FuncInfo->MBB->addLiveIn(Reg);
637 if (Reg) BB->addLiveIn(Reg);
637638
638639 // Mark exception selector register as live in.
639640 Reg = TLI.getExceptionSelectorRegister();
640 if (Reg) FuncInfo->MBB->addLiveIn(Reg);
641 if (Reg) BB->addLiveIn(Reg);
641642
642643 // FIXME: Hack around an exception handling flaw (PR1508): the personality
643644 // function and list of typeids logically belong to the invoke (or, if you
650651 // in exceptions not being caught because no typeids are associated with
651652 // the invoke. This may not be the only way things can go wrong, but it
652653 // is the only way we try to work around for the moment.
653 const BasicBlock *LLVMBB = FuncInfo->MBB->getBasicBlock();
654 const BasicBlock *LLVMBB = BB->getBasicBlock();
654655 const BranchInst *Br = dyn_cast(LLVMBB->getTerminator());
655656
656657 if (Br && Br->isUnconditional()) { // Critical edge?
674675 // Iterate over all basic blocks in the function.
675676 for (Function::const_iterator I = Fn.begin(), E = Fn.end(); I != E; ++I) {
676677 const BasicBlock *LLVMBB = &*I;
677 FuncInfo->MBB = FuncInfo->MBBMap[LLVMBB];
678 FuncInfo->InsertPt = FuncInfo->MBB->getFirstNonPHI();
678 MachineBasicBlock *BB = FuncInfo->MBBMap[LLVMBB];
679679
680680 BasicBlock::const_iterator const Begin = LLVMBB->getFirstNonPHI();
681681 BasicBlock::const_iterator const End = LLVMBB->end();
682 BasicBlock::const_iterator BI = End;
683
682 BasicBlock::const_iterator BI = Begin;
683
684 // Lower any arguments needed in this block if this is the entry block.
685 if (LLVMBB == &Fn.getEntryBlock())
686 LowerArguments(LLVMBB);
687
688 // Setup an EH landing-pad block.
689 if (BB->isLandingPad())
690 PrepareEHLandingPad(BB);
691
684692 // Before doing SelectionDAG ISel, see if FastISel has been requested.
685693 if (FastIS) {
686 FastIS->startNewBlock();
687
694 // Emit code for any incoming arguments. This must happen before
695 // beginning FastISel on the entry block.
696 if (LLVMBB == &Fn.getEntryBlock()) {
697 CurDAG->setRoot(SDB->getControlRoot());
698 SDB->clear();
699 BB = CodeGenAndEmitDAG(BB);
700 }
701 FastIS->startNewBlock(BB);
688702 // Do FastISel on as many instructions as possible.
689 for (; BI != Begin; --BI) {
690 const Instruction *Inst = llvm::prior(BI);
691
692 // If we no longer require this instruction, skip it.
693 if (!Inst->mayWriteToMemory() &&
694 !isa(Inst) &&
695 !isa(Inst) &&
696 !FuncInfo->isExportedInst(Inst))
703 for (; BI != End; ++BI) {
704 #if 0
705 // Defer instructions with no side effects; they'll be emitted
706 // on-demand later.
707 if (BI->isSafeToSpeculativelyExecute() &&
708 !FuncInfo->isExportedInst(BI))
697709 continue;
698
699 // Bottom-up: reset the insert pos at the top, after any local-value
700 // instructions.
701 MachineBasicBlock::iterator LVIP = FastIS->getLastLocalValue();
702 if (LVIP != FuncInfo->MBB->end())
703 FuncInfo->InsertPt = next(LVIP);
704 else
705 FuncInfo->InsertPt = FuncInfo->MBB->getFirstNonPHI();
710 #endif
706711
707712 // Try to select the instruction with FastISel.
708 if (FastIS->SelectInstruction(Inst))
713 if (FastIS->SelectInstruction(BI))
709714 continue;
710715
711716 // Then handle certain instructions as single-LLVM-Instruction blocks.
712 if (isa(Inst)) {
717 if (isa(BI)) {
713718 ++NumFastIselFailures;
714719 if (EnableFastISelVerbose || EnableFastISelAbort) {
715720 dbgs() << "FastISel missed call: ";
716 Inst->dump();
721 BI->dump();
717722 }
718723
719 if (!Inst->getType()->isVoidTy() && !Inst->use_empty()) {
720 unsigned &R = FuncInfo->ValueMap[Inst];
724 if (!BI->getType()->isVoidTy() && !BI->use_empty()) {
725 unsigned &R = FuncInfo->ValueMap[BI];
721726 if (!R)
722 R = FuncInfo->CreateRegs(Inst->getType());
727 R = FuncInfo->CreateRegs(BI->getType());
723728 }
724729
725730 bool HadTailCall = false;
726 SelectBasicBlock(Inst, BI, HadTailCall);
731 BB = SelectBasicBlock(BB, BI, llvm::next(BI), HadTailCall);
727732
728733 // If the call was emitted as a tail call, we're done with the block.
729734 if (HadTailCall) {
730 --BI;
735 BI = End;
731736 break;
732737 }
733738
739 // If the instruction was codegen'd with multiple blocks,
740 // inform the FastISel object where to resume inserting.
741 FastIS->setCurrentBlock(BB);
734742 continue;
735743 }
736744
737745 // Otherwise, give up on FastISel for the rest of the block.
738746 // For now, be a little lenient about non-branch terminators.
739 if (!isa(Inst) || isa(Inst)) {
747 if (!isa(BI) || isa(BI)) {
740748 ++NumFastIselFailures;
741749 if (EnableFastISelVerbose || EnableFastISelAbort) {
742750 dbgs() << "FastISel miss: ";
743 Inst->dump();
751 BI->dump();
744752 }
745753 if (EnableFastISelAbort)
746754 // The "fast" selector couldn't handle something and bailed.
751759 }
752760 }
753761
754 FuncInfo->InsertPt = FuncInfo->MBB->getFirstNonPHI();
755
756 // Setup an EH landing-pad block.
757 if (FuncInfo->MBB->isLandingPad())
758 PrepareEHLandingPad();
759
760 // Lower any arguments needed in this block if this is the entry block.
761 if (LLVMBB == &Fn.getEntryBlock())
762 LowerArguments(LLVMBB);
763
764762 // Run SelectionDAG instruction selection on the remainder of the block
765763 // not handled by FastISel. If FastISel is not run, this is the entire
766764 // block.
767 bool HadTailCall;
768 SelectBasicBlock(Begin, BI, HadTailCall);
769
770 FinishBasicBlock();
765 if (BI != End) {
766 bool HadTailCall;
767 BB = SelectBasicBlock(BB, BI, End, HadTailCall);
768 }
769
770 FinishBasicBlock(BB);
771771 FuncInfo->PHINodesToUpdate.clear();
772772 }
773773
775775 }
776776
777777 void
778 SelectionDAGISel::FinishBasicBlock() {
778 SelectionDAGISel::FinishBasicBlock(MachineBasicBlock *BB) {
779779
780780 DEBUG(dbgs() << "Total amount of phi nodes to update: "
781781 << FuncInfo->PHINodesToUpdate.size() << "\n";
793793 MachineInstr *PHI = FuncInfo->PHINodesToUpdate[i].first;
794794 assert(PHI->isPHI() &&
795795 "This is not a machine PHI node that we are updating!");
796 if (!FuncInfo->MBB->isSuccessor(PHI->getParent()))
796 if (!BB->isSuccessor(PHI->getParent()))
797797 continue;
798798 PHI->addOperand(
799799 MachineOperand::CreateReg(FuncInfo->PHINodesToUpdate[i].second, false));
800 PHI->addOperand(MachineOperand::CreateMBB(FuncInfo->MBB));
800 PHI->addOperand(MachineOperand::CreateMBB(BB));
801801 }
802802 return;
803803 }
806806 // Lower header first, if it wasn't already lowered
807807 if (!SDB->BitTestCases[i].Emitted) {
808808 // Set the current basic block to the mbb we wish to insert the code into
809 FuncInfo->MBB = SDB->BitTestCases[i].Parent;
810 FuncInfo->InsertPt = FuncInfo->MBB->end();
809 BB = SDB->BitTestCases[i].Parent;
811810 // Emit the code
812 SDB->visitBitTestHeader(SDB->BitTestCases[i], FuncInfo->MBB);
811 SDB->visitBitTestHeader(SDB->BitTestCases[i], BB);
813812 CurDAG->setRoot(SDB->getRoot());
814813 SDB->clear();
815 CodeGenAndEmitDAG();
814 BB = CodeGenAndEmitDAG(BB);
816815 }
817816
818817 for (unsigned j = 0, ej = SDB->BitTestCases[i].Cases.size(); j != ej; ++j) {
819818 // Set the current basic block to the mbb we wish to insert the code into
820 FuncInfo->MBB = SDB->BitTestCases[i].Cases[j].ThisBB;
821 FuncInfo->InsertPt = FuncInfo->MBB->end();
819 BB = SDB->BitTestCases[i].Cases[j].ThisBB;
822820 // Emit the code
823821 if (j+1 != ej)
824822 SDB->visitBitTestCase(SDB->BitTestCases[i].Cases[j+1].ThisBB,
825823 SDB->BitTestCases[i].Reg,
826824 SDB->BitTestCases[i].Cases[j],
827 FuncInfo->MBB);
825 BB);
828826 else
829827 SDB->visitBitTestCase(SDB->BitTestCases[i].Default,
830828 SDB->BitTestCases[i].Reg,
831829 SDB->BitTestCases[i].Cases[j],
832 FuncInfo->MBB);
830 BB);
833831
834832
835833 CurDAG->setRoot(SDB->getRoot());
836834 SDB->clear();
837 CodeGenAndEmitDAG();
835 BB = CodeGenAndEmitDAG(BB);
838836 }
839837
840838 // Update PHI Nodes
879877 // Lower header first, if it wasn't already lowered
880878 if (!SDB->JTCases[i].first.Emitted) {
881879 // Set the current basic block to the mbb we wish to insert the code into
882 FuncInfo->MBB = SDB->JTCases[i].first.HeaderBB;
883 FuncInfo->InsertPt = FuncInfo->MBB->end();
880 BB = SDB->JTCases[i].first.HeaderBB;
884881 // Emit the code
885882 SDB->visitJumpTableHeader(SDB->JTCases[i].second, SDB->JTCases[i].first,
886 FuncInfo->MBB);
883 BB);
887884 CurDAG->setRoot(SDB->getRoot());
888885 SDB->clear();
889 CodeGenAndEmitDAG();
886 BB = CodeGenAndEmitDAG(BB);
890887 }
891888
892889 // Set the current basic block to the mbb we wish to insert the code into
893 FuncInfo->MBB = SDB->JTCases[i].second.MBB;
894 FuncInfo->InsertPt = FuncInfo->MBB->end();
890 BB = SDB->JTCases[i].second.MBB;
895891 // Emit the code
896892 SDB->visitJumpTable(SDB->JTCases[i].second);
897893 CurDAG->setRoot(SDB->getRoot());
898894 SDB->clear();
899 CodeGenAndEmitDAG();
895 BB = CodeGenAndEmitDAG(BB);
900896
901897 // Update PHI Nodes
902898 for (unsigned pi = 0, pe = FuncInfo->PHINodesToUpdate.size();
914910 (MachineOperand::CreateMBB(SDB->JTCases[i].first.HeaderBB));
915911 }
916912 // JT BB. Just iterate over successors here
917 if (FuncInfo->MBB->isSuccessor(PHIBB)) {
913 if (BB->isSuccessor(PHIBB)) {
918914 PHI->addOperand
919915 (MachineOperand::CreateReg(FuncInfo->PHINodesToUpdate[pi].second,
920916 false));
921 PHI->addOperand(MachineOperand::CreateMBB(FuncInfo->MBB));
917 PHI->addOperand(MachineOperand::CreateMBB(BB));
922918 }
923919 }
924920 }
930926 MachineInstr *PHI = FuncInfo->PHINodesToUpdate[i].first;
931927 assert(PHI->isPHI() &&
932928 "This is not a machine PHI node that we are updating!");
933 if (FuncInfo->MBB->isSuccessor(PHI->getParent())) {
929 if (BB->isSuccessor(PHI->getParent())) {
934930 PHI->addOperand(
935931 MachineOperand::CreateReg(FuncInfo->PHINodesToUpdate[i].second, false));
936 PHI->addOperand(MachineOperand::CreateMBB(FuncInfo->MBB));
932 PHI->addOperand(MachineOperand::CreateMBB(BB));
937933 }
938934 }
939935
941937 // additional DAGs necessary.
942938 for (unsigned i = 0, e = SDB->SwitchCases.size(); i != e; ++i) {
943939 // Set the current basic block to the mbb we wish to insert the code into
944 MachineBasicBlock *ThisBB = FuncInfo->MBB = SDB->SwitchCases[i].ThisBB;
945 FuncInfo->InsertPt = FuncInfo->MBB->end();
940 MachineBasicBlock *ThisBB = BB = SDB->SwitchCases[i].ThisBB;
946941
947942 // Determine the unique successors.
948943 SmallVector Succs;
952947
953948 // Emit the code. Note that this could result in ThisBB being split, so
954949 // we need to check for updates.
955 SDB->visitSwitchCase(SDB->SwitchCases[i], FuncInfo->MBB);
950 SDB->visitSwitchCase(SDB->SwitchCases[i], BB);
956951 CurDAG->setRoot(SDB->getRoot());
957952 SDB->clear();
958 CodeGenAndEmitDAG();
959 ThisBB = FuncInfo->MBB;
953 ThisBB = CodeGenAndEmitDAG(BB);
960954
961955 // Handle any PHI nodes in successors of this chunk, as if we were coming
962956 // from the original BB before switch expansion. Note that PHI nodes can
963957 // occur multiple times in PHINodesToUpdate. We have to be very careful to
964958 // handle them the right number of times.
965959 for (unsigned i = 0, e = Succs.size(); i != e; ++i) {
966 FuncInfo->MBB = Succs[i];
967 FuncInfo->InsertPt = FuncInfo->MBB->end();
968 // FuncInfo->MBB may have been removed from the CFG if a branch was
969 // constant folded.
970 if (ThisBB->isSuccessor(FuncInfo->MBB)) {
971 for (MachineBasicBlock::iterator Phi = FuncInfo->MBB->begin();
972 Phi != FuncInfo->MBB->end() && Phi->isPHI();
960 BB = Succs[i];
961 // BB may have been removed from the CFG if a branch was constant folded.
962 if (ThisBB->isSuccessor(BB)) {
963 for (MachineBasicBlock::iterator Phi = BB->begin();
964 Phi != BB->end() && Phi->isPHI();
973965 ++Phi) {
974966 // This value for this PHI node is recorded in PHINodesToUpdate.
975967 for (unsigned pn = 0; ; ++pn) {
1919 #include "llvm/Target/TargetRegisterInfo.h"
2020 #include "llvm/GlobalVariable.h"
2121 #include "llvm/DerivedTypes.h"
22 #include "llvm/CodeGen/Analysis.h"
2322 #include "llvm/CodeGen/MachineFrameInfo.h"
2423 #include "llvm/CodeGen/MachineJumpTableInfo.h"
2524 #include "llvm/CodeGen/MachineFunction.h"
838837 return 1;
839838 }
840839
841 /// Get the EVTs and ArgFlags collections that represent the legalized return
842 /// type of the given function. This does not require a DAG or a return value,
843 /// and is suitable for use before any DAGs for the function are constructed.
844 /// TODO: Move this out of TargetLowering.cpp.
845 void llvm::GetReturnInfo(const Type* ReturnType, Attributes attr,
846 SmallVectorImpl &Outs,
847 const TargetLowering &TLI,
848 SmallVectorImpl *Offsets) {
849 SmallVector ValueVTs;
850 ComputeValueVTs(TLI, ReturnType, ValueVTs);
851 unsigned NumValues = ValueVTs.size();
852 if (NumValues == 0) return;
853 unsigned Offset = 0;
854
855 for (unsigned j = 0, f = NumValues; j != f; ++j) {
856 EVT VT = ValueVTs[j];
857 ISD::NodeType ExtendKind = ISD::ANY_EXTEND;
858
859 if (attr & Attribute::SExt)
860 ExtendKind = ISD::SIGN_EXTEND;
861 else if (attr & Attribute::ZExt)
862 ExtendKind = ISD::ZERO_EXTEND;
863
864 // FIXME: C calling convention requires the return type to be promoted to
865 // at least 32-bit. But this is not necessary for non-C calling
866 // conventions. The frontend should mark functions whose return values
867 // require promoting with signext or zeroext attributes.
868 if (ExtendKind != ISD::ANY_EXTEND && VT.isInteger()) {
869 EVT MinVT = TLI.getRegisterType(ReturnType->getContext(), MVT::i32);
870 if (VT.bitsLT(MinVT))
871 VT = MinVT;
872 }
873
874 unsigned NumParts = TLI.getNumRegisters(ReturnType->getContext(), VT);
875 EVT PartVT = TLI.getRegisterType(ReturnType->getContext(), VT);
876 unsigned PartSize = TLI.getTargetData()->getTypeAllocSize(
877 PartVT.getTypeForEVT(ReturnType->getContext()));
878
879 // 'inreg' on function refers to return value
880 ISD::ArgFlagsTy Flags = ISD::ArgFlagsTy();
881 if (attr & Attribute::InReg)
882 Flags.setInReg();
883
884 // Propagate extension type if any
885 if (attr & Attribute::SExt)
886 Flags.setSExt();
887 else if (attr & Attribute::ZExt)
888 Flags.setZExt();
889
890 for (unsigned i = 0; i < NumParts; ++i) {
891 Outs.push_back(ISD::OutputArg(Flags, PartVT, /*isFixed=*/true));
892 if (Offsets) {
893 Offsets->push_back(Offset);
894 Offset += PartSize;
895 }
896 }
897 }
898 }
899
900840 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
901841 /// function arguments in the caller parameter area. This is the actual
902842 /// alignment, not its logarithm.
2222 #include "llvm/GlobalVariable.h"
2323 #include "llvm/Instructions.h"
2424 #include "llvm/IntrinsicInst.h"
25 #include "llvm/CodeGen/Analysis.h"
2625 #include "llvm/CodeGen/FastISel.h"
2726 #include "llvm/CodeGen/FunctionLoweringInfo.h"
2827 #include "llvm/CodeGen/MachineConstantPool.h"
8483
8584 bool X86SelectStore(const Instruction *I);
8685
87 bool X86SelectRet(const Instruction *I);
88
8986 bool X86SelectCmp(const Instruction *I);
9087
9188 bool X86SelectZExt(const Instruction *I);
107104 bool X86SelectCall(const Instruction *I);
108105
109106 CCAssignFn *CCAssignFnForCall(CallingConv::ID CC, bool isTailCall = false);
110 CCAssignFn *CCAssignFnForRet(CallingConv::ID CC, bool isTailCall = false);
111107
112108 const X86InstrInfo *getInstrInfo() const {
113109 return getTargetMachine()->getInstrInfo();
179175 return CC_X86_32_GHC;
180176 else
181177 return CC_X86_32_C;
182 }
183
184 /// CCAssignFnForRet - Selects the correct CCAssignFn for a given calling
185 /// convention.
186 CCAssignFn *X86FastISel::CCAssignFnForRet(CallingConv::ID CC,
187 bool isTaillCall) {
188 if (Subtarget->is64Bit()) {
189 if (Subtarget->isTargetWin64())
190 return RetCC_X86_Win64_C;
191 else
192 return RetCC_X86_64_C;
193 }
194
195 return RetCC_X86_32_C;
196178 }
197179
198180 /// X86FastEmitLoad - Emit a machine instruction to load a value of type VT.
247229 }
248230
249231 ResultReg = createResultReg(RC);
250 addFullAddress(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt,
251 DL, TII.get(Opc), ResultReg), AM);
232 addFullAddress(BuildMI(MBB, DL, TII.get(Opc), ResultReg), AM);
252233 return true;
253234 }
254235
267248 case MVT::i1: {
268249 // Mask out all but lowest bit.
269250 unsigned AndResult = createResultReg(X86::GR8RegisterClass);
270 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
251 BuildMI(MBB, DL,
271252 TII.get(X86::AND8ri), AndResult).addReg(Val).addImm(1);
272253 Val = AndResult;
273254 }
284265 break;
285266 }
286267
287 addFullAddress(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt,
288 DL, TII.get(Opc)), AM).addReg(Val);
268 addFullAddress(BuildMI(MBB, DL, TII.get(Opc)), AM).addReg(Val);
289269 return true;
290270 }
291271
313293 }
314294
315295 if (Opc) {
316 addFullAddress(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt,
317 DL, TII.get(Opc)), AM)
296 addFullAddress(BuildMI(MBB, DL, TII.get(Opc)), AM)
318297 .addImm(Signed ? (uint64_t) CI->getSExtValue() :
319298 CI->getZExtValue());
320299 return true;
353332 // Don't walk into other basic blocks; it's possible we haven't
354333 // visited them yet, so the instructions may not yet be assigned
355334 // virtual registers.
356 if (FuncInfo.MBBMap[I->getParent()] != FuncInfo.MBB)
335 if (FuncInfo.MBBMap[I->getParent()] != MBB)
357336 return false;
358337
359338 Opcode = I->getOpcode();
550529 }
551530
552531 LoadReg = createResultReg(RC);
553 addFullAddress(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt,
554 DL, TII.get(Opc), LoadReg), StubAM);
532 addFullAddress(BuildMI(MBB, DL, TII.get(Opc), LoadReg), StubAM);
555533
556534 // Prevent loading GV stub multiple times in same MBB.
557535 LocalValueMap[V] = LoadReg;
675653 return false;
676654
677655 return X86FastEmitStore(VT, I->getOperand(0), AM);
678 }
679
680 /// X86SelectRet - Select and emit code to implement ret instructions.
681 bool X86FastISel::X86SelectRet(const Instruction *I) {
682 const ReturnInst *Ret = cast(I);
683 const Function &F = *I->getParent()->getParent();
684
685 if (!FuncInfo.CanLowerReturn)
686 return false;
687
688 CallingConv::ID CC = F.getCallingConv();
689 if (CC != CallingConv::C &&
690 CC != CallingConv::Fast &&
691 CC != CallingConv::X86_FastCall)
692 return false;
693
694 if (Subtarget->isTargetWin64())
695 return false;
696
697 // fastcc with -tailcallopt is intended to provide a guaranteed
698 // tail call optimization. Fastisel doesn't know how to do that.
699 if (CC == CallingConv::Fast && GuaranteedTailCallOpt)
700 return false;
701
702 // Let SDISel handle vararg functions.
703 if (F.isVarArg())
704 return false;
705
706 if (Ret->getNumOperands() > 0) {
707 SmallVector Outs;
708 GetReturnInfo(F.getReturnType(), F.getAttributes().getRetAttributes(),
709 Outs, TLI);
710
711 // Analyze operands of the call, assigning locations to each operand.
712 SmallVector ValLocs;
713 CCState CCInfo(CC, F.isVarArg(), TM, ValLocs, I->getContext());
714 CCInfo.AnalyzeReturn(Outs, CCAssignFnForRet(CC));
715
716 const Value *RV = Ret->getOperand(0);
717 unsigned Reg = getRegForValue(RV);
718 if (Reg == 0)
719 return false;
720
721 // Copy the return value into registers.
722 for (unsigned i = 0, e = ValLocs.size(); i != e; ++i) {
723 CCValAssign &VA = ValLocs[i];
724
725 // Don't bother handling odd stuff for now.
726 if (VA.getLocInfo() != CCValAssign::Full)
727 return false;
728 if (!VA.isRegLoc())
729 return false;
730
731 TargetRegisterClass* RC = TLI.getRegClassFor(VA.getValVT());
732 bool Emitted = TII.copyRegToReg(*FuncInfo.MBB, FuncInfo.InsertPt,
733 VA.getLocReg(), Reg + VA.getValNo(),
734 RC, RC, DL);
735 assert(Emitted && "Failed to emit a copy instruction!"); Emitted=Emitted;
736
737 MRI.addLiveOut(VA.getLocReg());
738 }
739 }
740
741 // Now emit the RET.
742 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(X86::RET));
743 return true;
744656 }
745657
746658 /// X86SelectLoad - Select and emit code to implement load instructions.
807719 // CMPri, otherwise use CMPrr.
808720 if (const ConstantInt *Op1C = dyn_cast(Op1)) {
809721 if (unsigned CompareImmOpc = X86ChooseCmpImmediateOpcode(VT, Op1C)) {
810 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(CompareImmOpc))
811 .addReg(Op0Reg)
812 .addImm(Op1C->getSExtValue());
722 BuildMI(MBB, DL, TII.get(CompareImmOpc)).addReg(Op0Reg)
723 .addImm(Op1C->getSExtValue());
813724 return true;
814725 }
815726 }
819730
820731 unsigned Op1Reg = getRegForValue(Op1);
821732 if (Op1Reg == 0) return false;
822 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(CompareOpc))
823 .addReg(Op0Reg)
824 .addReg(Op1Reg);
733 BuildMI(MBB, DL, TII.get(CompareOpc)).addReg(Op0Reg).addReg(Op1Reg);
825734
826735 return true;
827736 }
843752
844753 unsigned EReg = createResultReg(&X86::GR8RegClass);
845754 unsigned NPReg = createResultReg(&X86::GR8RegClass);
846 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(X86::SETEr), EReg);
847 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
848 TII.get(X86::SETNPr), NPReg);
849 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
755 BuildMI(MBB, DL, TII.get(X86::SETEr), EReg);
756 BuildMI(MBB, DL, TII.get(X86::SETNPr), NPReg);
757 BuildMI(MBB, DL,
850758 TII.get(X86::AND8rr), ResultReg).addReg(NPReg).addReg(EReg);
851759 UpdateValueMap(I, ResultReg);
852760 return true;
857765
858766 unsigned NEReg = createResultReg(&X86::GR8RegClass);
859767 unsigned PReg = createResultReg(&X86::GR8RegClass);
860 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
861 TII.get(X86::SETNEr), NEReg);
862 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
863 TII.get(X86::SETPr), PReg);
864 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
865 TII.get(X86::OR8rr), ResultReg)
866 .addReg(PReg).addReg(NEReg);
768 BuildMI(MBB, DL, TII.get(X86::SETNEr), NEReg);
769 BuildMI(MBB, DL, TII.get(X86::SETPr), PReg);
770 BuildMI(MBB, DL, TII.get(X86::OR8rr), ResultReg).addReg(PReg).addReg(NEReg);
867771 UpdateValueMap(I, ResultReg);
868772 return true;
869773 }
902806 if (!X86FastEmitCompare(Op0, Op1, VT))
903807 return false;
904808
905 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(SetCCOpc), ResultReg);
809 BuildMI(MBB, DL, TII.get(SetCCOpc), ResultReg);
906810 UpdateValueMap(I, ResultReg);
907811 return true;
908812 }
938842
939843 // Try to take advantage of fallthrough opportunities.
940844 CmpInst::Predicate Predicate = CI->getPredicate();
941 if (FuncInfo.MBB->isLayoutSuccessor(TrueMBB)) {
845 if (MBB->isLayoutSuccessor(TrueMBB)) {
942846 std::swap(TrueMBB, FalseMBB);
943847 Predicate = CmpInst::getInversePredicate(Predicate);
944848 }
987891 if (!X86FastEmitCompare(Op0, Op1, VT))
988892 return false;
989893
990 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(BranchOpc))
991 .addMBB(TrueMBB);
894 BuildMI(MBB, DL, TII.get(BranchOpc)).addMBB(TrueMBB);
992895
993896 if (Predicate == CmpInst::FCMP_UNE) {
994897 // X86 requires a second branch to handle UNE (and OEQ,
995898 // which is mapped to UNE above).
996 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(X86::JP_4))
997 .addMBB(TrueMBB);
899 BuildMI(MBB, DL, TII.get(X86::JP_4)).addMBB(TrueMBB);
998900 }
999901
1000902 FastEmitBranch(FalseMBB, DL);
1001 FuncInfo.MBB->addSuccessor(TrueMBB);
903 MBB->addSuccessor(TrueMBB);
1002904 return true;
1003905 }
1004906 } else if (ExtractValueInst *EI =
1024926 unsigned Reg = getRegForValue(EI);
1025927
1026928 for (MachineBasicBlock::const_reverse_iterator
1027 RI = FuncInfo.MBB->rbegin(), RE = FuncInfo.MBB->rend();
1028 RI != RE; ++RI) {
929 RI = MBB->rbegin(), RE = MBB->rend(); RI != RE; ++RI) {
1029930 const MachineInstr &MI = *RI;
1030931
1031932 if (MI.definesRegister(Reg)) {
1050951 unsigned OpCode = SetMI->getOpcode();
1051952
1052953 if (OpCode == X86::SETOr || OpCode == X86::SETBr) {
1053 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1054 TII.get(OpCode == X86::SETOr ? X86::JO_4 : X86::JB_4))
954 BuildMI(MBB, DL, TII.get(OpCode == X86::SETOr ?
955 X86::JO_4 : X86::JB_4))
1055956 .addMBB(TrueMBB);
1056957 FastEmitBranch(FalseMBB, DL);
1057 FuncInfo.MBB->addSuccessor(TrueMBB);
958 MBB->addSuccessor(TrueMBB);
1058959 return true;
1059960 }
1060961 }
1066967 unsigned OpReg = getRegForValue(BI->getCondition());
1067968 if (OpReg == 0) return false;
1068969
1069 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(X86::TEST8rr))
1070 .addReg(OpReg).addReg(OpReg);
1071 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(X86::JNE_4))
1072 .addMBB(TrueMBB);
970 BuildMI(MBB, DL, TII.get(X86::TEST8rr)).addReg(OpReg).addReg(OpReg);
971 BuildMI(MBB, DL, TII.get(X86::JNE_4)).addMBB(TrueMBB);
1073972 FastEmitBranch(FalseMBB, DL);
1074 FuncInfo.MBB->addSuccessor(TrueMBB);
973 MBB->addSuccessor(TrueMBB);
1075974 return true;
1076975 }
1077976
11281027 // Fold immediate in shl(x,3).
11291028 if (const ConstantInt *CI = dyn_cast(I->getOperand(1))) {
11301029 unsigned ResultReg = createResultReg(RC);
1131 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(OpImm),
1030 BuildMI(MBB, DL, TII.get(OpImm),
11321031 ResultReg).addReg(Op0Reg).addImm(CI->getZExtValue() & 0xff);
11331032 UpdateValueMap(I, ResultReg);
11341033 return true;
11361035
11371036 unsigned Op1Reg = getRegForValue(I->getOperand(1));
11381037 if (Op1Reg == 0) return false;
1139 TII.copyRegToReg(*FuncInfo.MBB, FuncInfo.InsertPt,
1140 CReg, Op1Reg, RC, RC, DL);
1038 TII.copyRegToReg(*MBB, MBB->end(), CReg, Op1Reg, RC, RC, DL);
11411039
11421040 // The shift instruction uses X86::CL. If we defined a super-register
11431041 // of X86::CL, emit an EXTRACT_SUBREG to precisely describe what
11441042 // we're doing here.
11451043 if (CReg != X86::CL)
1146 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1147 TII.get(TargetOpcode::EXTRACT_SUBREG), X86::CL)
1044 BuildMI(MBB, DL, TII.get(TargetOpcode::EXTRACT_SUBREG), X86::CL)
11481045 .addReg(CReg).addImm(X86::sub_8bit);
11491046
11501047 unsigned ResultReg = createResultReg(RC);
1151 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(OpReg), ResultReg)
1152 .addReg(Op0Reg);
1048 BuildMI(MBB, DL, TII.get(OpReg), ResultReg).addReg(Op0Reg);
11531049 UpdateValueMap(I, ResultReg);
11541050 return true;
11551051 }
11811077 unsigned Op2Reg = getRegForValue(I->getOperand(2));
11821078 if (Op2Reg == 0) return false;
11831079
1184 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(X86::TEST8rr))
1185 .addReg(Op0Reg).addReg(Op0Reg);
1080 BuildMI(MBB, DL, TII.get(X86::TEST8rr)).addReg(Op0Reg).addReg(Op0Reg);
11861081 unsigned ResultReg = createResultReg(RC);
1187 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc), ResultReg)
1188 .addReg(Op1Reg).addReg(Op2Reg);
1082 BuildMI(MBB, DL, TII.get(Opc), ResultReg).addReg(Op1Reg).addReg(Op2Reg);
11891083 UpdateValueMap(I, ResultReg);
11901084 return true;
11911085 }
11991093 unsigned OpReg = getRegForValue(V);
12001094 if (OpReg == 0) return false;
12011095 unsigned ResultReg = createResultReg(X86::FR64RegisterClass);
1202 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1203 TII.get(X86::CVTSS2SDrr), ResultReg)
1204 .addReg(OpReg);
1096 BuildMI(MBB, DL, TII.get(X86::CVTSS2SDrr), ResultReg).addReg(OpReg);
12051097 UpdateValueMap(I, ResultReg);
12061098 return true;
12071099 }
12181110 unsigned OpReg = getRegForValue(V);
12191111 if (OpReg == 0) return false;
12201112 unsigned ResultReg = createResultReg(X86::FR32RegisterClass);
1221 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1222 TII.get(X86::CVTSD2SSrr), ResultReg)
1223 .addReg(OpReg);
1113 BuildMI(MBB, DL, TII.get(X86::CVTSD2SSrr), ResultReg).addReg(OpReg);
12241114 UpdateValueMap(I, ResultReg);
12251115 return true;
12261116 }
12551145 const TargetRegisterClass *CopyRC = (SrcVT == MVT::i16)
12561146 ? X86::GR16_ABCDRegisterClass : X86::GR32_ABCDRegisterClass;
12571147 unsigned CopyReg = createResultReg(CopyRC);
1258 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(CopyOpc), CopyReg)
1259 .addReg(InputReg);
1148 BuildMI(MBB, DL, TII.get(CopyOpc), CopyReg).addReg(InputReg);
12601149
12611150 // Then issue an extract_subreg.
12621151 unsigned ResultReg = FastEmitInst_extractsubreg(MVT::i8,
12771166 switch (CI->getIntrinsicID()) {
12781167 default: break;
12791168 case Intrinsic::sadd_with_overflow:
1280 case Intrinsic::uadd_with_overflow: {
1169 case Intrinsic::uadd_with_overflow:
12811170 // Cheat a little. We know that the registers for "add" and "seto" are
12821171 // allocated sequentially. However, we only keep track of the register
12831172 // for "add" in the value map. Use extractvalue's index to get the
12841173 // correct register for "seto".
1285 unsigned OpReg = getRegForValue(Agg);
1286 if (OpReg == 0)
1287 return false;
1288 UpdateValueMap(I, OpReg + *EI->idx_begin());
1174 UpdateValueMap(I, lookUpRegForValue(Agg) + *EI->idx_begin());
12891175 return true;
1290 }
12911176 }
12921177 }
12931178
13321217 return false;
13331218
13341219 unsigned ResultReg = createResultReg(TLI.getRegClassFor(VT));
1335 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(OpC), ResultReg).
1220 BuildMI(MBB, DL, TII.get(OpC), ResultReg).
13361221 addImm(CI->isZero() ? -1ULL : 0);
13371222 UpdateValueMap(&I, ResultReg);
13381223 return true;
13461231 const TargetInstrDesc &II = TII.get(TargetOpcode::DBG_VALUE);
13471232 // FIXME may need to add RegState::Debug to any registers produced,
13481233 // although ESP/EBP should be the only ones at the moment.
1349 addFullAddress(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, II), AM).
1350 addImm(0).addMetadata(DI->getVariable());
1234 addFullAddress(BuildMI(MBB, DL, II), AM).addImm(0).
1235 addMetadata(DI->getVariable());
13511236 return true;
13521237 }
13531238 case Intrinsic::trap: {
1354 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(X86::TRAP));
1239 BuildMI(MBB, DL, TII.get(X86::TRAP));
13551240 return true;
13561241 }
13571242 case Intrinsic::sadd_with_overflow:
13871272 return false;
13881273
13891274 unsigned ResultReg = createResultReg(TLI.getRegClassFor(VT));
1390 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(OpC), ResultReg)
1391 .addReg(Reg1).addReg(Reg2);
1275 BuildMI(MBB, DL, TII.get(OpC), ResultReg).addReg(Reg1).addReg(Reg2);
13921276 unsigned DestReg1 = UpdateValueMap(&I, ResultReg);
13931277
13941278 // If the add with overflow is an intra-block value then we just want to
14061290 unsigned Opc = X86::SETBr;
14071291 if (I.getIntrinsicID() == Intrinsic::sadd_with_overflow)
14081292 Opc = X86::SETOr;
1409 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc), ResultReg);
1293 BuildMI(MBB, DL, TII.get(Opc), ResultReg);
14101294 return true;
14111295 }
14121296 }
15331417
15341418 // Issue CALLSEQ_START
15351419 unsigned AdjStackDown = TM.getRegisterInfo()->getCallFrameSetupOpcode();
1536 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(AdjStackDown))
1537 .addImm(NumBytes);
1420 BuildMI(MBB, DL, TII.get(AdjStackDown)).addImm(NumBytes);
15381421
15391422 // Process argument: walk the register/memloc assignments, inserting
15401423 // copies / loads.
15901473
15911474 if (VA.isRegLoc()) {
15921475 TargetRegisterClass* RC = TLI.getRegClassFor(ArgVT);
1593 bool Emitted = TII.copyRegToReg(*FuncInfo.MBB, FuncInfo.InsertPt,
1594 VA.getLocReg(), Arg, RC, RC, DL);
1476 bool Emitted = TII.copyRegToReg(*MBB, MBB->end(), VA.getLocReg(),
1477 Arg, RC, RC, DL);
15951478 assert(Emitted && "Failed to emit a copy instruction!"); Emitted=Emitted;
15961479 Emitted = true;
15971480 RegArgs.push_back(VA.getLocReg());
16171500 if (Subtarget->isPICStyleGOT()) {
16181501 TargetRegisterClass *RC = X86::GR32RegisterClass;
16191502 unsigned Base = getInstrInfo()->getGlobalBaseReg(FuncInfo.MF);
1620 bool Emitted = TII.copyRegToReg(*FuncInfo.MBB, FuncInfo.InsertPt,
1621 X86::EBX, Base, RC, RC, DL);
1503 bool Emitted = TII.copyRegToReg(*MBB, MBB->end(), X86::EBX, Base, RC, RC,
1504 DL);
16221505 assert(Emitted && "Failed to emit a copy instruction!"); Emitted=Emitted;
16231506 Emitted = true;
16241507 }
16281511 if (CalleeOp) {
16291512 // Register-indirect call.
16301513 unsigned CallOpc = Subtarget->is64Bit() ? X86::CALL64r : X86::CALL32r;
1631 MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(CallOpc))
1632 .addReg(CalleeOp);
1514 MIB = BuildMI(MBB, DL, TII.get(CallOpc)).addReg(CalleeOp);
16331515
16341516 } else {
16351517 // Direct call.
16581540 }
16591541
16601542
1661 MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(CallOpc))
1662 .addGlobalAddress(GV, 0, OpFlags);
1543 MIB = BuildMI(MBB, DL, TII.get(CallOpc)).addGlobalAddress(GV, 0, OpFlags);
16631544 }
16641545
16651546 // Add an implicit use GOT pointer in EBX.
16721553
16731554 // Issue CALLSEQ_END
16741555 unsigned AdjStackUp = TM.getRegisterInfo()->getCallFrameDestroyOpcode();
1675 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(AdjStackUp))
1676 .addImm(NumBytes).addImm(0);
1556 BuildMI(MBB, DL, TII.get(AdjStackUp)).addImm(NumBytes).addImm(0);
16771557
16781558 // Now handle call return value (if any).
16791559 SmallVector UsedRegs;
17001580 }
17011581
17021582 unsigned ResultReg = createResultReg(DstRC);
1703 bool Emitted = TII.copyRegToReg(*FuncInfo.MBB, FuncInfo.InsertPt, ResultReg,
1583 bool Emitted = TII.copyRegToReg(*MBB, MBB->end(), ResultReg,
17041584 RVLocs[0].getLocReg(), DstRC, SrcRC, DL);
17051585 assert(Emitted && "Failed to emit a copy instruction!"); Emitted=Emitted;
17061586 Emitted = true;
17141594 unsigned Opc = ResVT == MVT::f32 ? X86::ST_Fp80m32 : X86::ST_Fp80m64;
17151595 unsigned MemSize = ResVT.getSizeInBits()/8;
17161596 int FI = MFI.CreateStackObject(MemSize, MemSize, false);
1717 addFrameReference(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1718 TII.get(Opc)), FI)
1719 .addReg(ResultReg);
1597 addFrameReference(BuildMI(MBB, DL, TII.get(Opc)), FI).addReg(ResultReg);
17201598 DstRC = ResVT == MVT::f32
17211599 ? X86::FR32RegisterClass : X86::FR64RegisterClass;
17221600 Opc = ResVT == MVT::f32 ? X86::MOVSSrm : X86::MOVSDrm;
17231601 ResultReg = createResultReg(DstRC);
1724 addFrameReference(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1725 TII.get(Opc), ResultReg), FI);
1602 addFrameReference(BuildMI(MBB, DL, TII.get(Opc), ResultReg), FI);
17261603 }
17271604
17281605 if (AndToI1) {
17291606 // Mask out all but lowest bit for some call which produces an i1.
17301607 unsigned AndResult = createResultReg(X86::GR8RegisterClass);
1731 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1608 BuildMI(MBB, DL,
17321609 TII.get(X86::AND8ri), AndResult).addReg(ResultReg).addImm(1);
17331610 ResultReg = AndResult;
17341611 }
17511628 return X86SelectLoad(I);
17521629 case Instruction::Store:
17531630 return X86SelectStore(I);
1754 case Instruction::Ret:
1755 return X86SelectRet(I);
17561631 case Instruction::ICmp:
17571632 case Instruction::FCmp:
17581633 return X86SelectCmp(I);
18531728 else
18541729 Opc = X86::LEA64r;
18551730 unsigned ResultReg = createResultReg(RC);
1856 addLeaAddress(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1857 TII.get(Opc), ResultReg), AM);
1731 addLeaAddress(BuildMI(MBB, DL, TII.get(Opc), ResultReg), AM);
18581732 return ResultReg;
18591733 }
18601734 return 0;
18841758 // Create the load from the constant pool.
18851759 unsigned MCPOffset = MCP.getConstantPoolIndex(C, Align);
18861760 unsigned ResultReg = createResultReg(RC);
1887 addConstantPoolReference(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1888 TII.get(Opc), ResultReg),
1761 addConstantPoolReference(BuildMI(MBB, DL, TII.get(Opc), ResultReg),
18891762 MCPOffset, PICBase, OpFlag);
18901763
18911764 return ResultReg;
19081781 unsigned Opc = Subtarget->is64Bit() ? X86::LEA64r : X86::LEA32r;
19091782 TargetRegisterClass* RC = TLI.getRegClassFor(TLI.getPointerTy());
19101783 unsigned ResultReg = createResultReg(RC);
1911 addLeaAddress(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL,
1912 TII.get(Opc), ResultReg), AM);
1784 addLeaAddress(BuildMI(MBB, DL, TII.get(Opc), ResultReg), AM);
19131785 return ResultReg;
19141786 }
19151787
12171217
12181218 bool
12191219 X86TargetLowering::CanLowerReturn(CallingConv::ID CallConv, bool isVarArg,
1220 const SmallVectorImpl<ISD::OutputArg> &Outs,
1220 const SmallVectorImpl<EVT> &OutTys,
1221 const SmallVectorImpl &ArgsFlags,
12211222 LLVMContext &Context) const {
12221223 SmallVector RVLocs;
12231224 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
12241225 RVLocs, Context);
1225 return CCInfo.CheckReturn(Outs, RetCC_X86);
1226 return CCInfo.CheckReturn(OutTys, ArgsFlags, RetCC_X86);
12261227 }
12271228
12281229 SDValue
739739
740740 virtual bool
741741 CanLowerReturn(CallingConv::ID CallConv, bool isVarArg,
742 const SmallVectorImpl<ISD::OutputArg> &Outs,
742 const SmallVectorImpl<EVT> &OutTys,
743 const SmallVectorImpl &ArgsFlags,
743744 LLVMContext &Context) const;
744745
745746 void ReplaceATOMIC_BINARY_64(SDNode *N, SmallVectorImpl &Results,
11341134
11351135 bool XCoreTargetLowering::
11361136 CanLowerReturn(CallingConv::ID CallConv, bool isVarArg,
1137 const SmallVectorImpl<ISD::OutputArg> &Outs,
1137 const SmallVectorImpl<EVT> &OutTys,
1138 const SmallVectorImpl &ArgsFlags,
11381139 LLVMContext &Context) const {
11391140 SmallVector RVLocs;
11401141 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
11411142 RVLocs, Context);
1142 return CCInfo.CheckReturn(Outs, RetCC_XCore);
1143 return CCInfo.CheckReturn(OutTys, ArgsFlags, RetCC_XCore);
11431144 }
11441145
11451146 SDValue
192192
193193 virtual bool
194194 CanLowerReturn(CallingConv::ID CallConv, bool isVarArg,
195 const SmallVectorImpl<ISD::OutputArg> &ArgsFlags,
195 const SmallVectorImpl<EVT> &OutTys,
196 const SmallVectorImpl &ArgsFlags,
196197 LLVMContext &Context) const;
197198 };
198199 }
1313
1414 ; X64: test1:
1515 ; X64: movslq %edi, %rax
16 ; X64: movl (%rsi,%rax,4), %e
16 ; X64: movl (%rsi,%rax,4), %eax
17 ; X64: ret
1718
1819 }
1920 define i32 @test2(i64 %t3, i32* %t1) nounwind {
44 ; CHECK: foo:
55 ; CHECK-NEXT: movq %rdi, -8(%rsp)
66 ; CHECK-NEXT: movq %rsi, -16(%rsp)
7 ; CHECK-NEXT: movsd 128(%rsi,%rdi,8), %xmm0
7 ; CHECK: movsd 128(%rsi,%rdi,8), %xmm0
88 ; CHECK-NEXT: ret
99
1010 define double @foo(i64 %x, double* %p) nounwind {
4848 ret i32 %tmp2
4949 }
5050
51 define void @ptrtoint_i1(i8* %p, i1* %q) nounwind {
51 define i1 @ptrtoint_i1(i8* %p) nounwind {
5252 %t = ptrtoint i8* %p to i1
53 store i1 %t, i1* %q
54 ret void
53 ret i1 %t
5554 }
5655 define i8* @inttoptr_i1(i1 %p) nounwind {
5756 %t = inttoptr i1 %p to i8*
8685 ret i8 %tmp
8786 }
8887
89 define void @load_store_i1(i1* %p, i1* %q) nounwind {
90 %t = load i1* %p
91 store i1 %t, i1* %q
88 define void @store_i1(i1* %p, i1 %t) nounwind {
89 store i1 %t, i1* %p
9290 ret void
9391 }
92 define i1 @load_i1(i1* %p) nounwind {
93 %t = load i1* %p
94 ret i1 %t
95 }
431431
432432 for (unsigned i = 0; i < Memo.PhysRegs->size(); ++i) {
433433 if ((*Memo.PhysRegs)[i] != "")
434 OS << " TII.copyRegToReg(*FuncInfo.MBB, FuncInfo.InsertPt, "
434 OS << " TII.copyRegToReg(*MBB, MBB->end(), "
435435 << (*Memo.PhysRegs)[i] << ", Op" << i << ", "
436436 << "TM.getRegisterInfo()->getPhysicalRegisterRegClass("
437437 << (*Memo.PhysRegs)[i] << "), "
525525
526526 for (unsigned i = 0; i < Memo.PhysRegs->size(); ++i) {
527527 if ((*Memo.PhysRegs)[i] != "")
528 OS << " TII.copyRegToReg(*FuncInfo.MBB, FuncInfo.InsertPt, "
528 OS << " TII.copyRegToReg(*MBB, MBB->end(), "
529529 << (*Memo.PhysRegs)[i] << ", Op" << i << ", "
530530 << "TM.getRegisterInfo()->getPhysicalRegisterRegClass("
531531 << (*Memo.PhysRegs)[i] << "), "