llvm.org GIT mirror llvm / f572191
Finish converting the rest of the NEON VLD instructions to use pseudo- instructions prior to regalloc. Since it's getting a little close to the 2.8 branch deadline, I'll have to leave the rest of the instructions handled by the NEONPreAllocPass for now, but I didn't want to leave half of the VLD instructions converted and the other half not. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112983 91177308-0d34-0410-b5e6-96231b3b80d8 Bob Wilson 10 years ago
4 changed file(s) with 149 addition(s) and 154 deletion(s). Raw diff Collapse all Expand all
104104 D2 = TRI->getSubReg(DstReg, ARM::dsub_5);
105105 D3 = TRI->getSubReg(DstReg, ARM::dsub_7);
106106 }
107 MIB.addReg(D0).addReg(D1);
107 MIB.addReg(D0, RegState::Define | getDeadRegState(DstIsDead))
108 .addReg(D1, RegState::Define | getDeadRegState(DstIsDead));
108109 if (NumRegs > 2)
109 MIB.addReg(D2);
110 MIB.addReg(D2, RegState::Define | getDeadRegState(DstIsDead));
110111 if (NumRegs > 3)
111 MIB.addReg(D3);
112 MIB.addReg(D3, RegState::Define | getDeadRegState(DstIsDead));
112113
113114 if (hasWriteBack) {
114115 bool WBIsDead = MI.getOperand(OpIdx).isDead();
115116 unsigned WBReg = MI.getOperand(OpIdx++).getReg();
116 MIB.addReg(WBReg, getDefRegState(true) | getDeadRegState(WBIsDead));
117 MIB.addReg(WBReg, RegState::Define | getDeadRegState(WBIsDead));
117118 }
118119 // Copy the addrmode6 operands.
119120 bool AddrIsKill = MI.getOperand(OpIdx).isKill();
127128
128129 MIB = AddDefaultPred(MIB);
129130 TransferImpOps(MI, MIB, MIB);
130 // Add an implicit def for the super-reg.
131 MIB.addReg(DstReg, (getDefRegState(true) | getDeadRegState(DstIsDead) |
132 getImplRegState(true)));
131 // For an instruction writing the odd subregs, add an implicit use of the
132 // super-register because the even subregs were loaded separately.
133 if (RegSpc == OddDblSpc)
134 MIB.addReg(DstReg, RegState::Implicit);
135 // Add an implicit def for the super-register.
136 MIB.addReg(DstReg, RegState::ImplicitDefine | getDeadRegState(DstIsDead));
133137 MI.eraseFromParent();
134138 }
135139
146150 if (hasWriteBack) {
147151 bool DstIsDead = MI.getOperand(OpIdx).isDead();
148152 unsigned DstReg = MI.getOperand(OpIdx++).getReg();
149 MIB.addReg(DstReg, getDefRegState(true) | getDeadRegState(DstIsDead));
153 MIB.addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead));
150154 }
151155 // Copy the addrmode6 operands.
152156 bool AddrIsKill = MI.getOperand(OpIdx).isKill();
335339 case ARM::VLD2q32Pseudo_UPD:
336340 ExpandVLD(MBBI, ARM::VLD2q32, true, SingleSpc, 4); break;
337341
342 case ARM::VLD3d8Pseudo:
343 ExpandVLD(MBBI, ARM::VLD3d8, false, SingleSpc, 3); break;
344 case ARM::VLD3d16Pseudo:
345 ExpandVLD(MBBI, ARM::VLD3d16, false, SingleSpc, 3); break;
346 case ARM::VLD3d32Pseudo:
347 ExpandVLD(MBBI, ARM::VLD3d32, false, SingleSpc, 3); break;
338348 case ARM::VLD1d64TPseudo:
339349 ExpandVLD(MBBI, ARM::VLD1d64T, false, SingleSpc, 3); break;
350 case ARM::VLD3d8Pseudo_UPD:
351 ExpandVLD(MBBI, ARM::VLD3d8_UPD, true, SingleSpc, 3); break;
352 case ARM::VLD3d16Pseudo_UPD:
353 ExpandVLD(MBBI, ARM::VLD3d16_UPD, true, SingleSpc, 3); break;
354 case ARM::VLD3d32Pseudo_UPD:
355 ExpandVLD(MBBI, ARM::VLD3d32_UPD, true, SingleSpc, 3); break;
340356 case ARM::VLD1d64TPseudo_UPD:
341 ExpandVLD(MBBI, ARM::VLD1d64T, true, SingleSpc, 3); break;
342
357 ExpandVLD(MBBI, ARM::VLD1d64T_UPD, true, SingleSpc, 3); break;
358 case ARM::VLD3q8Pseudo_UPD:
359 ExpandVLD(MBBI, ARM::VLD3q8_UPD, true, EvenDblSpc, 3); break;
360 case ARM::VLD3q16Pseudo_UPD:
361 ExpandVLD(MBBI, ARM::VLD3q16_UPD, true, EvenDblSpc, 3); break;
362 case ARM::VLD3q32Pseudo_UPD:
363 ExpandVLD(MBBI, ARM::VLD3q32_UPD, true, EvenDblSpc, 3); break;
364 case ARM::VLD3q8oddPseudo_UPD:
365 ExpandVLD(MBBI, ARM::VLD3q8_UPD, true, OddDblSpc, 3); break;
366 case ARM::VLD3q16oddPseudo_UPD:
367 ExpandVLD(MBBI, ARM::VLD3q16_UPD, true, OddDblSpc, 3); break;
368 case ARM::VLD3q32oddPseudo_UPD:
369 ExpandVLD(MBBI, ARM::VLD3q32_UPD, true, OddDblSpc, 3); break;
370
371 case ARM::VLD4d8Pseudo:
372 ExpandVLD(MBBI, ARM::VLD4d8, false, SingleSpc, 4); break;
373 case ARM::VLD4d16Pseudo:
374 ExpandVLD(MBBI, ARM::VLD4d16, false, SingleSpc, 4); break;
375 case ARM::VLD4d32Pseudo:
376 ExpandVLD(MBBI, ARM::VLD4d32, false, SingleSpc, 4); break;
343377 case ARM::VLD1d64QPseudo:
344378 ExpandVLD(MBBI, ARM::VLD1d64Q, false, SingleSpc, 4); break;
379 case ARM::VLD4d8Pseudo_UPD:
380 ExpandVLD(MBBI, ARM::VLD4d8_UPD, true, SingleSpc, 4); break;
381 case ARM::VLD4d16Pseudo_UPD:
382 ExpandVLD(MBBI, ARM::VLD4d16_UPD, true, SingleSpc, 4); break;
383 case ARM::VLD4d32Pseudo_UPD:
384 ExpandVLD(MBBI, ARM::VLD4d32_UPD, true, SingleSpc, 4); break;
345385 case ARM::VLD1d64QPseudo_UPD:
346 ExpandVLD(MBBI, ARM::VLD1d64Q, true, SingleSpc, 4); break;
386 ExpandVLD(MBBI, ARM::VLD1d64Q_UPD, true, SingleSpc, 4); break;
387 case ARM::VLD4q8Pseudo_UPD:
388 ExpandVLD(MBBI, ARM::VLD4q8_UPD, true, EvenDblSpc, 4); break;
389 case ARM::VLD4q16Pseudo_UPD:
390 ExpandVLD(MBBI, ARM::VLD4q16_UPD, true, EvenDblSpc, 4); break;
391 case ARM::VLD4q32Pseudo_UPD:
392 ExpandVLD(MBBI, ARM::VLD4q32_UPD, true, EvenDblSpc, 4); break;
393 case ARM::VLD4q8oddPseudo_UPD:
394 ExpandVLD(MBBI, ARM::VLD4q8_UPD, true, OddDblSpc, 4); break;
395 case ARM::VLD4q16oddPseudo_UPD:
396 ExpandVLD(MBBI, ARM::VLD4q16_UPD, true, OddDblSpc, 4); break;
397 case ARM::VLD4q32oddPseudo_UPD:
398 ExpandVLD(MBBI, ARM::VLD4q32_UPD, true, OddDblSpc, 4); break;
347399
348400 case ARM::VST1q8Pseudo:
349401 ExpandVST(MBBI, ARM::VST1q8, false, SingleSpc, 2); break;
11101110 break;
11111111 }
11121112
1113 EVT ResTy;
1114 if (NumVecs == 1)
1115 ResTy = VT;
1116 else {
1117 unsigned ResTyElts = (NumVecs == 3) ? 4 : NumVecs;
1118 if (!is64BitVector)
1119 ResTyElts *= 2;
1120 ResTy = EVT::getVectorVT(*CurDAG->getContext(), MVT::i64, ResTyElts);
1121 }
1122
11131123 SDValue Pred = getAL(CurDAG);
11141124 SDValue Reg0 = CurDAG->getRegister(0, MVT::i32);
1125 SDValue SuperReg;
11151126 if (is64BitVector) {
11161127 unsigned Opc = DOpcodes[OpcodeIndex];
11171128 const SDValue Ops[] = { MemAddr, Align, Pred, Reg0, Chain };
1118 SDNode *VLd;
1119 if (NumVecs <= 2) {
1120 EVT ResTy;
1121 if (NumVecs == 1)
1122 ResTy = VT;
1123 else
1124 ResTy = EVT::getVectorVT(*CurDAG->getContext(), MVT::i64, NumVecs);
1125 VLd = CurDAG->getMachineNode(Opc, dl, ResTy, MVT::Other, Ops, 5);
1126 } else {
1127 std::vector ResTys(NumVecs, VT);
1128 ResTys.push_back(MVT::Other);
1129 VLd = CurDAG->getMachineNode(Opc, dl, ResTys, Ops, 5);
1130 }
1129 SDNode *VLd = CurDAG->getMachineNode(Opc, dl, ResTy, MVT::Other, Ops, 5);
11311130 if (NumVecs == 1)
11321131 return VLd;
11331132
1134 SDValue SuperReg;
1135 if (NumVecs <= 2)
1136 SuperReg = SDValue(VLd, 0);
1137 else {
1138 SDValue V0 = SDValue(VLd, 0);
1139 SDValue V1 = SDValue(VLd, 1);
1140 // Form a REG_SEQUENCE to force register allocation.
1141 SDValue V2 = SDValue(VLd, 2);
1142 // If it's a vld3, form a quad D-register but discard the last part.
1143 SDValue V3 = (NumVecs == 3)
1144 ? SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF,dl,VT), 0)
1145 : SDValue(VLd, 3);
1146 SuperReg = SDValue(QuadDRegs(MVT::v4i64, V0, V1, V2, V3), 0);
1147 }
1148
1133 SuperReg = SDValue(VLd, 0);
11491134 assert(ARM::dsub_7 == ARM::dsub_0+7 && "Unexpected subreg numbering");
11501135 for (unsigned Vec = 0; Vec < NumVecs; ++Vec) {
11511136 SDValue D = CurDAG->getTargetExtractSubreg(ARM::dsub_0+Vec,
11521137 dl, VT, SuperReg);
11531138 ReplaceUses(SDValue(N, Vec), D);
11541139 }
1155 ReplaceUses(SDValue(N, NumVecs), SDValue(VLd, NumVecs <= 2 ? 1 : NumVecs));
1140 ReplaceUses(SDValue(N, NumVecs), SDValue(VLd, 1));
11561141 return NULL;
11571142 }
11581143
1159 EVT RegVT = GetNEONSubregVT(VT);
11601144 if (NumVecs <= 2) {
11611145 // Quad registers are directly supported for VLD1 and VLD2,
11621146 // loading pairs of D regs.
11631147 unsigned Opc = QOpcodes0[OpcodeIndex];
11641148 const SDValue Ops[] = { MemAddr, Align, Pred, Reg0, Chain };
1165
1166 EVT ResTy;
1167 if (NumVecs == 1)
1168 ResTy = VT;
1169 else
1170 ResTy = EVT::getVectorVT(*CurDAG->getContext(), MVT::i64, 2 * NumVecs);
11711149 SDNode *VLd = CurDAG->getMachineNode(Opc, dl, ResTy, MVT::Other, Ops, 5);
1172
1173 // Combine the even and odd subregs to produce the result.
11741150 if (NumVecs == 1)
11751151 return VLd;
11761152
1177 SDValue QQ = SDValue(VLd, 0);
1153 SuperReg = SDValue(VLd, 0);
11781154 Chain = SDValue(VLd, 1);
11791155
1180 SDValue Q0 = CurDAG->getTargetExtractSubreg(ARM::qsub_0, dl, VT, QQ);
1181 SDValue Q1 = CurDAG->getTargetExtractSubreg(ARM::qsub_1, dl, VT, QQ);
1182 ReplaceUses(SDValue(N, 0), Q0);
1183 ReplaceUses(SDValue(N, 1), Q1);
11841156 } else {
11851157 // Otherwise, quad registers are loaded with two separate instructions,
11861158 // where one loads the even registers and the other loads the odd registers.
1187
1188 std::vector ResTys(NumVecs, RegVT);
1189 ResTys.push_back(MemAddr.getValueType());
1190 ResTys.push_back(MVT::Other);
1159 EVT AddrTy = MemAddr.getValueType();
11911160
11921161 // Load the even subregs.
11931162 unsigned Opc = QOpcodes0[OpcodeIndex];
1194 const SDValue OpsA[] = { MemAddr, Align, Reg0, Pred, Reg0, Chain };
1195 SDNode *VLdA = CurDAG->getMachineNode(Opc, dl, ResTys, OpsA, 6);
1196 Chain = SDValue(VLdA, NumVecs+1);
1163 SDValue ImplDef =
1164 SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF, dl, ResTy), 0);
1165 const SDValue OpsA[] = { MemAddr, Align, Reg0, ImplDef, Pred, Reg0, Chain };
1166 SDNode *VLdA =
1167 CurDAG->getMachineNode(Opc, dl, ResTy, AddrTy, MVT::Other, OpsA, 7);
1168 Chain = SDValue(VLdA, 2);
11971169
11981170 // Load the odd subregs.
11991171 Opc = QOpcodes1[OpcodeIndex];
1200 const SDValue OpsB[] = { SDValue(VLdA, NumVecs),
1201 Align, Reg0, Pred, Reg0, Chain };
1202 SDNode *VLdB = CurDAG->getMachineNode(Opc, dl, ResTys, OpsB, 6);
1203 Chain = SDValue(VLdB, NumVecs+1);
1204
1205 SDValue V0 = SDValue(VLdA, 0);
1206 SDValue V1 = SDValue(VLdB, 0);
1207 SDValue V2 = SDValue(VLdA, 1);
1208 SDValue V3 = SDValue(VLdB, 1);
1209 SDValue V4 = SDValue(VLdA, 2);
1210 SDValue V5 = SDValue(VLdB, 2);
1211 SDValue V6 = (NumVecs == 3)
1212 ? SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF,dl,RegVT), 0)
1213 : SDValue(VLdA, 3);
1214 SDValue V7 = (NumVecs == 3)
1215 ? SDValue(CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF,dl,RegVT), 0)
1216 : SDValue(VLdB, 3);
1217 SDValue RegSeq = SDValue(OctoDRegs(MVT::v8i64, V0, V1, V2, V3,
1218 V4, V5, V6, V7), 0);
1219
1220 // Extract out the 3 / 4 Q registers.
1221 assert(ARM::qsub_3 == ARM::qsub_0+3 && "Unexpected subreg numbering");
1222 for (unsigned Vec = 0; Vec < NumVecs; ++Vec) {
1223 SDValue Q = CurDAG->getTargetExtractSubreg(ARM::qsub_0+Vec,
1224 dl, VT, RegSeq);
1225 ReplaceUses(SDValue(N, Vec), Q);
1226 }
1172 const SDValue OpsB[] = { SDValue(VLdA, 1), Align, Reg0, SDValue(VLdA, 0),
1173 Pred, Reg0, Chain };
1174 SDNode *VLdB =
1175 CurDAG->getMachineNode(Opc, dl, ResTy, AddrTy, MVT::Other, OpsB, 7);
1176 SuperReg = SDValue(VLdB, 0);
1177 Chain = SDValue(VLdB, 2);
1178 }
1179
1180 // Extract out the Q registers.
1181 assert(ARM::qsub_3 == ARM::qsub_0+3 && "Unexpected subreg numbering");
1182 for (unsigned Vec = 0; Vec < NumVecs; ++Vec) {
1183 SDValue Q = CurDAG->getTargetExtractSubreg(ARM::qsub_0+Vec,
1184 dl, VT, SuperReg);
1185 ReplaceUses(SDValue(N, Vec), Q);
12271186 }
12281187 ReplaceUses(SDValue(N, NumVecs), Chain);
12291188 return NULL;
21652124 }
21662125
21672126 case Intrinsic::arm_neon_vld3: {
2168 unsigned DOpcodes[] = { ARM::VLD3d8, ARM::VLD3d16,
2169 ARM::VLD3d32, ARM::VLD1d64T };
2170 unsigned QOpcodes0[] = { ARM::VLD3q8_UPD,
2171 ARM::VLD3q16_UPD,
2172 ARM::VLD3q32_UPD };
2173 unsigned QOpcodes1[] = { ARM::VLD3q8odd_UPD,
2174 ARM::VLD3q16odd_UPD,
2175 ARM::VLD3q32odd_UPD };
2127 unsigned DOpcodes[] = { ARM::VLD3d8Pseudo, ARM::VLD3d16Pseudo,
2128 ARM::VLD3d32Pseudo, ARM::VLD1d64TPseudo };
2129 unsigned QOpcodes0[] = { ARM::VLD3q8Pseudo_UPD,
2130 ARM::VLD3q16Pseudo_UPD,
2131 ARM::VLD3q32Pseudo_UPD };
2132 unsigned QOpcodes1[] = { ARM::VLD3q8oddPseudo_UPD,
2133 ARM::VLD3q16oddPseudo_UPD,
2134 ARM::VLD3q32oddPseudo_UPD };
21762135 return SelectVLD(N, 3, DOpcodes, QOpcodes0, QOpcodes1);
21772136 }
21782137
21792138 case Intrinsic::arm_neon_vld4: {
2180 unsigned DOpcodes[] = { ARM::VLD4d8, ARM::VLD4d16,
2181 ARM::VLD4d32, ARM::VLD1d64Q };
2182 unsigned QOpcodes0[] = { ARM::VLD4q8_UPD,
2183 ARM::VLD4q16_UPD,
2184 ARM::VLD4q32_UPD };
2185 unsigned QOpcodes1[] = { ARM::VLD4q8odd_UPD,
2186 ARM::VLD4q16odd_UPD,
2187 ARM::VLD4q32odd_UPD };
2139 unsigned DOpcodes[] = { ARM::VLD4d8Pseudo, ARM::VLD4d16Pseudo,
2140 ARM::VLD4d32Pseudo, ARM::VLD1d64QPseudo };
2141 unsigned QOpcodes0[] = { ARM::VLD4q8Pseudo_UPD,
2142 ARM::VLD4q16Pseudo_UPD,
2143 ARM::VLD4q32Pseudo_UPD };
2144 unsigned QOpcodes1[] = { ARM::VLD4q8oddPseudo_UPD,
2145 ARM::VLD4q16oddPseudo_UPD,
2146 ARM::VLD4q32oddPseudo_UPD };
21882147 return SelectVLD(N, 4, DOpcodes, QOpcodes0, QOpcodes1);
21892148 }
21902149
180180 : PseudoNLdSt<(outs QQPR:$dst, GPR:$wb),
181181 (ins addrmode6:$addr, am6offset:$offset), IIC_VST,
182182 "$addr.addr = $wb">;
183 class VLDQQQQWBPseudo
184 : PseudoNLdSt<(outs QQQQPR:$dst, GPR:$wb),
185 (ins addrmode6:$addr, am6offset:$offset, QQQQPR:$src), IIC_VST,
186 "$addr.addr = $wb, $src = $dst">;
183187
184188 // VLD1 : Vector Load (multiple single elements)
185189 class VLD1D op7_4, string Dt>
355359 def VLD3d16 : VLD3D<0b0100, 0b0100, "16">;
356360 def VLD3d32 : VLD3D<0b0100, 0b1000, "32">;
357361
362 def VLD3d8Pseudo : VLDQQPseudo;
363 def VLD3d16Pseudo : VLDQQPseudo;
364 def VLD3d32Pseudo : VLDQQPseudo;
365
358366 // ...with address register writeback:
359367 class VLD3DWB op11_8, bits<4> op7_4, string Dt>
360368 : NLdSt<0, 0b10, op11_8, op7_4,
367375 def VLD3d16_UPD : VLD3DWB<0b0100, 0b0100, "16">;
368376 def VLD3d32_UPD : VLD3DWB<0b0100, 0b1000, "32">;
369377
378 def VLD3d8Pseudo_UPD : VLDQQWBPseudo;
379 def VLD3d16Pseudo_UPD : VLDQQWBPseudo;
380 def VLD3d32Pseudo_UPD : VLDQQWBPseudo;
381
370382 // ...with double-spaced registers (non-updating versions for disassembly only):
371383 def VLD3q8 : VLD3D<0b0101, 0b0000, "8">;
372384 def VLD3q16 : VLD3D<0b0101, 0b0100, "16">;
375387 def VLD3q16_UPD : VLD3DWB<0b0101, 0b0100, "16">;
376388 def VLD3q32_UPD : VLD3DWB<0b0101, 0b1000, "32">;
377389
390 def VLD3q8Pseudo_UPD : VLDQQQQWBPseudo;
391 def VLD3q16Pseudo_UPD : VLDQQQQWBPseudo;
392 def VLD3q32Pseudo_UPD : VLDQQQQWBPseudo;
393
378394 // ...alternate versions to be allocated odd register numbers:
379 def VLD3q8odd_UPD : VLD3DWB<0b0101, 0b0000, "8">;
380 def VLD3q16odd_UPD : VLD3DWB<0b0101, 0b0100, "16">;
381 def VLD3q32odd_UPD : VLD3DWB<0b0101, 0b1000, "32">;
395 def VLD3q8oddPseudo_UPD : VLDQQQQWBPseudo;
396 def VLD3q16oddPseudo_UPD : VLDQQQQWBPseudo;
397 def VLD3q32oddPseudo_UPD : VLDQQQQWBPseudo;
382398
383399 // VLD4 : Vector Load (multiple 4-element structures)
384400 class VLD4D op11_8, bits<4> op7_4, string Dt>
390406 def VLD4d8 : VLD4D<0b0000, 0b0000, "8">;
391407 def VLD4d16 : VLD4D<0b0000, 0b0100, "16">;
392408 def VLD4d32 : VLD4D<0b0000, 0b1000, "32">;
409
410 def VLD4d8Pseudo : VLDQQPseudo;
411 def VLD4d16Pseudo : VLDQQPseudo;
412 def VLD4d32Pseudo : VLDQQPseudo;
393413
394414 // ...with address register writeback:
395415 class VLD4DWB op11_8, bits<4> op7_4, string Dt>
403423 def VLD4d16_UPD : VLD4DWB<0b0000, 0b0100, "16">;
404424 def VLD4d32_UPD : VLD4DWB<0b0000, 0b1000, "32">;
405425
426 def VLD4d8Pseudo_UPD : VLDQQWBPseudo;
427 def VLD4d16Pseudo_UPD : VLDQQWBPseudo;
428 def VLD4d32Pseudo_UPD : VLDQQWBPseudo;
429
406430 // ...with double-spaced registers (non-updating versions for disassembly only):
407431 def VLD4q8 : VLD4D<0b0001, 0b0000, "8">;
408432 def VLD4q16 : VLD4D<0b0001, 0b0100, "16">;
411435 def VLD4q16_UPD : VLD4DWB<0b0001, 0b0100, "16">;
412436 def VLD4q32_UPD : VLD4DWB<0b0001, 0b1000, "32">;
413437
438 def VLD4q8Pseudo_UPD : VLDQQQQWBPseudo;
439 def VLD4q16Pseudo_UPD : VLDQQQQWBPseudo;
440 def VLD4q32Pseudo_UPD : VLDQQQQWBPseudo;
441
414442 // ...alternate versions to be allocated odd register numbers:
415 def VLD4q8odd_UPD : VLD4DWB<0b0001, 0b0000, "8">;
416 def VLD4q16odd_UPD : VLD4DWB<0b0001, 0b0100, "16">;
417 def VLD4q32odd_UPD : VLD4DWB<0b0001, 0b1000, "32">;
443 def VLD4q8oddPseudo_UPD : VLDQQQQWBPseudo;
444 def VLD4q16oddPseudo_UPD : VLDQQQQWBPseudo;
445 def VLD4q32oddPseudo_UPD : VLDQQQQWBPseudo;
418446
419447 // VLD1LN : Vector Load (single element to one lane)
420448 // FIXME: Not yet implemented.
7373 Stride = 2;
7474 return true;
7575
76 case ARM::VLD3d8:
77 case ARM::VLD3d16:
78 case ARM::VLD3d32:
79 case ARM::VLD1d64T:
8076 case ARM::VLD3LNd8:
8177 case ARM::VLD3LNd16:
8278 case ARM::VLD3LNd32:
8480 NumRegs = 3;
8581 return true;
8682
87 case ARM::VLD3q8_UPD:
88 case ARM::VLD3q16_UPD:
89 case ARM::VLD3q32_UPD:
90 FirstOpnd = 0;
91 NumRegs = 3;
92 Offset = 0;
93 Stride = 2;
94 return true;
95
96 case ARM::VLD3q8odd_UPD:
97 case ARM::VLD3q16odd_UPD:
98 case ARM::VLD3q32odd_UPD:
99 FirstOpnd = 0;
100 NumRegs = 3;
101 Offset = 1;
102 Stride = 2;
103 return true;
104
10583 case ARM::VLD3LNq16:
10684 case ARM::VLD3LNq32:
10785 FirstOpnd = 0;
11896 Stride = 2;
11997 return true;
12098
121 case ARM::VLD4d8:
122 case ARM::VLD4d16:
123 case ARM::VLD4d32:
124 case ARM::VLD1d64Q:
12599 case ARM::VLD4LNd8:
126100 case ARM::VLD4LNd16:
127101 case ARM::VLD4LNd32:
128102 FirstOpnd = 0;
129103 NumRegs = 4;
130 return true;
131
132 case ARM::VLD4q8_UPD:
133 case ARM::VLD4q16_UPD:
134 case ARM::VLD4q32_UPD:
135 FirstOpnd = 0;
136 NumRegs = 4;
137 Offset = 0;
138 Stride = 2;
139 return true;
140
141 case ARM::VLD4q8odd_UPD:
142 case ARM::VLD4q16odd_UPD:
143 case ARM::VLD4q32odd_UPD:
144 FirstOpnd = 0;
145 NumRegs = 4;
146 Offset = 1;
147 Stride = 2;
148104 return true;
149105
150106 case ARM::VLD4LNq16: