llvm.org GIT mirror llvm / f516a66
Remove the need to cache the subtarget in the X86 TargetRegisterInfo classes. Use a Triple instead and simplify a lot of the querying logic to use lookups on the Triple. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@232071 91177308-0d34-0410-b5e6-96231b3b80d8 Eric Christopher 5 years ago
3 changed file(s) with 23 addition(s) and 24 deletion(s). Raw diff Collapse all Expand all
103103 : X86GenInstrInfo(
104104 (STI.isTarget64BitLP64() ? X86::ADJCALLSTACKDOWN64 : X86::ADJCALLSTACKDOWN32),
105105 (STI.isTarget64BitLP64() ? X86::ADJCALLSTACKUP64 : X86::ADJCALLSTACKUP32)),
106 Subtarget(STI), RI(STI) {
106 Subtarget(STI), RI(STI.getTargetTriple()) {
107107
108108 static const X86MemoryFoldTableEntry MemoryFoldTable2Addr[] = {
109109 { X86::ADC32ri, X86::ADC32mi, 0 },
5252 EnableBasePointer("x86-use-base-pointer", cl::Hidden, cl::init(true),
5353 cl::desc("Enable use of a base pointer for complex stack frames"));
5454
55 X86RegisterInfo::X86RegisterInfo(const X86Subtarget &STI)
56 : X86GenRegisterInfo(
57 (STI.is64Bit() ? X86::RIP : X86::EIP),
58 X86_MC::getDwarfRegFlavour(STI.getTargetTriple(), false),
59 X86_MC::getDwarfRegFlavour(STI.getTargetTriple(), true),
60 (STI.is64Bit() ? X86::RIP : X86::EIP)),
61 Subtarget(STI) {
55 X86RegisterInfo::X86RegisterInfo(const Triple &TT)
56 : X86GenRegisterInfo((TT.isArch64Bit() ? X86::RIP : X86::EIP),
57 X86_MC::getDwarfRegFlavour(TT, false),
58 X86_MC::getDwarfRegFlavour(TT, true),
59 (TT.isArch64Bit() ? X86::RIP : X86::EIP)) {
6260 X86_MC::InitLLVM2SEHRegisterMapping(this);
6361
6462 // Cache some information.
65 Is64Bit = Subtarget.is64Bit();
66 IsWin64 = Subtarget.isTargetWin64();
63 Is64Bit = TT.isArch64Bit();
64 IsWin64 = Is64Bit && TT.isOSWindows();
6765
6866 // Use a callee-saved register as the base pointer. These registers must
6967 // not conflict with any ABI requirements. For example, in 32-bit mode PIC
7068 // requires GOT in the EBX register before function calls via PLT GOT pointer.
7169 if (Is64Bit) {
7270 SlotSize = 8;
73 bool Use64BitReg =
74 Subtarget.isTarget64BitLP64() || Subtarget.isTargetNaCl64();
71 // This matches the simplified 32-bit pointer code in the data layout
72 // computation.
73 // FIXME: Should use the data layout?
74 bool Use64BitReg = TT.getEnvironment() != Triple::GNUX32;
7575 StackPtr = Use64BitReg ? X86::RSP : X86::ESP;
7676 FramePtr = Use64BitReg ? X86::RBP : X86::EBP;
7777 BasePtr = Use64BitReg ? X86::RBX : X86::EBX;
161161 const TargetRegisterClass *
162162 X86RegisterInfo::getPointerRegClass(const MachineFunction &MF,
163163 unsigned Kind) const {
164 const X86Subtarget &Subtarget = MF.getSubtarget();
164165 switch (Kind) {
165166 default: llvm_unreachable("Unexpected Kind in getPointerRegClass!");
166167 case 0: // Normal GPRs.
172173 return &X86::GR64_NOSPRegClass;
173174 return &X86::GR32_NOSPRegClass;
174175 case 2: // Available for tailcall (not callee-saved GPRs).
175 if (Subtarget.isTargetWin64())
176 if (IsWin64)
176177 return &X86::GR64_TCW64RegClass;
177 else if (Subtarget.is64Bit())
178 else if (Is64Bit)
178179 return &X86::GR64_TCRegClass;
179180
180181 const Function *F = MF.getFunction();
210211 case X86::GR64RegClassID:
211212 return 12 - FPDiff;
212213 case X86::VR128RegClassID:
213 return Subtarget.is64Bit() ? 10 : 4;
214 return Is64Bit ? 10 : 4;
214215 case X86::VR64RegClassID:
215216 return 4;
216217 }
218219
219220 const MCPhysReg *
220221 X86RegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
222 const X86Subtarget &Subtarget = MF->getSubtarget();
221223 bool HasAVX = Subtarget.hasAVX();
222224 bool HasAVX512 = Subtarget.hasAVX512();
223225 bool CallsEHReturn = MF->getMMI().callsEHReturn();
279281 const uint32_t *
280282 X86RegisterInfo::getCallPreservedMask(const MachineFunction &MF,
281283 CallingConv::ID CC) const {
284 const X86Subtarget &Subtarget = MF.getSubtarget();
282285 bool HasAVX = Subtarget.hasAVX();
283286 bool HasAVX512 = Subtarget.hasAVX512();
284287
404407 Reserved.set(*AI);
405408 }
406409 }
407 if (!Is64Bit || !Subtarget.hasAVX512()) {
410 if (!Is64Bit || !MF.getSubtarget().hasAVX512()) {
408411 for (unsigned n = 16; n != 32; ++n) {
409412 for (MCRegAliasIterator AI(X86::XMM0 + n, this, true); AI.isValid(); ++AI)
410413 Reserved.set(*AI);
567570 return TFI->hasFP(MF) ? FramePtr : StackPtr;
568571 }
569572
570 unsigned X86RegisterInfo::getPtrSizedFrameRegister(
571 const MachineFunction &MF) const {
573 unsigned
574 X86RegisterInfo::getPtrSizedFrameRegister(const MachineFunction &MF) const {
575 const X86Subtarget &Subtarget = MF.getSubtarget();
572576 unsigned FrameReg = getFrameRegister(MF);
573577 if (Subtarget.isTarget64BitILP32())
574578 FrameReg = getX86SubSuperRegister(FrameReg, MVT::i32, false);
1919 #include "X86GenRegisterInfo.inc"
2020
2121 namespace llvm {
22 class X86Subtarget;
23
2422 class X86RegisterInfo final : public X86GenRegisterInfo {
25 public:
26 const X86Subtarget &Subtarget;
27
2823 private:
2924 /// Is64Bit - Is the target 64-bits.
3025 ///
5247 unsigned BasePtr;
5348
5449 public:
55 X86RegisterInfo(const X86Subtarget &STI);
50 X86RegisterInfo(const Triple &TT);
5651
5752 // FIXME: This should be tablegen'd like getDwarfRegNum is
5853 int getSEHRegNum(unsigned i) const;