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[AMDGPU] computeKnownBitsForTargetNode for 24 bit mul Differential Revision: https://reviews.llvm.org/D37168 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@311896 91177308-0d34-0410-b5e6-96231b3b80d8 Stanislav Mekhanoshin 2 years ago
2 changed file(s) with 78 addition(s) and 14 deletion(s). Raw diff Collapse all Expand all
38403840
38413841 Known.resetAll(); // Don't know anything.
38423842
3843 KnownBits Known2;
38443843 unsigned Opc = Op.getOpcode();
38453844
38463845 switch (Opc) {
38713870
38723871 // High bits are zero.
38733872 Known.Zero = APInt::getHighBitsSet(BitWidth, BitWidth - 16);
3873 break;
3874 }
3875 case AMDGPUISD::MUL_U24:
3876 case AMDGPUISD::MUL_I24: {
3877 KnownBits LHSKnown, RHSKnown;
3878 DAG.computeKnownBits(Op.getOperand(0), LHSKnown);
3879 DAG.computeKnownBits(Op.getOperand(1), RHSKnown);
3880
3881 unsigned TrailZ = LHSKnown.countMinTrailingZeros() +
3882 RHSKnown.countMinTrailingZeros();
3883 Known.Zero.setLowBits(std::min(TrailZ, 32u));
3884
3885 unsigned LHSValBits = 32 - std::max(LHSKnown.countMinSignBits(), 8u);
3886 unsigned RHSValBits = 32 - std::max(RHSKnown.countMinSignBits(), 8u);
3887 unsigned MaxValBits = std::min(LHSValBits + RHSValBits, 32u);
3888 if (MaxValBits >= 32)
3889 break;
3890 bool Negative = false;
3891 if (Opc == AMDGPUISD::MUL_I24) {
3892 bool LHSNegative = !!(LHSKnown.One & (1 << 23));
3893 bool LHSPositive = !!(LHSKnown.Zero & (1 << 23));
3894 bool RHSNegative = !!(RHSKnown.One & (1 << 23));
3895 bool RHSPositive = !!(RHSKnown.Zero & (1 << 23));
3896 if ((!LHSNegative && !LHSPositive) || (!RHSNegative && !RHSPositive))
3897 break;
3898 Negative = (LHSNegative && RHSPositive) || (LHSPositive && RHSNegative);
3899 }
3900 if (Negative)
3901 Known.One.setHighBits(32 - MaxValBits);
3902 else
3903 Known.Zero.setHighBits(32 - MaxValBits);
38743904 break;
38753905 }
38763906 }
None ; RUN: llc -march=amdgcn < %s | FileCheck %s
0 ; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
11
2 ; CHECK-LABEL: {{^}}zext_shl64_to_32:
3 ; CHECK: s_lshl_b32
4 ; CHECK-NOT: s_lshl_b64
2 ; GCN-LABEL: {{^}}zext_shl64_to_32:
3 ; GCN: s_lshl_b32
4 ; GCN-NOT: s_lshl_b64
55 define amdgpu_kernel void @zext_shl64_to_32(i64 addrspace(1)* nocapture %out, i32 %x) {
66 %and = and i32 %x, 1073741823
77 %ext = zext i32 %and to i64
1010 ret void
1111 }
1212
13 ; CHECK-LABEL: {{^}}sext_shl64_to_32:
14 ; CHECK: s_lshl_b32
15 ; CHECK-NOT: s_lshl_b64
13 ; GCN-LABEL: {{^}}sext_shl64_to_32:
14 ; GCN: s_lshl_b32
15 ; GCN-NOT: s_lshl_b64
1616 define amdgpu_kernel void @sext_shl64_to_32(i64 addrspace(1)* nocapture %out, i32 %x) {
1717 %and = and i32 %x, 536870911
1818 %ext = sext i32 %and to i64
2121 ret void
2222 }
2323
24 ; CHECK-LABEL: {{^}}zext_shl64_overflow:
25 ; CHECK: s_lshl_b64
26 ; CHECK-NOT: s_lshl_b32
24 ; GCN-LABEL: {{^}}zext_shl64_overflow:
25 ; GCN: s_lshl_b64
26 ; GCN-NOT: s_lshl_b32
2727 define amdgpu_kernel void @zext_shl64_overflow(i64 addrspace(1)* nocapture %out, i32 %x) {
2828 %and = and i32 %x, 2147483647
2929 %ext = zext i32 %and to i64
3232 ret void
3333 }
3434
35 ; CHECK-LABEL: {{^}}sext_shl64_overflow:
36 ; CHECK: s_lshl_b64
37 ; CHECK-NOT: s_lshl_b32
35 ; GCN-LABEL: {{^}}sext_shl64_overflow:
36 ; GCN: s_lshl_b64
37 ; GCN-NOT: s_lshl_b32
3838 define amdgpu_kernel void @sext_shl64_overflow(i64 addrspace(1)* nocapture %out, i32 %x) {
3939 %and = and i32 %x, 2147483647
4040 %ext = sext i32 %and to i64
4242 store i64 %shl, i64 addrspace(1)* %out, align 4
4343 ret void
4444 }
45
46 ; GCN-LABEL: {{^}}mulu24_shl64:
47 ; GCN: v_mul_u32_u24_e32 [[M:v[0-9]+]], 7, v{{[0-9]+}}
48 ; GCN: v_lshlrev_b32_e32 v{{[0-9]+}}, 2, [[M]]
49 define amdgpu_kernel void @mulu24_shl64(i32 addrspace(1)* nocapture %arg) {
50 bb:
51 %tmp = tail call i32 @llvm.amdgcn.workitem.id.x()
52 %tmp1 = and i32 %tmp, 6
53 %mulconv = mul nuw nsw i32 %tmp1, 7
54 %tmp2 = zext i32 %mulconv to i64
55 %tmp3 = getelementptr inbounds i32, i32 addrspace(1)* %arg, i64 %tmp2
56 store i32 0, i32 addrspace(1)* %tmp3, align 4
57 ret void
58 }
59
60 ; GCN-LABEL: {{^}}muli24_shl64:
61 ; GCN: v_mul_i32_i24_e32 [[M:v[0-9]+]], -7, v{{[0-9]+}}
62 ; GCN: v_lshlrev_b32_e32 v{{[0-9]+}}, 3, [[M]]
63 define amdgpu_kernel void @muli24_shl64(i64 addrspace(1)* nocapture %arg, i32 addrspace(1)* nocapture readonly %arg1) {
64 bb:
65 %tmp = tail call i32 @llvm.amdgcn.workitem.id.x()
66 %tmp2 = sext i32 %tmp to i64
67 %tmp3 = getelementptr inbounds i32, i32 addrspace(1)* %arg1, i64 %tmp2
68 %tmp4 = load i32, i32 addrspace(1)* %tmp3, align 4
69 %tmp5 = or i32 %tmp4, -8388608
70 %tmp6 = mul nsw i32 %tmp5, -7
71 %tmp7 = zext i32 %tmp6 to i64
72 %tmp8 = shl nuw nsw i64 %tmp7, 3
73 %tmp9 = getelementptr inbounds i64, i64 addrspace(1)* %arg, i64 %tmp2
74 store i64 %tmp8, i64 addrspace(1)* %tmp9, align 8
75 ret void
76 }
77
78 declare i32 @llvm.amdgcn.workitem.id.x()