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Merging r243263: ------------------------------------------------------------------------ r243263 | mareko | 2015-07-27 04:37:42 -0700 (Mon, 27 Jul 2015) | 3 lines AMDGPU/SI: Fix the V_FRACT_F64 SI bug workaround This is a candidate for 3.7. ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_37@243316 91177308-0d34-0410-b5e6-96231b3b80d8 Hans Wennborg 5 years ago
2 changed file(s) with 8 addition(s) and 8 deletion(s). Raw diff Collapse all Expand all
32723272 (f64 (fadd (f64 (VOP3Mods f64:$x, i32:$mods)),
32733273 (f64 (fneg (f64 (ffloor (f64 (VOP3Mods f64:$x, i32:$mods)))))))),
32743274 (V_CNDMASK_B64_PSEUDO
3275 $x,
32763275 (V_MIN_F64
32773276 SRCMODS.NONE,
32783277 (V_FRACT_F64_e64 $mods, $x, DSTCLAMP.NONE, DSTOMOD.NONE),
32793278 SRCMODS.NONE,
32803279 (V_MOV_B64_PSEUDO 0x3fefffffffffffff),
32813280 DSTCLAMP.NONE, DSTOMOD.NONE),
3281 $x,
32823282 (V_CMP_CLASS_F64_e64 SRCMODS.NONE, $x, 3/*NaN*/))
32833283 >;
32843284
32903290 $x,
32913291 SRCMODS.NEG,
32923292 (V_CNDMASK_B64_PSEUDO
3293 $x,
32943293 (V_MIN_F64
32953294 SRCMODS.NONE,
32963295 (V_FRACT_F64_e64 $mods, $x, DSTCLAMP.NONE, DSTOMOD.NONE),
32973296 SRCMODS.NONE,
32983297 (V_MOV_B64_PSEUDO 0x3fefffffffffffff),
32993298 DSTCLAMP.NONE, DSTOMOD.NONE),
3299 $x,
33003300 (V_CMP_CLASS_F64_e64 SRCMODS.NONE, $x, 3/*NaN*/)),
33013301 DSTCLAMP.NONE, DSTOMOD.NONE)
33023302 >;
1010 ; SI: v_mov_b32_e32 v[[UPHI:[0-9]+]], 0x3fefffff
1111 ; SI: v_min_f64 v{{\[}}[[MINLO:[0-9]+]]:[[MINHI:[0-9]+]]], v{{\[}}[[UPLO]]:[[UPHI]]], [[FRC]]
1212 ; SI: v_cmp_class_f64_e64 [[COND:s\[[0-9]+:[0-9]+\]]], v{{\[}}[[LO]]:[[HI]]], 3
13 ; SI: v_cndmask_b32_e64 v[[RESLO:[0-9]+]], v[[LO]], v[[MINLO]], [[COND]]
14 ; SI: v_cndmask_b32_e64 v[[RESHI:[0-9]+]], v[[HI]], v[[MINHI]], [[COND]]
13 ; SI: v_cndmask_b32_e64 v[[RESLO:[0-9]+]], v[[MINLO]], v[[LO]], [[COND]]
14 ; SI: v_cndmask_b32_e64 v[[RESHI:[0-9]+]], v[[MINHI]], v[[HI]], [[COND]]
1515 ; SI: buffer_store_dwordx2 v{{\[}}[[RESLO]]:[[RESHI]]]
1616 ; CI: buffer_store_dwordx2 [[FRC]]
1717 define void @fract_f64(double addrspace(1)* %out, double addrspace(1)* %src) nounwind {
2727 ; SI: v_mov_b32_e32 v[[UPHI:[0-9]+]], 0x3fefffff
2828 ; SI: v_min_f64 v{{\[}}[[MINLO:[0-9]+]]:[[MINHI:[0-9]+]]], v{{\[}}[[UPLO]]:[[UPHI]]], [[FRC]]
2929 ; SI: v_cmp_class_f64_e64 [[COND:s\[[0-9]+:[0-9]+\]]], v{{\[}}[[LO]]:[[HI]]], 3
30 ; SI: v_cndmask_b32_e64 v[[RESLO:[0-9]+]], v[[LO]], v[[MINLO]], [[COND]]
31 ; SI: v_cndmask_b32_e64 v[[RESHI:[0-9]+]], v[[HI]], v[[MINHI]], [[COND]]
30 ; SI: v_cndmask_b32_e64 v[[RESLO:[0-9]+]], v[[MINLO]], v[[LO]], [[COND]]
31 ; SI: v_cndmask_b32_e64 v[[RESHI:[0-9]+]], v[[MINHI]], v[[HI]], [[COND]]
3232 ; SI: buffer_store_dwordx2 v{{\[}}[[RESLO]]:[[RESHI]]]
3333 ; CI: buffer_store_dwordx2 [[FRC]]
3434 define void @fract_f64_neg(double addrspace(1)* %out, double addrspace(1)* %src) nounwind {
4545 ; SI: v_mov_b32_e32 v[[UPHI:[0-9]+]], 0x3fefffff
4646 ; SI: v_min_f64 v{{\[}}[[MINLO:[0-9]+]]:[[MINHI:[0-9]+]]], v{{\[}}[[UPLO]]:[[UPHI]]], [[FRC]]
4747 ; SI: v_cmp_class_f64_e64 [[COND:s\[[0-9]+:[0-9]+\]]], v{{\[}}[[LO]]:[[HI]]], 3
48 ; SI: v_cndmask_b32_e64 v[[RESLO:[0-9]+]], v[[LO]], v[[MINLO]], [[COND]]
49 ; SI: v_cndmask_b32_e64 v[[RESHI:[0-9]+]], v[[HI]], v[[MINHI]], [[COND]]
48 ; SI: v_cndmask_b32_e64 v[[RESLO:[0-9]+]], v[[MINLO]], v[[LO]], [[COND]]
49 ; SI: v_cndmask_b32_e64 v[[RESHI:[0-9]+]], v[[MINHI]], v[[HI]], [[COND]]
5050 ; SI: buffer_store_dwordx2 v{{\[}}[[RESLO]]:[[RESHI]]]
5151 ; CI: buffer_store_dwordx2 [[FRC]]
5252 define void @fract_f64_neg_abs(double addrspace(1)* %out, double addrspace(1)* %src) nounwind {