llvm.org GIT mirror llvm / f49a409
Fix the encoding of the armv7m (MClass) for MSR registers other than aspr, iaspr, espr and xpsr which also needed to have 0b10 in their mask encoding bits. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158560 91177308-0d34-0410-b5e6-96231b3b80d8 Kevin Enderby 8 years ago
3 changed file(s) with 41 addition(s) and 31 deletion(s). Raw diff Collapse all Expand all
33533353 .Case("xpsr_nzcvq", 0x803)
33543354 .Case("xpsr_g", 0x403)
33553355 .Case("xpsr_nzcvqg", 0xc03)
3356 .Case("ipsr", 5)
3357 .Case("epsr", 6)
3358 .Case("iepsr", 7)
3359 .Case("msp", 8)
3360 .Case("psp", 9)
3361 .Case("primask", 16)
3362 .Case("basepri", 17)
3363 .Case("basepri_max", 18)
3364 .Case("faultmask", 19)
3365 .Case("control", 20)
3356 .Case("ipsr", 0x805)
3357 .Case("epsr", 0x806)
3358 .Case("iepsr", 0x807)
3359 .Case("msp", 0x808)
3360 .Case("psp", 0x809)
3361 .Case("primask", 0x810)
3362 .Case("basepri", 0x811)
3363 .Case("basepri_max", 0x812)
3364 .Case("faultmask", 0x813)
3365 .Case("control", 0x814)
33663366 .Default(~0U);
33673367
33683368 if (FlagsVal == ~0U)
33693369 return MatchOperand_NoMatch;
33703370
3371 if (!hasV7Ops() && FlagsVal >= 17 && FlagsVal <= 19)
3371 if (!hasV7Ops() && FlagsVal >= 0x811 && FlagsVal <= 0x813)
33723372 // basepri, basepri_max and faultmask only valid for V7m.
33733373 return MatchOperand_NoMatch;
33743374
670670 case 0x803: O << "xpsr"; return; // with _nzcvq bits is an alias for xpsr
671671 case 0x403: O << "xpsr_g"; return;
672672 case 0xc03: O << "xpsr_nzcvqg"; return;
673 case 5: O << "ipsr"; return;
674 case 6: O << "epsr"; return;
675 case 7: O << "iepsr"; return;
676 case 8: O << "msp"; return;
677 case 9: O << "psp"; return;
678 case 16: O << "primask"; return;
679 case 17: O << "basepri"; return;
680 case 18: O << "basepri_max"; return;
681 case 19: O << "faultmask"; return;
682 case 20: O << "control"; return;
673 case 5:
674 case 0x805: O << "ipsr"; return;
675 case 6:
676 case 0x806: O << "epsr"; return;
677 case 7:
678 case 0x807: O << "iepsr"; return;
679 case 8:
680 case 0x808: O << "msp"; return;
681 case 9:
682 case 0x809: O << "psp"; return;
683 case 0x10:
684 case 0x810: O << "primask"; return;
685 case 0x11:
686 case 0x811: O << "basepri"; return;
687 case 0x12:
688 case 0x812: O << "basepri_max"; return;
689 case 0x13:
690 case 0x813: O << "faultmask"; return;
691 case 0x14:
692 case 0x814: O << "control"; return;
683693 }
684694 }
685695
8585 @ CHECK: msr xpsr, r0 @ encoding: [0x80,0xf3,0x03,0x88]
8686 @ CHECK: msr xpsr_g, r0 @ encoding: [0x80,0xf3,0x03,0x84]
8787 @ CHECK: msr xpsr_nzcvqg, r0 @ encoding: [0x80,0xf3,0x03,0x8c]
88 @ CHECK: msr ipsr, r0 @ encoding: [0x80,0xf3,0x05,0x80]
89 @ CHECK: msr epsr, r0 @ encoding: [0x80,0xf3,0x06,0x80]
90 @ CHECK: msr iepsr, r0 @ encoding: [0x80,0xf3,0x07,0x80]
91 @ CHECK: msr msp, r0 @ encoding: [0x80,0xf3,0x08,0x80]
92 @ CHECK: msr psp, r0 @ encoding: [0x80,0xf3,0x09,0x80]
93 @ CHECK: msr primask, r0 @ encoding: [0x80,0xf3,0x10,0x80]
94 @ CHECK: msr basepri, r0 @ encoding: [0x80,0xf3,0x11,0x80]
95 @ CHECK: msr basepri_max, r0 @ encoding: [0x80,0xf3,0x12,0x80]
96 @ CHECK: msr faultmask, r0 @ encoding: [0x80,0xf3,0x13,0x80]
97 @ CHECK: msr control, r0 @ encoding: [0x80,0xf3,0x14,0x80]
88 @ CHECK: msr ipsr, r0 @ encoding: [0x80,0xf3,0x05,0x88]
89 @ CHECK: msr epsr, r0 @ encoding: [0x80,0xf3,0x06,0x88]
90 @ CHECK: msr iepsr, r0 @ encoding: [0x80,0xf3,0x07,0x88]
91 @ CHECK: msr msp, r0 @ encoding: [0x80,0xf3,0x08,0x88]
92 @ CHECK: msr psp, r0 @ encoding: [0x80,0xf3,0x09,0x88]
93 @ CHECK: msr primask, r0 @ encoding: [0x80,0xf3,0x10,0x88]
94 @ CHECK: msr basepri, r0 @ encoding: [0x80,0xf3,0x11,0x88]
95 @ CHECK: msr basepri_max, r0 @ encoding: [0x80,0xf3,0x12,0x88]
96 @ CHECK: msr faultmask, r0 @ encoding: [0x80,0xf3,0x13,0x88]
97 @ CHECK: msr control, r0 @ encoding: [0x80,0xf3,0x14,0x88]