llvm.org GIT mirror llvm / f43272c
CodeGen: Redo analyzePhysRegs() and computeRegisterLiveness() computeRegisterLiveness() was broken in that it reported dead for a register even if a subregister was alive. I assume this was because the results of analayzePhysRegs() are hard to understand with respect to subregisters. This commit: Changes the results of analyzePhysRegs (=struct PhysRegInfo) to be clearly understandable, also renames the fields to avoid silent breakage of third-party code (and improve the grammar). Fix all (two) users of computeRegisterLiveness() in llvm: By reenabling it and removing workarounds for the bug. This fixes http://llvm.org/PR24535 and http://llvm.org/PR25033 Differential Revision: http://reviews.llvm.org/D15320 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@255362 91177308-0d34-0410-b5e6-96231b3b80d8 Matthias Braun 4 years ago
10 changed file(s) with 98 addition(s) and 154 deletion(s). Raw diff Collapse all Expand all
695695
696696 /// Possible outcome of a register liveness query to computeRegisterLiveness()
697697 enum LivenessQueryResult {
698 LQR_Live, ///< Register is known to be live.
699 LQR_OverlappingLive, ///< Register itself is not live, but some overlapping
700 ///< register is.
701 LQR_Dead, ///< Register is known to be dead.
702 LQR_Unknown ///< Register liveness not decidable from local
703 ///< neighborhood.
698 LQR_Live, ///< Register is known to be (at least partially) live.
699 LQR_Dead, ///< Register is known to be fully dead.
700 LQR_Unknown ///< Register liveness not decidable from local neighborhood.
704701 };
705702
706703 /// Return whether (physical) register \p Reg has been ined and not
163163 bool Tied;
164164 };
165165
166 /// PhysRegInfo - Information about a physical register used by a set of
166 /// Information about how a physical register Reg is used by a set of
167167 /// operands.
168168 struct PhysRegInfo {
169 /// Clobbers - Reg or an overlapping register is defined, or a regmask
170 /// clobbers Reg.
171 bool Clobbers;
172
173 /// Defines - Reg or a super-register is defined.
174 bool Defines;
175
176 /// Reads - Reg or a super-register is read.
177 bool Reads;
178
179 /// ReadsOverlap - Reg or an overlapping register is read.
180 bool ReadsOverlap;
181
182 /// DefinesDead - All defs of a Reg or a super-register are dead.
183 bool DefinesDead;
184
185 /// There is a kill of Reg or a super-register.
186 bool Kills;
169 /// There is a regmask operand indicating Reg is clobbered.
170 /// \see MachineOperand::CreateRegMask().
171 bool Clobbered;
172
173 /// Reg or one of its aliases is defined. The definition may only cover
174 /// parts of the register.
175 bool Defined;
176 /// Reg or a super-register is defined. The definition covers the full
177 /// register.
178 bool FullyDefined;
179
180 /// Reg or ont of its aliases is read. The register may only be read
181 /// partially.
182 bool Read;
183 /// Reg or a super-register is read. The full register is read.
184 bool FullyRead;
185
186 /// Reg is FullyDefined and all defs of reg or an overlapping register are
187 /// dead.
188 bool DeadDef;
189
190 /// There is a use operand of reg or a super-register with kill flag set.
191 bool Killed;
187192 };
188193
189194 /// analyzeVirtReg - Analyze how the current instruction or bundle uses a
11381138 continue;
11391139 MIBundleOperands::PhysRegInfo RI =
11401140 MIBundleOperands(FoldMI).analyzePhysReg(Reg, &TRI);
1141 if (RI.Defines)
1141 if (RI.FullyDefined)
11421142 continue;
11431143 // FoldMI does not define this physreg. Remove the LI segment.
11441144 assert(MO->isDead() && "Cannot fold physreg def");
11771177 do {
11781178 --I;
11791179
1180 MachineOperandIteratorBase::PhysRegInfo Analysis =
1180 MachineOperandIteratorBase::PhysRegInfo Info =
11811181 ConstMIOperands(I).analyzePhysReg(Reg, TRI);
11821182
1183 if (Analysis.Defines)
1184 // Outputs happen after inputs so they take precedence if both are
1185 // present.
1186 return Analysis.DefinesDead ? LQR_Dead : LQR_Live;
1187
1188 if (Analysis.Kills || Analysis.Clobbers)
1189 // Register killed, so isn't live.
1183 // Defs happen after uses so they take precedence if both are present.
1184
1185 // Register is dead after a dead def of the full register.
1186 if (Info.DeadDef)
11901187 return LQR_Dead;
1191
1192 else if (Analysis.ReadsOverlap)
1193 // Defined or read without a previous kill - live.
1194 return Analysis.Reads ? LQR_Live : LQR_OverlappingLive;
1195
1188 // Register is (at least partially) live after a def.
1189 if (Info.Defined)
1190 return LQR_Live;
1191 // Register is dead after a full kill or clobber and no def.
1192 if (Info.Killed || Info.Clobbered)
1193 return LQR_Dead;
1194 // Register must be live if we read it.
1195 if (Info.Read)
1196 return LQR_Live;
11961197 } while (I != begin() && --N > 0);
11971198 }
11981199
11991200 // Did we get to the start of the block?
12001201 if (I == begin()) {
12011202 // If so, the register's state is definitely defined by the live-in state.
1202 for (MCRegAliasIterator RAI(Reg, TRI, /*IncludeSelf=*/true);
1203 RAI.isValid(); ++RAI) {
1203 for (MCRegAliasIterator RAI(Reg, TRI, /*IncludeSelf=*/true); RAI.isValid();
1204 ++RAI)
12041205 if (isLiveIn(*RAI))
1205 return (*RAI == Reg) ? LQR_Live : LQR_OverlappingLive;
1206 }
1206 return LQR_Live;
12071207
12081208 return LQR_Dead;
12091209 }
12151215 // If this is the last insn in the block, don't search forwards.
12161216 if (I != end()) {
12171217 for (++I; I != end() && N > 0; ++I, --N) {
1218 MachineOperandIteratorBase::PhysRegInfo Analysis =
1218 MachineOperandIteratorBase::PhysRegInfo Info =
12191219 ConstMIOperands(I).analyzePhysReg(Reg, TRI);
12201220
1221 if (Analysis.ReadsOverlap)
1222 // Used, therefore must have been live.
1223 return (Analysis.Reads) ?
1224 LQR_Live : LQR_OverlappingLive;
1225
1226 else if (Analysis.Clobbers || Analysis.Defines)
1227 // Defined (but not read) therefore cannot have been live.
1221 // Register is live when we read it here.
1222 if (Info.Read)
1223 return LQR_Live;
1224 // Register is dead if we can fully overwrite or clobber it here.
1225 if (Info.FullyDefined || Info.Clobbered)
12281226 return LQR_Dead;
12291227 }
12301228 }
292292 MachineOperandIteratorBase::analyzePhysReg(unsigned Reg,
293293 const TargetRegisterInfo *TRI) {
294294 bool AllDefsDead = true;
295 PhysRegInfo PRI = {false, false, false, false, false, false};
295 PhysRegInfo PRI = {false, false, false, false, false, false, false};
296296
297297 assert(TargetRegisterInfo::isPhysicalRegister(Reg) &&
298298 "analyzePhysReg not given a physical register!");
299299 for (; isValid(); ++*this) {
300300 MachineOperand &MO = deref();
301301
302 if (MO.isRegMask() && MO.clobbersPhysReg(Reg))
303 PRI.Clobbers = true; // Regmask clobbers Reg.
302 if (MO.isRegMask() && MO.clobbersPhysReg(Reg)) {
303 PRI.Clobbered = true;
304 continue;
305 }
304306
305307 if (!MO.isReg())
306308 continue;
309311 if (!MOReg || !TargetRegisterInfo::isPhysicalRegister(MOReg))
310312 continue;
311313
312 bool IsRegOrSuperReg = MOReg == Reg || TRI->isSuperRegister(MOReg, Reg);
313 bool IsRegOrOverlapping = MOReg == Reg || TRI->regsOverlap(MOReg, Reg);
314
315 if (IsRegOrSuperReg && MO.readsReg()) {
316 // Reg or a super-reg is read, and perhaps killed also.
317 PRI.Reads = true;
318 PRI.Kills = MO.isKill();
319 }
320
321 if (IsRegOrOverlapping && MO.readsReg()) {
322 PRI.ReadsOverlap = true;// Reg or an overlapping register is read.
323 }
324
325 if (!MO.isDef())
326 continue;
327
328 if (IsRegOrSuperReg) {
329 PRI.Defines = true; // Reg or a super-register is defined.
314 if (!TRI->regsOverlap(MOReg, Reg))
315 continue;
316
317 bool Covered = TRI->isSuperRegisterEq(MOReg, Reg);
318 if (MO.readsReg()) {
319 PRI.Read = true;
320 if (Covered) {
321 PRI.FullyRead = true;
322 if (MO.isKill())
323 PRI.Killed = true;
324 }
325 } else if (MO.isDef()) {
326 PRI.Defined = true;
327 if (Covered)
328 PRI.FullyDefined = true;
330329 if (!MO.isDead())
331330 AllDefsDead = false;
332331 }
333 if (IsRegOrOverlapping)
334 PRI.Clobbers = true; // Reg or an overlapping reg is defined.
335 }
336
337 if (AllDefsDead && PRI.Defines)
338 PRI.DefinesDead = true; // Reg or super-register was defined and was dead.
332 }
333
334 if (AllDefsDead && PRI.FullyDefined)
335 PRI.DeadDef = true;
339336
340337 return PRI;
341338 }
352352 MIOperands::PhysRegInfo PRI =
353353 MIOperands(I).analyzePhysReg(AArch64::NZCV, TRI);
354354
355 if (PRI.Reads) {
355 if (PRI.Read) {
356356 // The ccmp doesn't produce exactly the same flags as the original
357357 // compare, so reject the transform if there are uses of the flags
358358 // besides the terminators.
361361 return nullptr;
362362 }
363363
364 if (PRI.Clobbers) {
364 if (PRI.Defined || PRI.Clobbered) {
365365 DEBUG(dbgs() << "Not convertible compare: " << *I);
366366 ++NumUnknNZCVDefs;
367367 return nullptr;
20282028 }
20292029 }
20302030
2031 static bool isAnySubRegLive(unsigned Reg, const TargetRegisterInfo *TRI,
2032 MachineInstr *MI) {
2033 for (MCSubRegIterator Subreg(Reg, TRI, /* IncludeSelf */ true);
2034 Subreg.isValid(); ++Subreg)
2035 if (MI->getParent()->computeRegisterLiveness(TRI, *Subreg, MI) !=
2036 MachineBasicBlock::LQR_Dead)
2037 return true;
2038 return false;
2039 }
20402031 bool llvm::tryFoldSPUpdateIntoPushPop(const ARMSubtarget &Subtarget,
20412032 MachineFunction &MF, MachineInstr *MI,
20422033 unsigned NumBytes) {
21112102 // registers live within the function we might clobber a return value
21122103 // register; the other way a register can be live here is if it's
21132104 // callee-saved.
2114 // TODO: Currently, computeRegisterLiveness() does not report "live" if a
2115 // sub reg is live. When computeRegisterLiveness() works for sub reg, it
2116 // can replace isAnySubRegLive().
21172105 if (isCalleeSavedRegister(CurReg, CSRegs) ||
2118 isAnySubRegLive(CurReg, TRI, MI)) {
2106 MI->getParent()->computeRegisterLiveness(TRI, CurReg, MI) !=
2107 MachineBasicBlock::LQR_Dead) {
21192108 // VFP pops don't allow holes in the register list, so any skip is fatal
21202109 // for our transformation. GPR pops do, so we should just keep looking.
21212110 if (IsVFPPushPop)
44384438 // first frame index. See X86FrameLowering.cpp - clobbersTheStack.
44394439
44404440
4441 bool AXDead = (Reg == AX);
4442 // FIXME: The above could figure out that AX is dead in more cases with:
4443 // || (MachineBasicBlock::LQR_Dead ==
4444 // MBB.computeRegisterLiveness(&getRegisterInfo(), AX, MI));
4445 //
4446 // Unfortunately this is slightly broken, see PR24535 and the likely
4447 // related PR25033 PR24991 PR24992 PR25201. These issues seem to
4448 // showcase sub-register / super-register confusion: a previous kill
4449 // of AH but no kill of AL leads computeRegisterLiveness to
4450 // erroneously conclude that AX is dead.
4451 //
4452 // Once fixed, also update cmpxchg-clobber-flags.ll and
4453 // peephole-na-phys-copy-folding.ll.
4454
4455 if (!AXDead)
4441 bool AXDead = (Reg == AX) ||
4442 (MachineBasicBlock::LQR_Dead ==
4443 MBB.computeRegisterLiveness(&getRegisterInfo(), AX, MI));
4444 if (!AXDead) {
4445 // FIXME: If computeRegisterLiveness() reported LQR_Unknown then AX may
4446 // actually be dead. This is not a problem for correctness as we are just
4447 // (unnecessarily) saving+restoring a dead register. However the
4448 // MachineVerifier expects operands that read from dead registers
4449 // to be marked with the "undef" flag.
44564450 BuildMI(MBB, MI, DL, get(Push)).addReg(AX, getKillRegState(true));
4451 }
44574452 if (FromEFLAGS) {
44584453 BuildMI(MBB, MI, DL, get(X86::SETOr), X86::AL);
44594454 BuildMI(MBB, MI, DL, get(X86::LAHF));
None ; RUN: llc -mtriple=i386-linux-gnu %s -o - | FileCheck %s -check-prefix=i386
1 ; RUN: llc -mtriple=i386-linux-gnu -pre-RA-sched=fast %s -o - | FileCheck %s -check-prefix=i386f
0 ; RUN: llc -verify-machineinstrs -mtriple=i386-linux-gnu %s -o - | FileCheck %s -check-prefix=i386
1 ; RUN: llc -verify-machineinstrs -mtriple=i386-linux-gnu -pre-RA-sched=fast %s -o - | FileCheck %s -check-prefix=i386f
22
3 ; RUN: llc -mtriple=x86_64-linux-gnu %s -o - | FileCheck %s -check-prefix=x8664
4 ; RUN: llc -mtriple=x86_64-linux-gnu -pre-RA-sched=fast %s -o - | FileCheck %s -check-prefix=x8664
5 ; RUN: llc -mtriple=x86_64-linux-gnu -mattr=+sahf %s -o - | FileCheck %s -check-prefix=x8664-sahf
6 ; RUN: llc -mtriple=x86_64-linux-gnu -mattr=+sahf -pre-RA-sched=fast %s -o - | FileCheck %s -check-prefix=x8664-sahf
7 ; RUN: llc -mtriple=x86_64-linux-gnu -mcpu=corei7 %s -o - | FileCheck %s -check-prefix=x8664-sahf
8
9 ; FIXME: X86InstrInfo::copyPhysReg had code which figured out whether AX was
10 ; live or not to avoid save / restore when it's not needed. See FIXME in
11 ; that function for more details on which the code is currently
12 ; disabled. The extra push/pop are marked below and can be removed once
13 ; the issue is fixed.
14 ; -verify-machineinstrs should also be added back in the RUN lines above.
3 ; RUN: llc -verify-machineinstrs -mtriple=x86_64-linux-gnu %s -o - | FileCheck %s -check-prefix=x8664
4 ; RUN: llc -verify-machineinstrs -mtriple=x86_64-linux-gnu -pre-RA-sched=fast %s -o - | FileCheck %s -check-prefix=x8664
5 ; RUN: llc -verify-machineinstrs -mtriple=x86_64-linux-gnu -mattr=+sahf %s -o - | FileCheck %s -check-prefix=x8664-sahf
6 ; RUN: llc -verify-machineinstrs -mtriple=x86_64-linux-gnu -mattr=+sahf -pre-RA-sched=fast %s -o - | FileCheck %s -check-prefix=x8664-sahf
7 ; RUN: llc -verify-machineinstrs -mtriple=x86_64-linux-gnu -mcpu=corei7 %s -o - | FileCheck %s -check-prefix=x8664-sahf
158
169 declare i32 @foo()
1710 declare i32 @bar(i64)
2720 ; i386-NEXT: movl %edx, 4(%esp)
2821 ; i386-NEXT: movl %eax, (%esp)
2922 ; i386-NEXT: calll bar
30 ; ** FIXME Next line isn't actually necessary. **
31 ; i386-NEXT: pushl %eax
3223 ; i386-NEXT: movl [[FLAGS]], %eax
3324 ; i386-NEXT: addb $127, %al
3425 ; i386-NEXT: sahf
35 ; ** FIXME Next line isn't actually necessary. **
36 ; i386-NEXT: popl %eax
3726 ; i386-NEXT: jne
3827
3928 ; i386f-LABEL: test_intervening_call:
4029 ; i386f: cmpxchg8b
4130 ; i386f-NEXT: movl %eax, (%esp)
4231 ; i386f-NEXT: movl %edx, 4(%esp)
43 ; ** FIXME Next line isn't actually necessary. **
44 ; i386f-NEXT: pushl %eax
4532 ; i386f-NEXT: seto %al
4633 ; i386f-NEXT: lahf
4734 ; i386f-NEXT: movl %eax, [[FLAGS:%.*]]
48 ; ** FIXME Next line isn't actually necessary. **
49 ; i386f-NEXT: popl %eax
5035 ; i386f-NEXT: calll bar
51 ; ** FIXME Next line isn't actually necessary. **
52 ; i386f-NEXT: pushl %eax
5336 ; i386f-NEXT: movl [[FLAGS]], %eax
5437 ; i386f-NEXT: addb $127, %al
5538 ; i386f-NEXT: sahf
56 ; ** FIXME Next line isn't actually necessary. **
57 ; i386f-NEXT: popl %eax
5839 ; i386f-NEXT: jne
5940
6041 ; x8664-LABEL: test_intervening_call:
7657 ; x8664-sahf-NEXT: popq %rax
7758 ; x8664-sahf-NEXT: movq %rax, %rdi
7859 ; x8664-sahf-NEXT: callq bar
79 ; ** FIXME Next line isn't actually necessary. **
80 ; x8664-sahf-NEXT: pushq %rax
8160 ; x8664-sahf-NEXT: movq [[FLAGS]], %rax
8261 ; x8664-sahf-NEXT: addb $127, %al
8362 ; x8664-sahf-NEXT: sahf
84 ; ** FIXME Next line isn't actually necessary. **
85 ; x8664-sahf-NEXT: popq %rax
8663 ; x8664-sahf-NEXT: jne
8764
8865 %cx = cmpxchg i64* %foo, i64 %bar, i64 %baz seq_cst seq_cst
151128 define i32 @test_feed_cmov(i32* %addr, i32 %desired, i32 %new) {
152129 ; i386-LABEL: test_feed_cmov:
153130 ; i386: cmpxchgl
154 ; ** FIXME Next line isn't actually necessary. **
155 ; i386-NEXT: pushl %eax
156131 ; i386-NEXT: seto %al
157132 ; i386-NEXT: lahf
158133 ; i386-NEXT: movl %eax, [[FLAGS:%.*]]
159 ; ** FIXME Next line isn't actually necessary. **
160 ; i386-NEXT: popl %eax
161134 ; i386-NEXT: calll foo
162135 ; i386-NEXT: pushl %eax
163136 ; i386-NEXT: movl [[FLAGS]], %eax
167140
168141 ; i386f-LABEL: test_feed_cmov:
169142 ; i386f: cmpxchgl
170 ; ** FIXME Next line isn't actually necessary. **
171 ; i386f-NEXT: pushl %eax
172143 ; i386f-NEXT: seto %al
173144 ; i386f-NEXT: lahf
174145 ; i386f-NEXT: movl %eax, [[FLAGS:%.*]]
175 ; ** FIXME Next line isn't actually necessary. **
176 ; i386f-NEXT: popl %eax
177146 ; i386f-NEXT: calll foo
178147 ; i386f-NEXT: pushl %eax
179148 ; i386f-NEXT: movl [[FLAGS]], %eax
191160
192161 ; x8664-sahf-LABEL: test_feed_cmov:
193162 ; x8664-sahf: cmpxchgl
194 ; ** FIXME Next line isn't actually necessary. **
195 ; x8664-sahf: pushq %rax
196163 ; x8664-sahf: seto %al
197164 ; x8664-sahf-NEXT: lahf
198165 ; x8664-sahf-NEXT: movq %rax, [[FLAGS:%.*]]
199 ; ** FIXME Next line isn't actually necessary. **
200 ; x8664-sahf-NEXT: popq %rax
201166 ; x8664-sahf-NEXT: callq foo
202167 ; x8664-sahf-NEXT: pushq %rax
203168 ; x8664-sahf-NEXT: movq [[FLAGS]], %rax
None ; RUN: llc -mtriple=i386-linux-gnu %s -o - | FileCheck %s
1 ; RUN: llc -mtriple=x86_64-linux-gnu -mattr=+sahf %s -o - | FileCheck %s
2
3 ; FIXME Add -verify-machineinstrs back when PR24535 is fixed.
0 ; RUN: llc -verify-machineinstrs -mtriple=i386-linux-gnu %s -o - | FileCheck %s
1 ; RUN: llc -verify-machineinstrs -mtriple=x86_64-linux-gnu -mattr=+sahf %s -o - | FileCheck %s
42
53 ; The peephole optimizer can elide some physical register copies such as
64 ; EFLAGS. Make sure the flags are used directly, instead of needlessly using