llvm.org GIT mirror llvm / f38cc38
[PowerPC] Support powerpc64le as a syntax-checking target. This patch provides basic support for powerpc64le as an LLVM target. However, use of this target will not actually generate little-endian code. Instead, use of the target will cause the correct little-endian built-in defines to be generated, so that code that tests for __LITTLE_ENDIAN__, for example, will be correctly parsed for syntax-only testing. Code generation will otherwise be the same as powerpc64 (big-endian), for now. The patch leaves open the possibility of creating a little-endian PowerPC64 back end, but there is no immediate intent to create such a thing. The LLVM portions of this patch simply add ppc64le coverage everywhere that ppc64 coverage currently exists. There is nothing of any import worth testing until such time as little-endian code generation is implemented. In the corresponding Clang patch, there is a new test case variant to ensure that correct built-in defines for little-endian code are generated. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@187179 91177308-0d34-0410-b5e6-96231b3b80d8 Bill Schmidt 6 years ago
22 changed file(s) with 73 addition(s) and 17 deletion(s). Raw diff Collapse all Expand all
964964 ppc64:Linux:*:*)
965965 echo powerpc64-unknown-linux-gnu
966966 exit ;;
967 ppc64le:Linux:*:*)
968 echo powerpc64le-unknown-linux-gnu
969 exit ;;
967970 ppc:Linux:*:*)
968971 echo powerpc-unknown-linux-gnu
969972 exit ;;
529529 x86_64-*linux*)
530530 LD="${LD-ld} -m elf_i386"
531531 ;;
532 ppc64-*linux*|powerpc64-*linux*)
532 ppc64-*linux*|powerpc64-*linux*|ppc64le-*linux*|powerpc64le-*linux*)
533533 LD="${LD-ld} -m elf32ppclinux"
534534 ;;
535535 s390x-*linux*)
5454 msp430, // MSP430: msp430
5555 ppc, // PPC: powerpc
5656 ppc64, // PPC64: powerpc64, ppu
57 ppc64le, // PPC64LE: powerpc64le
5758 r600, // R600: AMD GPUs HD2XXX - HD6XXX
5859 sparc, // Sparc: sparc
5960 sparcv9, // Sparcv9: Sparcv9
27952795 return (ELFT::TargetEndianness == support::little) ?
27962796 Triple::mipsel : Triple::mips;
27972797 case ELF::EM_PPC64:
2798 return Triple::ppc64;
2798 return (ELFT::TargetEndianness == support::little) ?
2799 Triple::ppc64le : Triple::ppc64;
27992800 case ELF::EM_S390:
28002801 return Triple::systemz;
28012802 default:
395395 StubAddr++;
396396 *StubAddr = NopInstr;
397397 return Addr;
398 } else if (Arch == Triple::ppc64) {
398 } else if (Arch == Triple::ppc64 || Arch == Triple::ppc64le) {
399399 // PowerPC64 stub: the address points to a function descriptor
400400 // instead of the function itself. Load the function address
401401 // on r11 and sets it to control register. Also loads the function
769769 (uint32_t)(Value & 0xffffffffL), Type,
770770 (uint32_t)(Addend & 0xffffffffL));
771771 break;
772 case Triple::ppc64:
772 case Triple::ppc64: // Fall through.
773 case Triple::ppc64le:
773774 resolvePPC64Relocation(Section, Offset, Value, Type, Addend);
774775 break;
775776 case Triple::systemz:
984985 RelType, 0);
985986 Section.StubOffset += getMaxStubSize();
986987 }
987 } else if (Arch == Triple::ppc64) {
988 } else if (Arch == Triple::ppc64 || Arch == Triple::ppc64le) {
988989 if (RelType == ELF::R_PPC64_REL24) {
989990 // A PPC branch relocation will need a stub function if the target is
990991 // an external symbol (Symbol::ST_Unknown) or if the target address
171171 return 8; // 32-bit instruction and 32-bit address
172172 else if (Arch == Triple::mipsel || Arch == Triple::mips)
173173 return 16;
174 else if (Arch == Triple::ppc64)
174 else if (Arch == Triple::ppc64 || Arch == Triple::ppc64le)
175175 return 44;
176176 else if (Arch == Triple::x86_64)
177177 return 8; // GOT
7878 // to using it in -static mode.
7979 SixteenByteConstantSection = 0;
8080 if (RelocM != Reloc::Static &&
81 T.getArch() != Triple::x86_64 && T.getArch() != Triple::ppc64)
81 T.getArch() != Triple::x86_64 && T.getArch() != Triple::ppc64 &&
82 T.getArch() != Triple::ppc64le)
8283 SixteenByteConstantSection = // .literal16
8384 Ctx->getMachOSection("__TEXT", "__literal16",
8485 MCSectionMachO::S_16BYTE_LITERALS,
287288 FDEEncoding = dwarf::DW_EH_PE_udata4;
288289 TTypeEncoding = dwarf::DW_EH_PE_absptr;
289290 }
290 } else if (T.getArch() == Triple::ppc64) {
291 } else if (T.getArch() == Triple::ppc64 || T.getArch() == Triple::ppc64le) {
291292 PersonalityEncoding = dwarf::DW_EH_PE_indirect | dwarf::DW_EH_PE_pcrel |
292293 dwarf::DW_EH_PE_udata8;
293294 LSDAEncoding = dwarf::DW_EH_PE_pcrel | dwarf::DW_EH_PE_udata8;
2727 case mips64el:return "mips64el";
2828 case msp430: return "msp430";
2929 case ppc64: return "powerpc64";
30 case ppc64le: return "powerpc64le";
3031 case ppc: return "powerpc";
3132 case r600: return "r600";
3233 case sparc: return "sparc";
5960 case thumb: return "arm";
6061
6162 case ppc64:
63 case ppc64le:
6264 case ppc: return "ppc";
6365
6466 case mips:
167169 .Case("ppc64", ppc64)
168170 .Case("ppc32", ppc)
169171 .Case("ppc", ppc)
172 .Case("ppc64le", ppc64le)
170173 .Case("r600", r600)
171174 .Case("hexagon", hexagon)
172175 .Case("sparc", sparc)
196199 .Case("x86_64", "x86_64")
197200 .Case("powerpc", "ppc")
198201 .Case("powerpc64", "ppc64")
202 .Case("powerpc64le", "ppc64le")
199203 .Case("arm", "arm")
200204 .Cases("armv4t", "thumbv4t", "armv4t")
201205 .Cases("armv5", "armv5e", "thumbv5", "thumbv5e", "armv5")
219223 .Cases("amd64", "x86_64", Triple::x86_64)
220224 .Case("powerpc", Triple::ppc)
221225 .Cases("powerpc64", "ppu", Triple::ppc64)
226 .Case("powerpc64le", Triple::ppc64le)
222227 .Case("aarch64", Triple::aarch64)
223228 .Cases("arm", "xscale", Triple::arm)
224229 // FIXME: It would be good to replace these with explicit names for all the
689694 case llvm::Triple::mips64el:
690695 case llvm::Triple::nvptx64:
691696 case llvm::Triple::ppc64:
697 case llvm::Triple::ppc64le:
692698 case llvm::Triple::sparcv9:
693699 case llvm::Triple::systemz:
694700 case llvm::Triple::x86_64:
717723 case Triple::aarch64:
718724 case Triple::msp430:
719725 case Triple::systemz:
726 case Triple::ppc64le:
720727 T.setArch(UnknownArch);
721728 break;
722729
771778 case Triple::mips64el:
772779 case Triple::nvptx64:
773780 case Triple::ppc64:
781 case Triple::ppc64le:
774782 case Triple::sparcv9:
775783 case Triple::systemz:
776784 case Triple::x86_64:
221221 : MCTargetAsmParser(), STI(_STI), Parser(_Parser) {
222222 // Check for 64-bit vs. 32-bit pointer mode.
223223 Triple TheTriple(STI.getTargetTriple());
224 IsPPC64 = TheTriple.getArch() == Triple::ppc64;
224 IsPPC64 = (TheTriple.getArch() == Triple::ppc64 ||
225 TheTriple.getArch() == Triple::ppc64le);
225226 // Initialize the set of available features.
226227 setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
227228 }
13121313 extern "C" void LLVMInitializePowerPCAsmParser() {
13131314 RegisterMCAsmParser A(ThePPC32Target);
13141315 RegisterMCAsmParser B(ThePPC64Target);
1316 RegisterMCAsmParser C(ThePPC64LETarget);
13151317 }
13161318
13171319 #define GET_REGISTER_MATCHER
157157
158158 unsigned getPointerSize() const {
159159 StringRef Name = TheTarget.getName();
160 if (Name == "ppc64") return 8;
160 if (Name == "ppc64" || Name == "ppc64le") return 8;
161161 assert(Name == "ppc32" && "Unknown target name!");
162162 return 4;
163163 }
4141
4242 static MCRegisterInfo *createPPCMCRegisterInfo(StringRef TT) {
4343 Triple TheTriple(TT);
44 bool isPPC64 = (TheTriple.getArch() == Triple::ppc64);
44 bool isPPC64 = (TheTriple.getArch() == Triple::ppc64 ||
45 TheTriple.getArch() == Triple::ppc64le);
4546 unsigned Flavour = isPPC64 ? 0 : 1;
4647 unsigned RA = isPPC64 ? PPC::LR8 : PPC::LR;
4748
5960
6061 static MCAsmInfo *createPPCMCAsmInfo(const MCRegisterInfo &MRI, StringRef TT) {
6162 Triple TheTriple(TT);
62 bool isPPC64 = TheTriple.getArch() == Triple::ppc64;
63 bool isPPC64 = (TheTriple.getArch() == Triple::ppc64 ||
64 TheTriple.getArch() == Triple::ppc64le);
6365
6466 MCAsmInfo *MAI;
6567 if (TheTriple.isOSDarwin())
9092 }
9193 if (CM == CodeModel::Default) {
9294 Triple T(TT);
93 if (!T.isOSDarwin() && T.getArch() == Triple::ppc64)
95 if (!T.isOSDarwin() &&
96 (T.getArch() == Triple::ppc64 || T.getArch() == Triple::ppc64le))
9497 CM = CodeModel::Medium;
9598 }
9699 X->InitMCCodeGenInfo(RM, CM, OL);
124127 // Register the MC asm info.
125128 RegisterMCAsmInfoFn C(ThePPC32Target, createPPCMCAsmInfo);
126129 RegisterMCAsmInfoFn D(ThePPC64Target, createPPCMCAsmInfo);
130 RegisterMCAsmInfoFn E(ThePPC64LETarget, createPPCMCAsmInfo);
127131
128132 // Register the MC codegen info.
129133 TargetRegistry::RegisterMCCodeGenInfo(ThePPC32Target, createPPCMCCodeGenInfo);
130134 TargetRegistry::RegisterMCCodeGenInfo(ThePPC64Target, createPPCMCCodeGenInfo);
135 TargetRegistry::RegisterMCCodeGenInfo(ThePPC64LETarget,
136 createPPCMCCodeGenInfo);
131137
132138 // Register the MC instruction info.
133139 TargetRegistry::RegisterMCInstrInfo(ThePPC32Target, createPPCMCInstrInfo);
134140 TargetRegistry::RegisterMCInstrInfo(ThePPC64Target, createPPCMCInstrInfo);
141 TargetRegistry::RegisterMCInstrInfo(ThePPC64LETarget,
142 createPPCMCInstrInfo);
135143
136144 // Register the MC register info.
137145 TargetRegistry::RegisterMCRegInfo(ThePPC32Target, createPPCMCRegisterInfo);
138146 TargetRegistry::RegisterMCRegInfo(ThePPC64Target, createPPCMCRegisterInfo);
147 TargetRegistry::RegisterMCRegInfo(ThePPC64LETarget, createPPCMCRegisterInfo);
139148
140149 // Register the MC subtarget info.
141150 TargetRegistry::RegisterMCSubtargetInfo(ThePPC32Target,
142151 createPPCMCSubtargetInfo);
143152 TargetRegistry::RegisterMCSubtargetInfo(ThePPC64Target,
144153 createPPCMCSubtargetInfo);
154 TargetRegistry::RegisterMCSubtargetInfo(ThePPC64LETarget,
155 createPPCMCSubtargetInfo);
145156
146157 // Register the MC Code Emitter
147158 TargetRegistry::RegisterMCCodeEmitter(ThePPC32Target, createPPCMCCodeEmitter);
148159 TargetRegistry::RegisterMCCodeEmitter(ThePPC64Target, createPPCMCCodeEmitter);
160 TargetRegistry::RegisterMCCodeEmitter(ThePPC64LETarget,
161 createPPCMCCodeEmitter);
149162
150163 // Register the asm backend.
151164 TargetRegistry::RegisterMCAsmBackend(ThePPC32Target, createPPCAsmBackend);
152165 TargetRegistry::RegisterMCAsmBackend(ThePPC64Target, createPPCAsmBackend);
166 TargetRegistry::RegisterMCAsmBackend(ThePPC64LETarget, createPPCAsmBackend);
153167
154168 // Register the object streamer.
155169 TargetRegistry::RegisterMCObjectStreamer(ThePPC32Target, createMCStreamer);
156170 TargetRegistry::RegisterMCObjectStreamer(ThePPC64Target, createMCStreamer);
171 TargetRegistry::RegisterMCObjectStreamer(ThePPC64LETarget, createMCStreamer);
157172
158173 // Register the MCInstPrinter.
159174 TargetRegistry::RegisterMCInstPrinter(ThePPC32Target, createPPCMCInstPrinter);
160175 TargetRegistry::RegisterMCInstPrinter(ThePPC64Target, createPPCMCInstPrinter);
176 TargetRegistry::RegisterMCInstPrinter(ThePPC64LETarget,
177 createPPCMCInstPrinter);
161178 }
3232
3333 extern Target ThePPC32Target;
3434 extern Target ThePPC64Target;
35 extern Target ThePPC64LETarget;
3536
3637 MCCodeEmitter *createPPCMCCodeEmitter(const MCInstrInfo &MCII,
3738 const MCRegisterInfo &MRI,
251251 FeatureMFOCRF, FeatureFSqrt, FeatureFRES,
252252 FeatureFRSQRTE, FeatureSTFIWX,
253253 Feature64Bit /*, Feature64BitRegs */]>;
254 def : ProcessorModel<"ppc64le", G5Model,
255 [Directive64, FeatureAltivec,
256 FeatureMFOCRF, FeatureFSqrt, FeatureFRES,
257 FeatureFRSQRTE, FeatureSTFIWX,
258 Feature64Bit /*, Feature64BitRegs */]>;
254259
255260 //===----------------------------------------------------------------------===//
256261 // Calling Conventions
838838 "power6",
839839 "power6x",
840840 "power7",
841 "ppc64"
841 "ppc64",
842 "ppc64le"
842843 };
843844
844845 unsigned Directive = Subtarget.getDarwinDirective();
136136 // is enabled because external functions will assume this alignment.
137137 if (hasQPX() || isBGQ())
138138 StackAlignment = 32;
139
140 // Determine endianness.
141 IsLittleEndian = (TargetTriple.getArch() == Triple::ppc64le);
139142 }
140143
141144 /// hasLazyResolverStub - Return true if accesses to the specified global have
8888 bool IsBookE;
8989 bool HasLazyResolverStubs;
9090 bool IsJITCodeModel;
91 bool IsLittleEndian;
9192
9293 /// TargetTriple - What processor and OS we're targeting.
9394 Triple TargetTriple;
164165
165166 // isJITCodeModel - True if we're generating code for the JIT
166167 bool isJITCodeModel() const { return IsJITCodeModel; }
168
169 // isLittleEndian - True if generating little-endian code
170 bool isLittleEndian() const { return IsLittleEndian; }
167171
168172 // Specific obvious features.
169173 bool hasFSQRT() const { return HasFSQRT; }
2929 // Register the targets
3030 RegisterTargetMachine A(ThePPC32Target);
3131 RegisterTargetMachine B(ThePPC64Target);
32 RegisterTargetMachine C(ThePPC64LETarget);
3233 }
3334
3435 PPCTargetMachine::PPCTargetMachine(const Target &T, StringRef TT,
1111 #include "llvm/Support/TargetRegistry.h"
1212 using namespace llvm;
1313
14 Target llvm::ThePPC32Target, llvm::ThePPC64Target;
14 Target llvm::ThePPC32Target, llvm::ThePPC64Target, llvm::ThePPC64LETarget;
1515
1616 extern "C" void LLVMInitializePowerPCTargetInfo() {
1717 RegisterTarget
1919
2020 RegisterTarget
2121 Y(ThePPC64Target, "ppc64", "PowerPC 64");
22
23 RegisterTarget
24 Z(ThePPC64LETarget, "ppc64le", "PowerPC 64 LE");
2225 }
221221 llvm::Triple TargetTriple(M.getTargetTriple());
222222 bool IsAndroid = TargetTriple.getEnvironment() == llvm::Triple::Android;
223223 bool IsMacOSX = TargetTriple.getOS() == llvm::Triple::MacOSX;
224 bool IsPPC64 = TargetTriple.getArch() == llvm::Triple::ppc64;
224 bool IsPPC64 = TargetTriple.getArch() == llvm::Triple::ppc64 ||
225 TargetTriple.getArch() == llvm::Triple::ppc64le;
225226 bool IsX86_64 = TargetTriple.getArch() == llvm::Triple::x86_64;
226227 bool IsMIPS32 = TargetTriple.getArch() == llvm::Triple::mips ||
227228 TargetTriple.getArch() == llvm::Triple::mipsel;
960960 ppc64:Linux:*:*)
961961 echo powerpc64-unknown-linux-gnu
962962 exit ;;
963 ppc64le:Linux:*:*)
964 echo powerpc64le-unknown-linux-gnu
965 exit ;;
963966 ppc:Linux:*:*)
964967 echo powerpc-unknown-linux-gnu
965968 exit ;;
529529 x86_64-*linux*)
530530 LD="${LD-ld} -m elf_i386"
531531 ;;
532 ppc64-*linux*|powerpc64-*linux*)
532 ppc64-*linux*|powerpc64-*linux*|ppc64le-$linux*|powerpc64le-*linux*)
533533 LD="${LD-ld} -m elf32ppclinux"
534534 ;;
535535 s390x-*linux*)