llvm.org GIT mirror llvm / f37812e
Add support for 64-bit calling convention. This is far from complete, but it is enough to make it possible to write test cases using i64 arguments. Missing features: - Floating point arguments. - Receiving arguments on the stack. - Calls. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178523 91177308-0d34-0410-b5e6-96231b3b80d8 Jakob Stoklund Olesen 7 years ago
5 changed file(s) with 123 addition(s) and 12 deletion(s). Raw diff Collapse all Expand all
2121 CCIfType<[f64], CCAssignToReg<[D0, D1]>>
2222 ]>;
2323
24 // Sparc 64-bit C return-value convention.
25 def RetCC_Sparc64 : CallingConv<[
26 CCIfType<[i32], CCPromoteToType>,
27 CCIfType<[i64], CCAssignToReg<[I0, I1, I2, I3, I4, I5]>>,
28 CCIfType<[f32], CCAssignToReg<[F0, F1, F2, F3]>>,
29 CCIfType<[f64], CCAssignToReg<[D0, D1]>>
30 ]>;
31
2432 // Sparc 32-bit C Calling convention.
2533 def CC_Sparc32 : CallingConv<[
2634 //Custom assign SRet to [sp+64].
3341 // Alternatively, they are assigned to the stack in 4-byte aligned units.
3442 CCAssignToStack<4, 4>
3543 ]>;
44
45 // Sparc 64-bit C Calling convention.
46 def CC_Sparc64 : CallingConv<[
47 // All integers are promoted to i64 by the caller.
48 CCIfType<[i32], CCPromoteToType>,
49 // Integer arguments get passed in integer registers if there is space.
50 CCIfType<[i64], CCAssignToReg<[I0, I1, I2, I3, I4, I5]>>,
51 // FIXME: Floating point arguments.
52
53 // Alternatively, they are assigned to the stack in 8-byte aligned units.
54 CCAssignToStack<8, 8>
55 ]>;
9292 DAG.getTarget(), RVLocs, *DAG.getContext());
9393
9494 // Analize return values.
95 CCInfo.AnalyzeReturn(Outs, RetCC_Sparc32);
95 CCInfo.AnalyzeReturn(Outs, Subtarget->is64Bit() ?
96 RetCC_Sparc64 : RetCC_Sparc32);
9697
9798 SDValue Flag;
9899 SmallVector RetOps(1, Chain);
137138 &RetOps[0], RetOps.size());
138139 }
139140
140 /// LowerFormalArguments - V8 uses a very simple ABI, where all values are
141 SDValue SparcTargetLowering::
142 LowerFormalArguments(SDValue Chain,
143 CallingConv::ID CallConv,
144 bool IsVarArg,
145 const SmallVectorImpl &Ins,
146 DebugLoc DL,
147 SelectionDAG &DAG,
148 SmallVectorImpl &InVals) const {
149 if (Subtarget->is64Bit())
150 return LowerFormalArguments_64(Chain, CallConv, IsVarArg, Ins,
151 DL, DAG, InVals);
152 return LowerFormalArguments_32(Chain, CallConv, IsVarArg, Ins,
153 DL, DAG, InVals);
154 }
155
156 /// LowerFormalArguments32 - V8 uses a very simple ABI, where all values are
141157 /// passed in either one or two GPRs, including FP values. TODO: we should
142158 /// pass FP values in FP registers for fastcc functions.
143 SDValue
144 SparcTargetLowering::LowerFormalArguments(SDValue Chain,
145 CallingConv::ID CallConv, bool isVarArg,
146 const SmallVectorImpl
147 &Ins,
148 DebugLoc dl, SelectionDAG &DAG,
149 SmallVectorImpl &InVals)
150 const {
151
159 SDValue SparcTargetLowering::
160 LowerFormalArguments_32(SDValue Chain,
161 CallingConv::ID CallConv,
162 bool isVarArg,
163 const SmallVectorImpl &Ins,
164 DebugLoc dl,
165 SelectionDAG &DAG,
166 SmallVectorImpl &InVals) const {
152167 MachineFunction &MF = DAG.getMachineFunction();
153168 MachineRegisterInfo &RegInfo = MF.getRegInfo();
154169 SparcMachineFunctionInfo *FuncInfo = MF.getInfo();
337352 }
338353 }
339354
355 return Chain;
356 }
357
358 // Lower formal arguments for the 64 bit ABI.
359 SDValue SparcTargetLowering::
360 LowerFormalArguments_64(SDValue Chain,
361 CallingConv::ID CallConv,
362 bool IsVarArg,
363 const SmallVectorImpl &Ins,
364 DebugLoc DL,
365 SelectionDAG &DAG,
366 SmallVectorImpl &InVals) const {
367 MachineFunction &MF = DAG.getMachineFunction();
368
369 // Analyze arguments according to CC_Sparc64.
370 SmallVector ArgLocs;
371 CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(),
372 getTargetMachine(), ArgLocs, *DAG.getContext());
373 CCInfo.AnalyzeFormalArguments(Ins, CC_Sparc64);
374
375 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
376 CCValAssign &VA = ArgLocs[i];
377 if (VA.isRegLoc()) {
378 // This argument is passed in a register.
379 // All integer register arguments are promoted by the caller to i64.
380
381 // Create a virtual register for the promoted live-in value.
382 unsigned VReg = MF.addLiveIn(VA.getLocReg(),
383 getRegClassFor(VA.getLocVT()));
384 SDValue Arg = DAG.getCopyFromReg(Chain, DL, VReg, VA.getLocVT());
385
386 // The caller promoted the argument, so insert an Assert?ext SDNode so we
387 // won't promote the value again in this function.
388 switch (VA.getLocInfo()) {
389 case CCValAssign::SExt:
390 Arg = DAG.getNode(ISD::AssertSext, DL, VA.getLocVT(), Arg,
391 DAG.getValueType(VA.getValVT()));
392 break;
393 case CCValAssign::ZExt:
394 Arg = DAG.getNode(ISD::AssertZext, DL, VA.getLocVT(), Arg,
395 DAG.getValueType(VA.getValVT()));
396 break;
397 default:
398 break;
399 }
400
401 // Truncate the register down to the argument type.
402 if (VA.isExtInLoc())
403 Arg = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), Arg);
404
405 InVals.push_back(Arg);
406 continue;
407 }
408
409 // The registers are exhausted. This argument was passed on the stack.
410 assert(VA.isMemLoc());
411 }
340412 return Chain;
341413 }
342414
7676 const SmallVectorImpl &Ins,
7777 DebugLoc dl, SelectionDAG &DAG,
7878 SmallVectorImpl &InVals) const;
79 SDValue LowerFormalArguments_32(SDValue Chain,
80 CallingConv::ID CallConv,
81 bool isVarArg,
82 const SmallVectorImpl &Ins,
83 DebugLoc dl, SelectionDAG &DAG,
84 SmallVectorImpl &InVals) const;
85 SDValue LowerFormalArguments_64(SDValue Chain,
86 CallingConv::ID CallConv,
87 bool isVarArg,
88 const SmallVectorImpl &Ins,
89 DebugLoc dl, SelectionDAG &DAG,
90 SmallVectorImpl &InVals) const;
7991
8092 virtual SDValue
8193 LowerCall(TargetLowering::CallLoweringInfo &CLI,
0 ; RUN: llc < %s -march=sparcv9 | FileCheck %s
1
2 ; CHECK: ret2:
3 ; CHECK: or %g0, %i1, %i0
4 define i64 @ret2(i64 %a, i64 %b) {
5 ret i64 %b
6 }
0 ; RUN: llc < %s -march=sparc -mattr=-v9 | not grep popc
1 ; RUN: llc < %s -march=sparcv9 -mattr=v9 | grep popc
1 ; RUN: llc < %s -march=sparc -mattr=+v9 | grep popc
22
33 declare i32 @llvm.ctpop.i32(i32)
44