llvm.org GIT mirror llvm / f36ad4a
R600/SI: Remove M0Reg register class It is no longer used. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@237142 91177308-0d34-0410-b5e6-96231b3b80d8 Tom Stellard 5 years ago
4 changed file(s) with 2 addition(s) and 5 deletion(s). Raw diff Collapse all Expand all
193193 const TargetRegisterClass *SrcRC;
194194
195195 if (!TargetRegisterInfo::isVirtualRegister(SrcReg) ||
196 DstRC == &AMDGPU::M0RegRegClass ||
197196 MRI.getRegClass(SrcReg) == &AMDGPU::VReg_1RegClass)
198197 return false;
199198
346346 assert(!TargetRegisterInfo::isVirtualRegister(Reg));
347347
348348 static const TargetRegisterClass *BaseClasses[] = {
349 &AMDGPU::M0RegRegClass,
350349 &AMDGPU::VGPR_32RegClass,
351350 &AMDGPU::SReg_32RegClass,
352351 &AMDGPU::VReg_64RegClass,
181181
182182 def VCCReg : RegisterClass<"AMDGPU", [i64, i1], 64, (add VCC)>;
183183 def EXECReg : RegisterClass<"AMDGPU", [i64, i1], 64, (add EXEC)>;
184 def M0Reg : RegisterClass<"AMDGPU", [i32], 32, (add M0)>;
185184
186185 // Register class for all scalar registers (SGPRs + Special Registers)
187186 def SReg_32 : RegisterClass<"AMDGPU", [i32, f32], 32,
188 (add SGPR_32, M0Reg, VCC_LO, VCC_HI, EXEC_LO, EXEC_HI, FLAT_SCR_LO, FLAT_SCR_HI)
187 (add SGPR_32, M0, VCC_LO, VCC_HI, EXEC_LO, EXEC_HI, FLAT_SCR_LO, FLAT_SCR_HI)
189188 >;
190189
191190 def SGPR_64 : RegisterClass<"AMDGPU", [v2i32, i64, f64], 64, (add SGPR_64Regs)>;
6464
6565 ; SI-LABEL: @simple_read2st64_f32_over_max_offset
6666 ; SI-NOT: ds_read2st64_b32
67 ; SI: v_add_i32_e32 [[BIGADD:v[0-9]+]], 0x10000, {{v[0-9]+}}
6768 ; SI: ds_read_b32 {{v[0-9]+}}, {{v[0-9]+}} offset:256
68 ; SI: v_add_i32_e32 [[BIGADD:v[0-9]+]], 0x10000, {{v[0-9]+}}
6969 ; SI: ds_read_b32 {{v[0-9]+}}, [[BIGADD]]
7070 ; SI: s_endpgm
7171 define void @simple_read2st64_f32_over_max_offset(float addrspace(1)* %out, float addrspace(3)* %lds) #0 {