llvm.org GIT mirror llvm / f350b27
Move the point at which FastISel taps into the SelectionDAGISel process up to a higher level. This allows FastISel to leverage more of SelectionDAGISel's infastructure, such as updating Machine PHI nodes. Also, implement transitioning from SDISel back to FastISel in the middle of a block, so it's now possible to go back and forth. This allows FastISel to hand individual CallInsts and other complicated things off to SDISel to handle, while handling the rest of the block itself. To help support this, reorganize the SelectionDAG class so that it is allocated once and reused throughout a function, instead of being completely reallocated for each block. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@55219 91177308-0d34-0410-b5e6-96231b3b80d8 Dan Gohman 11 years ago
14 changed file(s) with 380 addition(s) and 346 deletion(s). Raw diff Collapse all Expand all
3434 class MachineFunction;
3535 class MachineConstantPoolValue;
3636 class FunctionLoweringInfo;
37
38 /// NodeAllocatorType - The AllocatorType for allocating SDNodes. We use
39 /// pool allocation with recycling.
40 ///
41 typedef RecyclingAllocator
42 AlignOf::Alignment>
43 NodeAllocatorType;
4437
4538 template<> class ilist_traits : public ilist_default_traits {
4639 mutable SDNode Sentinel;
7669 FunctionLoweringInfo &FLI;
7770 MachineModuleInfo *MMI;
7871
79 /// Root - The root of the entire DAG. EntryNode - The starting token.
80 SDValue Root, EntryNode;
72 /// EntryNode - The starting token.
73 SDNode EntryNode;
74
75 /// Root - The root of the entire DAG.
76 SDValue Root;
8177
8278 /// AllNodes - A linked list of nodes in the current DAG.
8379 ilist AllNodes;
8480
85 /// NodeAllocator - Pool allocation for nodes. The allocator isn't
86 /// allocated inside this class because we want to reuse a single
87 /// recycler across multiple SelectionDAG runs.
88 NodeAllocatorType &NodeAllocator;
81 /// NodeAllocatorType - The AllocatorType for allocating SDNodes. We use
82 /// pool allocation with recycling.
83 typedef RecyclingAllocator
84 AlignOf::Alignment>
85 NodeAllocatorType;
86
87 /// NodeAllocator - Pool allocation for nodes.
88 NodeAllocatorType NodeAllocator;
8989
9090 /// CSEMap - This structure is used to memoize nodes, automatically performing
9191 /// CSE with existing nodes with a duplicate is requested.
9292 FoldingSet CSEMap;
9393
94 /// OperandAllocator - Pool allocation for machine-opcode SDNode operands.
95 BumpPtrAllocator OperandAllocator;
96
9497 /// Allocator - Pool allocation for misc. objects that are created once per
9598 /// SelectionDAG.
9699 BumpPtrAllocator Allocator;
100103
101104 public:
102105 SelectionDAG(TargetLowering &tli, MachineFunction &mf,
103 FunctionLoweringInfo &fli, MachineModuleInfo *mmi,
104 NodeAllocatorType &nodeallocator);
106 FunctionLoweringInfo &fli, MachineModuleInfo *mmi);
105107 ~SelectionDAG();
108
109 /// reset - Clear state and free memory necessary to make this
110 /// SelectionDAG ready to process a new block.
111 ///
112 void reset();
106113
107114 MachineFunction &getMachineFunction() const { return MF; }
108115 const TargetMachine &getTarget() const;
151158
152159 /// getEntryNode - Return the token chain corresponding to the entry of the
153160 /// function.
154 const SDValue &getEntryNode() const { return EntryNode; }
161 SDValue getEntryNode() const {
162 return SDValue(const_cast(&EntryNode), 0);
163 }
155164
156165 /// setRoot - Set the current root tag of the SelectionDAG.
157166 ///
720729 void DeleteNodeNotInCSEMaps(SDNode *N);
721730
722731 unsigned getMVTAlignment(MVT MemoryVT) const;
732
733 void allnodes_clear();
723734
724735 // List of non-single value types.
725736 std::vector VTList;
1414 #ifndef LLVM_CODEGEN_SELECTIONDAG_ISEL_H
1515 #define LLVM_CODEGEN_SELECTIONDAG_ISEL_H
1616
17 #include "llvm/BasicBlock.h"
1718 #include "llvm/Pass.h"
1819 #include "llvm/Constant.h"
1920 #include "llvm/CodeGen/SelectionDAG.h"
5758 unsigned MakeReg(MVT VT);
5859
5960 virtual void EmitFunctionEntryCode(Function &Fn, MachineFunction &MF) {}
60 virtual void InstructionSelect(SelectionDAG &SD) = 0;
61 virtual void InstructionSelect() = 0;
6162 virtual void InstructionSelectPostProcessing() {}
6263
6364 void SelectRootInit() {
7172 /// OutOps vector.
7273 virtual bool SelectInlineAsmMemoryOperand(const SDValue &Op,
7374 char ConstraintCode,
74 std::vector &OutOps,
75 SelectionDAG &DAG) {
75 std::vector &OutOps) {
7676 return true;
7777 }
7878
167167
168168 /// SelectInlineAsmMemoryOperands - Calls to this are automatically generated
169169 /// by tblgen. Others should not call it.
170 void SelectInlineAsmMemoryOperands(std::vector &Ops,
171 SelectionDAG &DAG);
170 void SelectInlineAsmMemoryOperands(std::vector &Ops);
172171
173172 // Calls to these predicates are generated by tblgen.
174173 bool CheckAndMask(SDValue LHS, ConstantSDNode *RHS,
179178 private:
180179 void SelectAllBasicBlocks(Function &Fn, MachineFunction &MF,
181180 FunctionLoweringInfo &FuncInfo);
182 void SelectBasicBlock(BasicBlock *BB, MachineFunction &MF,
183 FunctionLoweringInfo &FuncInfo,
181 void FinishBasicBlock(FunctionLoweringInfo &FuncInfo,
182 std::vector > &PHINodesToUpdate);
183
184 void SelectBasicBlock(BasicBlock *LLVMBB,
185 BasicBlock::iterator Begin,
186 BasicBlock::iterator End,
187 bool DoArgs,
184188 std::vector > &PHINodesToUpdate,
185 NodeAllocatorType &NodeAllocator);
186 void FinishBasicBlock(BasicBlock *BB, MachineFunction &MF,
187 FunctionLoweringInfo &FuncInfo,
189 FunctionLoweringInfo &FuncInfo);
190 void CodeGenAndEmitDAG();
191 void LowerArguments(BasicBlock *BB, SelectionDAGLowering &SDL);
192
193 void ComputeLiveOutVRegInfo();
194
195 void HandlePHINodesInSuccessorBlocks(BasicBlock *LLVMBB,
196 FunctionLoweringInfo &FuncInfo,
188197 std::vector > &PHINodesToUpdate,
189 NodeAllocatorType &NodeAllocator);
190
191 void BuildSelectionDAG(SelectionDAG &DAG, BasicBlock *LLVMBB,
192 std::vector > &PHINodesToUpdate,
193 FunctionLoweringInfo &FuncInfo);
194 void CodeGenAndEmitDAG(SelectionDAG &DAG);
195 void LowerArguments(BasicBlock *BB, SelectionDAGLowering &SDL);
196
197 void ComputeLiveOutVRegInfo(SelectionDAG &DAG);
198 SelectionDAGLowering &SDL);
198199
199200 /// Pick a safe ordering for instructions for each target node in the
200201 /// graph.
201 ScheduleDAG *Schedule(SelectionDAG &DAG);
202 ScheduleDAG *Schedule();
202203
203204 /// SwitchCases - Vector of CaseBlock structures used to communicate
204205 /// SwitchInst code generation information.
546546 // Drop all of the operands and decrement used nodes use counts.
547547 for (SDNode::op_iterator I = N->op_begin(), E = N->op_end(); I != E; ++I)
548548 I->getVal()->removeUser(std::distance(N->op_begin(), I), N);
549 if (N->OperandsNeedDelete) {
549 if (N->OperandsNeedDelete)
550550 delete[] N->OperandList;
551 }
552 N->OperandList = 0;
553 N->NumOperands = 0;
554551
555552 AllNodes.remove(N);
556553 }
562559 void SelectionDAG::RemoveNodeFromCSEMaps(SDNode *N) {
563560 bool Erased = false;
564561 switch (N->getOpcode()) {
562 case ISD::EntryToken:
563 assert(0 && "EntryToken should not be in CSEMaps!");
564 return;
565565 case ISD::HANDLENODE: return; // noop.
566566 case ISD::CONDCODE:
567567 assert(CondCodeNodes[cast(N)->get()] &&
763763 }
764764
765765 SelectionDAG::SelectionDAG(TargetLowering &tli, MachineFunction &mf,
766 FunctionLoweringInfo &fli, MachineModuleInfo *mmi,
767 NodeAllocatorType &nodeallocator)
768 : TLI(tli), MF(mf), FLI(fli), MMI(mmi), NodeAllocator(nodeallocator) {
769 EntryNode = Root = getNode(ISD::EntryToken, MVT::Other);
766 FunctionLoweringInfo &fli, MachineModuleInfo *mmi)
767 : TLI(tli), MF(mf), FLI(fli), MMI(mmi),
768 EntryNode(ISD::EntryToken, getVTList(MVT::Other)),
769 Root(getEntryNode()) {
770 AllNodes.push_back(&EntryNode);
770771 }
771772
772773 SelectionDAG::~SelectionDAG() {
774 allnodes_clear();
775 }
776
777 void SelectionDAG::allnodes_clear() {
773778 while (!AllNodes.empty()) {
774779 SDNode *N = AllNodes.remove(AllNodes.begin());
775780 N->SetNextInBucket(0);
776 if (N->OperandsNeedDelete) {
781 if (N->OperandsNeedDelete)
777782 delete [] N->OperandList;
778 }
779 N->OperandList = 0;
780 N->NumOperands = 0;
781 }
783 }
784 }
785
786 void SelectionDAG::reset() {
787 allnodes_clear();
788 OperandAllocator.Reset();
789 CSEMap.clear();
790
791 ExtendedValueTypeNodes.clear();
792 ExternalSymbols.clear();
793 TargetExternalSymbols.clear();
794 std::fill(CondCodeNodes.begin(), CondCodeNodes.end(),
795 static_cast(0));
796 std::fill(ValueTypeNodes.begin(), ValueTypeNodes.end(),
797 static_cast(0));
798
799 EntryNode.Uses = 0;
800 AllNodes.push_back(&EntryNode);
801 Root = getEntryNode();
782802 }
783803
784804 SDValue SelectionDAG::getZeroExtendInReg(SDValue Op, MVT VT) {
39874007 delete[] N->OperandList;
39884008 if (N->isMachineOpcode()) {
39894009 // We're creating a final node that will live unmorphed for the
3990 // remainder of this SelectionDAG's duration, so we can allocate the
3991 // operands directly out of the pool with no recycling metadata.
3992 N->OperandList = Allocator.Allocate(NumOps);
4010 // remainder of the current SelectionDAG iteration, so we can allocate
4011 // the operands directly out of a pool with no recycling metadata.
4012 N->OperandList = OperandAllocator.Allocate(NumOps);
39934013 N->OperandsNeedDelete = false;
39944014 } else {
39954015 N->OperandList = new SDUse[NumOps];
393393 /// entry block, return true. This includes arguments used by switches, since
394394 /// the switch may expand into multiple basic blocks.
395395 static bool isOnlyUsedInEntryBlock(Argument *A) {
396 // With FastISel active, we may be splitting blocks, so force creation
397 // of virtual registers for all non-dead arguments.
398 if (EnableFastISel)
399 return A->use_empty();
400
396401 BasicBlock *Entry = A->getParent()->begin();
397402 for (Value::use_iterator UI = A->use_begin(), E = A->use_end(); UI != E; ++UI)
398403 if (cast(*UI)->getParent() != Entry || isa(*UI))
50935098 }
50945099 }
50955100
5096 void SelectionDAGISel::BuildSelectionDAG(SelectionDAG &DAG, BasicBlock *LLVMBB,
5097 std::vector > &PHINodesToUpdate,
5098 FunctionLoweringInfo &FuncInfo) {
5099 SelectionDAGLowering SDL(DAG, TLI, *AA, FuncInfo, GFI);
5100 BB = FuncInfo.MBBMap[LLVMBB];
5101
5102 // Before doing SelectionDAG ISel, see if FastISel has been requested.
5103 // FastISel doesn't currently support entry blocks, because that
5104 // requires special handling for arguments. And it doesn't support EH
5105 // landing pads, which also require special handling.
5106 // For now, also exclude blocks with terminators that aren't
5107 // unconditional branches.
5108 BasicBlock::iterator Begin = LLVMBB->begin();
5109 if (EnableFastISel &&
5110 LLVMBB != &LLVMBB->getParent()->getEntryBlock() &&
5111 !BB->isLandingPad() &&
5112 isa(LLVMBB->getTerminator()) &&
5113 cast(LLVMBB->getTerminator())->isUnconditional()) {
5114 if (FastISel *F = TLI.createFastISel(FuncInfo.MF)) {
5115 Begin = F->SelectInstructions(Begin, LLVMBB->end(),
5116 FuncInfo.ValueMap, FuncInfo.MBBMap, BB);
5117
5118 // Clean up the FastISel object. TODO: Reorganize what data is
5119 // stored in the FastISel class itself and what is merely passed
5120 // to the SelectInstructions method, and then move the creation
5121 // and deletion of the FastISel object up so that it is only
5122 // done once per MachineFunction.
5123 delete F;
5124
5125 if (Begin == LLVMBB->end())
5126 // The "fast" selector selected the entire block, so we're done.
5127 return;
5128
5129 if (!DisableFastISelAbort) {
5130 // The "fast" selector couldn't handle something and bailed.
5131 // For the purpose of debugging, just abort.
5132 #ifndef NDEBUG
5133 Begin->dump();
5134 #endif
5135 assert(0 && "FastISel didn't select the entire block");
5136 abort();
5137 }
5138 }
5139 }
5140
5141 // Lower any arguments needed in this block if this is the entry block.
5142 if (LLVMBB == &LLVMBB->getParent()->getEntryBlock())
5143 LowerArguments(LLVMBB, SDL);
5144
5145 SDL.setCurrentBasicBlock(BB);
5146
5147 MachineModuleInfo *MMI = DAG.getMachineModuleInfo();
5148
5149 if (MMI && BB->isLandingPad()) {
5150 // Add a label to mark the beginning of the landing pad. Deletion of the
5151 // landing pad can thus be detected via the MachineModuleInfo.
5152 unsigned LabelID = MMI->addLandingPad(BB);
5153 DAG.setRoot(DAG.getLabel(ISD::EH_LABEL, DAG.getEntryNode(), LabelID));
5154
5155 // Mark exception register as live in.
5156 unsigned Reg = TLI.getExceptionAddressRegister();
5157 if (Reg) BB->addLiveIn(Reg);
5158
5159 // Mark exception selector register as live in.
5160 Reg = TLI.getExceptionSelectorRegister();
5161 if (Reg) BB->addLiveIn(Reg);
5162
5163 // FIXME: Hack around an exception handling flaw (PR1508): the personality
5164 // function and list of typeids logically belong to the invoke (or, if you
5165 // like, the basic block containing the invoke), and need to be associated
5166 // with it in the dwarf exception handling tables. Currently however the
5167 // information is provided by an intrinsic (eh.selector) that can be moved
5168 // to unexpected places by the optimizers: if the unwind edge is critical,
5169 // then breaking it can result in the intrinsics being in the successor of
5170 // the landing pad, not the landing pad itself. This results in exceptions
5171 // not being caught because no typeids are associated with the invoke.
5172 // This may not be the only way things can go wrong, but it is the only way
5173 // we try to work around for the moment.
5174 BranchInst *Br = dyn_cast(LLVMBB->getTerminator());
5175
5176 if (Br && Br->isUnconditional()) { // Critical edge?
5177 BasicBlock::iterator I, E;
5178 for (I = LLVMBB->begin(), E = --LLVMBB->end(); I != E; ++I)
5179 if (isSelector(I))
5180 break;
5181
5182 if (I == E)
5183 // No catch info found - try to extract some from the successor.
5184 copyCatchInfo(Br->getSuccessor(0), LLVMBB, MMI, FuncInfo);
5185 }
5186 }
5187
5188 // Lower all of the non-terminator instructions.
5189 for (BasicBlock::iterator I = Begin, E = --LLVMBB->end();
5190 I != E; ++I)
5191 SDL.visit(*I);
5192
5193 // Ensure that all instructions which are used outside of their defining
5194 // blocks are available as virtual registers. Invoke is handled elsewhere.
5195 for (BasicBlock::iterator I = Begin, E = LLVMBB->end(); I != E;++I)
5196 if (!I->use_empty() && !isa(I) && !isa(I)) {
5197 DenseMap::iterator VMI =FuncInfo.ValueMap.find(I);
5198 if (VMI != FuncInfo.ValueMap.end())
5199 SDL.CopyValueToVirtualRegister(I, VMI->second);
5200 }
5201
5202 // Handle PHI nodes in successor blocks. Emit code into the SelectionDAG to
5203 // ensure constants are generated when needed. Remember the virtual registers
5204 // that need to be added to the Machine PHI nodes as input. We cannot just
5205 // directly add them, because expansion might result in multiple MBB's for one
5206 // BB. As such, the start of the BB might correspond to a different MBB than
5207 // the end.
5208 //
5101 /// Handle PHI nodes in successor blocks. Emit code into the SelectionDAG to
5102 /// ensure constants are generated when needed. Remember the virtual registers
5103 /// that need to be added to the Machine PHI nodes as input. We cannot just
5104 /// directly add them, because expansion might result in multiple MBB's for one
5105 /// BB. As such, the start of the BB might correspond to a different MBB than
5106 /// the end.
5107 ///
5108 void
5109 SelectionDAGISel::HandlePHINodesInSuccessorBlocks(BasicBlock *LLVMBB,
5110 FunctionLoweringInfo &FuncInfo,
5111 std::vector > &PHINodesToUpdate,
5112 SelectionDAGLowering &SDL) {
52095113 TerminatorInst *TI = LLVMBB->getTerminator();
52105114
52115115 // Emit constants only once even if used by multiple PHI nodes.
52865190 JTCases = SDL.JTCases;
52875191 BitTestCases.clear();
52885192 BitTestCases = SDL.BitTestCases;
5193 }
5194
5195 void SelectionDAGISel::SelectBasicBlock(BasicBlock *LLVMBB,
5196 BasicBlock::iterator Begin,
5197 BasicBlock::iterator End,
5198 bool DoArgs,
5199 std::vector > &PHINodesToUpdate,
5200 FunctionLoweringInfo &FuncInfo) {
5201 SelectionDAGLowering SDL(*CurDAG, TLI, *AA, FuncInfo, GFI);
5202
5203 // Lower any arguments needed in this block if this is the entry block.
5204 if (DoArgs)
5205 LowerArguments(LLVMBB, SDL);
5206
5207 SDL.setCurrentBasicBlock(BB);
5208
5209 MachineModuleInfo *MMI = CurDAG->getMachineModuleInfo();
5210
5211 if (MMI && BB->isLandingPad()) {
5212 // Add a label to mark the beginning of the landing pad. Deletion of the
5213 // landing pad can thus be detected via the MachineModuleInfo.
5214 unsigned LabelID = MMI->addLandingPad(BB);
5215 CurDAG->setRoot(CurDAG->getLabel(ISD::EH_LABEL,
5216 CurDAG->getEntryNode(), LabelID));
5217
5218 // Mark exception register as live in.
5219 unsigned Reg = TLI.getExceptionAddressRegister();
5220 if (Reg) BB->addLiveIn(Reg);
5221
5222 // Mark exception selector register as live in.
5223 Reg = TLI.getExceptionSelectorRegister();
5224 if (Reg) BB->addLiveIn(Reg);
5225
5226 // FIXME: Hack around an exception handling flaw (PR1508): the personality
5227 // function and list of typeids logically belong to the invoke (or, if you
5228 // like, the basic block containing the invoke), and need to be associated
5229 // with it in the dwarf exception handling tables. Currently however the
5230 // information is provided by an intrinsic (eh.selector) that can be moved
5231 // to unexpected places by the optimizers: if the unwind edge is critical,
5232 // then breaking it can result in the intrinsics being in the successor of
5233 // the landing pad, not the landing pad itself. This results in exceptions
5234 // not being caught because no typeids are associated with the invoke.
5235 // This may not be the only way things can go wrong, but it is the only way
5236 // we try to work around for the moment.
5237 BranchInst *Br = dyn_cast(LLVMBB->getTerminator());
5238
5239 if (Br && Br->isUnconditional()) { // Critical edge?
5240 BasicBlock::iterator I, E;
5241 for (I = LLVMBB->begin(), E = --LLVMBB->end(); I != E; ++I)
5242 if (isSelector(I))
5243 break;
5244
5245 if (I == E)
5246 // No catch info found - try to extract some from the successor.
5247 copyCatchInfo(Br->getSuccessor(0), LLVMBB, MMI, FuncInfo);
5248 }
5249 }
5250
5251 // Lower all of the non-terminator instructions.
5252 for (BasicBlock::iterator I = Begin; I != End; ++I)
5253 if (!isa(I))
5254 SDL.visit(*I);
5255
5256 // Ensure that all instructions which are used outside of their defining
5257 // blocks are available as virtual registers. Invoke is handled elsewhere.
5258 for (BasicBlock::iterator I = Begin; I != End; ++I)
5259 if (!I->use_empty() && !isa(I) && !isa(I)) {
5260 DenseMap::iterator VMI =FuncInfo.ValueMap.find(I);
5261 if (VMI != FuncInfo.ValueMap.end())
5262 SDL.CopyValueToVirtualRegister(I, VMI->second);
5263 }
5264
5265 // Handle PHI nodes in successor blocks.
5266 if (Begin != End && End == LLVMBB->end())
5267 HandlePHINodesInSuccessorBlocks(LLVMBB, FuncInfo, PHINodesToUpdate, SDL);
52895268
52905269 // Make sure the root of the DAG is up-to-date.
5291 DAG.setRoot(SDL.getControlRoot());
5270 CurDAG->setRoot(SDL.getControlRoot());
52925271
52935272 // Check whether calls in this block are real tail calls. Fix up CALL nodes
52945273 // with correct tailcall attribute so that the target can rely on the tailcall
52955274 // attribute indicating whether the call is really eligible for tail call
52965275 // optimization.
5297 CheckDAGForTailCallsAndFixThem(DAG, TLI);
5298 }
5299
5300 void SelectionDAGISel::ComputeLiveOutVRegInfo(SelectionDAG &DAG) {
5276 CheckDAGForTailCallsAndFixThem(*CurDAG, TLI);
5277
5278 // Final step, emit the lowered DAG as machine code.
5279 CodeGenAndEmitDAG();
5280 CurDAG->reset();
5281 }
5282
5283 void SelectionDAGISel::ComputeLiveOutVRegInfo() {
53015284 SmallPtrSet VisitedNodes;
53025285 SmallVector Worklist;
53035286
5304 Worklist.push_back(DAG.getRoot().Val);
5287 Worklist.push_back(CurDAG->getRoot().Val);
53055288
53065289 APInt Mask;
53075290 APInt KnownZero;
53345317 if (!SrcVT.isInteger() || SrcVT.isVector())
53355318 continue;
53365319
5337 unsigned NumSignBits = DAG.ComputeNumSignBits(Src);
5320 unsigned NumSignBits = CurDAG->ComputeNumSignBits(Src);
53385321 Mask = APInt::getAllOnesValue(SrcVT.getSizeInBits());
5339 DAG.ComputeMaskedBits(Src, Mask, KnownZero, KnownOne);
5322 CurDAG->ComputeMaskedBits(Src, Mask, KnownZero, KnownOne);
53405323
53415324 // Only install this information if it tells us something.
53425325 if (NumSignBits != 1 || KnownZero != 0 || KnownOne != 0) {
53435326 DestReg -= TargetRegisterInfo::FirstVirtualRegister;
5344 FunctionLoweringInfo &FLI = DAG.getFunctionLoweringInfo();
5327 FunctionLoweringInfo &FLI = CurDAG->getFunctionLoweringInfo();
53455328 if (DestReg >= FLI.LiveOutRegInfo.size())
53465329 FLI.LiveOutRegInfo.resize(DestReg+1);
53475330 FunctionLoweringInfo::LiveOutInfo &LOI = FLI.LiveOutRegInfo[DestReg];
53525335 }
53535336 }
53545337
5355 void SelectionDAGISel::CodeGenAndEmitDAG(SelectionDAG &DAG) {
5338 void SelectionDAGISel::CodeGenAndEmitDAG() {
53565339 std::string GroupName;
53575340 if (TimePassesIsEnabled)
53585341 GroupName = "Instruction Selection and Scheduling";
53595342 std::string BlockName;
53605343 if (ViewDAGCombine1 || ViewLegalizeTypesDAGs || ViewLegalizeDAGs ||
53615344 ViewDAGCombine2 || ViewISelDAGs || ViewSchedDAGs || ViewSUnitDAGs)
5362 BlockName = DAG.getMachineFunction().getFunction()->getName() + ':' +
5345 BlockName = CurDAG->getMachineFunction().getFunction()->getName() + ':' +
53635346 BB->getBasicBlock()->getName();
53645347
53655348 DOUT << "Initial selection DAG:\n";
5366 DEBUG(DAG.dump());
5367
5368 if (ViewDAGCombine1) DAG.viewGraph("dag-combine1 input for " + BlockName);
5349 DEBUG(CurDAG->dump());
5350
5351 if (ViewDAGCombine1) CurDAG->viewGraph("dag-combine1 input for " + BlockName);
53695352
53705353 // Run the DAG combiner in pre-legalize mode.
53715354 if (TimePassesIsEnabled) {
53725355 NamedRegionTimer T("DAG Combining 1", GroupName);
5373 DAG.Combine(false, *AA, Fast);
5356 CurDAG->Combine(false, *AA, Fast);
53745357 } else {
5375 DAG.Combine(false, *AA, Fast);
5358 CurDAG->Combine(false, *AA, Fast);
53765359 }
53775360
53785361 DOUT << "Optimized lowered selection DAG:\n";
5379 DEBUG(DAG.dump());
5362 DEBUG(CurDAG->dump());
53805363
53815364 // Second step, hack on the DAG until it only uses operations and types that
53825365 // the target supports.
53835366 if (EnableLegalizeTypes) {// Enable this some day.
5384 if (ViewLegalizeTypesDAGs) DAG.viewGraph("legalize-types input for " +
5385 BlockName);
5367 if (ViewLegalizeTypesDAGs) CurDAG->viewGraph("legalize-types input for " +
5368 BlockName);
53865369
53875370 if (TimePassesIsEnabled) {
53885371 NamedRegionTimer T("Type Legalization", GroupName);
5389 DAG.LegalizeTypes();
5372 CurDAG->LegalizeTypes();
53905373 } else {
5391 DAG.LegalizeTypes();
5374 CurDAG->LegalizeTypes();
53925375 }
53935376
53945377 DOUT << "Type-legalized selection DAG:\n";
5395 DEBUG(DAG.dump());
5378 DEBUG(CurDAG->dump());
53965379
53975380 // TODO: enable a dag combine pass here.
53985381 }
53995382
5400 if (ViewLegalizeDAGs) DAG.viewGraph("legalize input for " + BlockName);
5383 if (ViewLegalizeDAGs) CurDAG->viewGraph("legalize input for " + BlockName);
54015384
54025385 if (TimePassesIsEnabled) {
54035386 NamedRegionTimer T("DAG Legalization", GroupName);
5404 DAG.Legalize();
5387 CurDAG->Legalize();
54055388 } else {
5406 DAG.Legalize();
5389 CurDAG->Legalize();
54075390 }
54085391
54095392 DOUT << "Legalized selection DAG:\n";
5410 DEBUG(DAG.dump());
5411
5412 if (ViewDAGCombine2) DAG.viewGraph("dag-combine2 input for " + BlockName);
5393 DEBUG(CurDAG->dump());
5394
5395 if (ViewDAGCombine2) CurDAG->viewGraph("dag-combine2 input for " + BlockName);
54135396
54145397 // Run the DAG combiner in post-legalize mode.
54155398 if (TimePassesIsEnabled) {
54165399 NamedRegionTimer T("DAG Combining 2", GroupName);
5417 DAG.Combine(true, *AA, Fast);
5400 CurDAG->Combine(true, *AA, Fast);
54185401 } else {
5419 DAG.Combine(true, *AA, Fast);
5402 CurDAG->Combine(true, *AA, Fast);
54205403 }
54215404
54225405 DOUT << "Optimized legalized selection DAG:\n";
5423 DEBUG(DAG.dump());
5424
5425 if (ViewISelDAGs) DAG.viewGraph("isel input for " + BlockName);
5406 DEBUG(CurDAG->dump());
5407
5408 if (ViewISelDAGs) CurDAG->viewGraph("isel input for " + BlockName);
54265409
54275410 if (!Fast && EnableValueProp)
5428 ComputeLiveOutVRegInfo(DAG);
5411 ComputeLiveOutVRegInfo();
54295412
54305413 // Third, instruction select all of the operations to machine code, adding the
54315414 // code to the MachineBasicBlock.
54325415 if (TimePassesIsEnabled) {
54335416 NamedRegionTimer T("Instruction Selection", GroupName);
5434 InstructionSelect(DAG);
5417 InstructionSelect();
54355418 } else {
5436 InstructionSelect(DAG);
5419 InstructionSelect();
54375420 }
54385421
54395422 DOUT << "Selected selection DAG:\n";
5440 DEBUG(DAG.dump());
5441
5442 if (ViewSchedDAGs) DAG.viewGraph("scheduler input for " + BlockName);
5423 DEBUG(CurDAG->dump());
5424
5425 if (ViewSchedDAGs) CurDAG->viewGraph("scheduler input for " + BlockName);
54435426
54445427 // Schedule machine code.
54455428 ScheduleDAG *Scheduler;
54465429 if (TimePassesIsEnabled) {
54475430 NamedRegionTimer T("Instruction Scheduling", GroupName);
5448 Scheduler = Schedule(DAG);
5431 Scheduler = Schedule();
54495432 } else {
5450 Scheduler = Schedule(DAG);
5433 Scheduler = Schedule();
54515434 }
54525435
54535436 if (ViewSUnitDAGs) Scheduler->viewGraph();
54695452 delete Scheduler;
54705453 }
54715454
5472 // Perform target specific isel post processing.
5473 if (TimePassesIsEnabled) {
5474 NamedRegionTimer T("Instruction Selection Post Processing", GroupName);
5475 InstructionSelectPostProcessing();
5476 } else {
5477 InstructionSelectPostProcessing();
5478 }
5479
54805455 DOUT << "Selected machine code:\n";
54815456 DEBUG(BB->dump());
54825457 }
54835458
54845459 void SelectionDAGISel::SelectAllBasicBlocks(Function &Fn, MachineFunction &MF,
54855460 FunctionLoweringInfo &FuncInfo) {
5486 // Define NodeAllocator here so that memory allocation is reused for
5461 // Define the SelectionDAG here so that memory allocation is reused for
54875462 // each basic block.
5488 NodeAllocatorType NodeAllocator;
5463 SelectionDAG DAG(TLI, MF, FuncInfo,
5464 getAnalysisToUpdate());
5465 CurDAG = &DAG;
54895466
54905467 std::vector > PHINodesToUpdate;
54915468 for (Function::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I) {
54925469 BasicBlock *LLVMBB = &*I;
5470 BB = FuncInfo.MBBMap[LLVMBB];
5471
5472 BasicBlock::iterator Begin = LLVMBB->begin();
5473 BasicBlock::iterator End = LLVMBB->end();
5474 bool DoArgs = LLVMBB == &Fn.getEntryBlock();
5475
5476 // Before doing SelectionDAG ISel, see if FastISel has been requested.
5477 // FastISel doesn't support EH landing pads, which require special handling.
5478 if (EnableFastISel && !BB->isLandingPad()) {
5479 if (FastISel *F = TLI.createFastISel(FuncInfo.MF)) {
5480 while (Begin != End) {
5481 Begin = F->SelectInstructions(Begin, End, FuncInfo.ValueMap,
5482 FuncInfo.MBBMap, BB);
5483
5484 if (Begin == End)
5485 // The "fast" selector selected the entire block, so we're done.
5486 break;
5487
5488 // Handle certain instructions as single-LLVM-Instruction blocks.
5489 if (isa(Begin) || isa(Begin) ||
5490 isa(Begin)) {
5491 if (Begin->getType() != Type::VoidTy) {
5492 unsigned &R = FuncInfo.ValueMap[Begin];
5493 if (!R)
5494 R = FuncInfo.CreateRegForValue(Begin);
5495 }
5496
5497 SelectBasicBlock(LLVMBB, Begin, next(Begin), DoArgs,
5498 PHINodesToUpdate, FuncInfo);
5499
5500 ++Begin;
5501 DoArgs = false;
5502 continue;
5503 }
5504
5505 if (!DisableFastISelAbort &&
5506 // For now, don't abort on non-conditional-branch terminators.
5507 (!isa(Begin) ||
5508 (isa(Begin) &&
5509 cast(Begin)->isUnconditional()))) {
5510 // The "fast" selector couldn't handle something and bailed.
5511 // For the purpose of debugging, just abort.
5512 #ifndef NDEBUG
5513 Begin->dump();
5514 #endif
5515 assert(0 && "FastISel didn't select the entire block");
5516 }
5517 break;
5518 }
5519 delete F;
5520 }
5521 }
5522
5523 if (Begin != End || DoArgs)
5524 SelectBasicBlock(LLVMBB, Begin, End, DoArgs, PHINodesToUpdate, FuncInfo);
5525
5526 FinishBasicBlock(FuncInfo, PHINodesToUpdate);
54935527 PHINodesToUpdate.clear();
5494
5495 SelectBasicBlock(LLVMBB, MF, FuncInfo, PHINodesToUpdate, NodeAllocator);
5496 FinishBasicBlock(LLVMBB, MF, FuncInfo, PHINodesToUpdate, NodeAllocator);
5497 }
5528 }
5529
5530 CurDAG = 0;
54985531 }
54995532
55005533 void
5501 SelectionDAGISel::SelectBasicBlock(BasicBlock *LLVMBB, MachineFunction &MF,
5502 FunctionLoweringInfo &FuncInfo,
5503 std::vector > &PHINodesToUpdate,
5504 NodeAllocatorType &NodeAllocator) {
5505 SelectionDAG DAG(TLI, MF, FuncInfo,
5506 getAnalysisToUpdate(),
5507 NodeAllocator);
5508 CurDAG = &DAG;
5509
5510 // First step, lower LLVM code to some DAG. This DAG may use operations and
5511 // types that are not supported by the target.
5512 BuildSelectionDAG(DAG, LLVMBB, PHINodesToUpdate, FuncInfo);
5513
5514 // Second step, emit the lowered DAG as machine code.
5515 CodeGenAndEmitDAG(DAG);
5516 }
5517
5518 void
5519 SelectionDAGISel::FinishBasicBlock(BasicBlock *LLVMBB, MachineFunction &MF,
5520 FunctionLoweringInfo &FuncInfo,
5521 std::vector > &PHINodesToUpdate,
5522 NodeAllocatorType &NodeAllocator) {
5534 SelectionDAGISel::FinishBasicBlock(FunctionLoweringInfo &FuncInfo,
5535 std::vector > &PHINodesToUpdate) {
5536
5537 // Perform target specific isel post processing.
5538 InstructionSelectPostProcessing();
5539
5540 DOUT << "Target-post-processed machine code:\n";
5541 DEBUG(BB->dump());
5542
55235543 DOUT << "Total amount of phi nodes to update: "
55245544 << PHINodesToUpdate.size() << "\n";
55255545 DEBUG(for (unsigned i = 0, e = PHINodesToUpdate.size(); i != e; ++i)
55435563 for (unsigned i = 0, e = BitTestCases.size(); i != e; ++i) {
55445564 // Lower header first, if it wasn't already lowered
55455565 if (!BitTestCases[i].Emitted) {
5546 SelectionDAG HSDAG(TLI, MF, FuncInfo,
5547 getAnalysisToUpdate(),
5548 NodeAllocator);
5549 CurDAG = &HSDAG;
5550 SelectionDAGLowering HSDL(HSDAG, TLI, *AA, FuncInfo, GFI);
5566 SelectionDAGLowering HSDL(*CurDAG, TLI, *AA, FuncInfo, GFI);
55515567 // Set the current basic block to the mbb we wish to insert the code into
55525568 BB = BitTestCases[i].Parent;
55535569 HSDL.setCurrentBasicBlock(BB);
55545570 // Emit the code
55555571 HSDL.visitBitTestHeader(BitTestCases[i]);
5556 HSDAG.setRoot(HSDL.getRoot());
5557 CodeGenAndEmitDAG(HSDAG);
5572 CurDAG->setRoot(HSDL.getRoot());
5573 CodeGenAndEmitDAG();
5574 CurDAG->reset();
55585575 }
55595576
55605577 for (unsigned j = 0, ej = BitTestCases[i].Cases.size(); j != ej; ++j) {
5561 SelectionDAG BSDAG(TLI, MF, FuncInfo,
5562 getAnalysisToUpdate(),
5563 NodeAllocator);
5564 CurDAG = &BSDAG;
5565 SelectionDAGLowering BSDL(BSDAG, TLI, *AA, FuncInfo, GFI);
5578 SelectionDAGLowering BSDL(*CurDAG, TLI, *AA, FuncInfo, GFI);
55665579 // Set the current basic block to the mbb we wish to insert the code into
55675580 BB = BitTestCases[i].Cases[j].ThisBB;
55685581 BSDL.setCurrentBasicBlock(BB);
55775590 BitTestCases[i].Cases[j]);
55785591
55795592
5580 BSDAG.setRoot(BSDL.getRoot());
5581 CodeGenAndEmitDAG(BSDAG);
5593 CurDAG->setRoot(BSDL.getRoot());
5594 CodeGenAndEmitDAG();
5595 CurDAG->reset();
55825596 }
55835597
55845598 // Update PHI Nodes
56175631 for (unsigned i = 0, e = JTCases.size(); i != e; ++i) {
56185632 // Lower header first, if it wasn't already lowered
56195633 if (!JTCases[i].first.Emitted) {
5620 SelectionDAG HSDAG(TLI, MF, FuncInfo,
5621 getAnalysisToUpdate(),
5622 NodeAllocator);
5623 CurDAG = &HSDAG;
5624 SelectionDAGLowering HSDL(HSDAG, TLI, *AA, FuncInfo, GFI);
5634 SelectionDAGLowering HSDL(*CurDAG, TLI, *AA, FuncInfo, GFI);
56255635 // Set the current basic block to the mbb we wish to insert the code into
56265636 BB = JTCases[i].first.HeaderBB;
56275637 HSDL.setCurrentBasicBlock(BB);
56285638 // Emit the code
56295639 HSDL.visitJumpTableHeader(JTCases[i].second, JTCases[i].first);
5630 HSDAG.setRoot(HSDL.getRoot());
5631 CodeGenAndEmitDAG(HSDAG);
5632 }
5633
5634 SelectionDAG JSDAG(TLI, MF, FuncInfo,
5635 getAnalysisToUpdate(),
5636 NodeAllocator);
5637 CurDAG = &JSDAG;
5638 SelectionDAGLowering JSDL(JSDAG, TLI, *AA, FuncInfo, GFI);
5640 CurDAG->setRoot(HSDL.getRoot());
5641 CodeGenAndEmitDAG();
5642 CurDAG->reset();
5643 }
5644
5645 SelectionDAGLowering JSDL(*CurDAG, TLI, *AA, FuncInfo, GFI);
56395646 // Set the current basic block to the mbb we wish to insert the code into
56405647 BB = JTCases[i].second.MBB;
56415648 JSDL.setCurrentBasicBlock(BB);
56425649 // Emit the code
56435650 JSDL.visitJumpTable(JTCases[i].second);
5644 JSDAG.setRoot(JSDL.getRoot());
5645 CodeGenAndEmitDAG(JSDAG);
5651 CurDAG->setRoot(JSDL.getRoot());
5652 CodeGenAndEmitDAG();
5653 CurDAG->reset();
56465654
56475655 // Update PHI Nodes
56485656 for (unsigned pi = 0, pe = PHINodesToUpdate.size(); pi != pe; ++pi) {
56815689 // If we generated any switch lowering information, build and codegen any
56825690 // additional DAGs necessary.
56835691 for (unsigned i = 0, e = SwitchCases.size(); i != e; ++i) {
5684 SelectionDAG SDAG(TLI, MF, FuncInfo,
5685 getAnalysisToUpdate(),
5686 NodeAllocator);
5687 CurDAG = &SDAG;
5688 SelectionDAGLowering SDL(SDAG, TLI, *AA, FuncInfo, GFI);
5692 SelectionDAGLowering SDL(*CurDAG, TLI, *AA, FuncInfo, GFI);
56895693
56905694 // Set the current basic block to the mbb we wish to insert the code into
56915695 BB = SwitchCases[i].ThisBB;
56935697
56945698 // Emit the code
56955699 SDL.visitSwitchCase(SwitchCases[i]);
5696 SDAG.setRoot(SDL.getRoot());
5697 CodeGenAndEmitDAG(SDAG);
5700 CurDAG->setRoot(SDL.getRoot());
5701 CodeGenAndEmitDAG();
5702 CurDAG->reset();
56985703
56995704 // Handle any PHI nodes in successors of this chunk, as if we were coming
57005705 // from the original BB before switch expansion. Note that PHI nodes can
57315736 /// Schedule - Pick a safe ordering for instructions for each
57325737 /// target node in the graph.
57335738 ///
5734 ScheduleDAG *SelectionDAGISel::Schedule(SelectionDAG &DAG) {
5739 ScheduleDAG *SelectionDAGISel::Schedule() {
57355740 RegisterScheduler::FunctionPassCtor Ctor = RegisterScheduler::getDefault();
57365741
57375742 if (!Ctor) {
57395744 RegisterScheduler::setDefault(Ctor);
57405745 }
57415746
5742 ScheduleDAG *Scheduler = Ctor(this, &DAG, BB, Fast);
5747 ScheduleDAG *Scheduler = Ctor(this, CurDAG, BB, Fast);
57435748 Scheduler->Run();
57445749
57455750 return Scheduler;
58225827 /// SelectInlineAsmMemoryOperands - Calls to this are automatically generated
58235828 /// by tblgen. Others should not call it.
58245829 void SelectionDAGISel::
5825 SelectInlineAsmMemoryOperands(std::vector &Ops, SelectionDAG &DAG) {
5830 SelectInlineAsmMemoryOperands(std::vector &Ops) {
58265831 std::vector InOps;
58275832 std::swap(InOps, Ops);
58285833
58435848 assert((Flags >> 3) == 1 && "Memory operand with multiple values?");
58445849 // Otherwise, this is a memory operand. Ask the target to select it.
58455850 std::vector SelOps;
5846 if (SelectInlineAsmMemoryOperand(InOps[i+1], 'm', SelOps, DAG)) {
5851 if (SelectInlineAsmMemoryOperand(InOps[i+1], 'm', SelOps)) {
58475852 cerr << "Could not match memory address. Inline asm failure!\n";
58485853 exit(1);
58495854 }
58505855
58515856 // Add this to the output node.
5852 MVT IntPtrTy = DAG.getTargetLoweringInfo().getPointerTy();
5853 Ops.push_back(DAG.getTargetConstant(4/*MEM*/ | (SelOps.size() << 3),
5854 IntPtrTy));
5857 MVT IntPtrTy = CurDAG->getTargetLoweringInfo().getPointerTy();
5858 Ops.push_back(CurDAG->getTargetConstant(4/*MEM*/ | (SelOps.size() << 3),
5859 IntPtrTy));
58555860 Ops.insert(Ops.end(), SelOps.begin(), SelOps.end());
58565861 i += 2;
58575862 }
5353 }
5454
5555 SDNode *Select(SDValue Op);
56 virtual void InstructionSelect(SelectionDAG &DAG);
56 virtual void InstructionSelect();
5757 bool SelectAddrMode2(SDValue Op, SDValue N, SDValue &Base,
5858 SDValue &Offset, SDValue &Opc);
5959 bool SelectAddrMode2Offset(SDValue Op, SDValue N,
9090 };
9191 }
9292
93 void ARMDAGToDAGISel::InstructionSelect(SelectionDAG &DAG) {
93 void ARMDAGToDAGISel::InstructionSelect() {
9494 DEBUG(BB->dump());
9595
9696 SelectRoot();
97 DAG.RemoveDeadNodes();
97 CurDAG->RemoveDeadNodes();
9898 }
9999
100100 bool ARMDAGToDAGISel::SelectAddrMode2(SDValue Op, SDValue N,
162162
163163 /// InstructionSelect - This callback is invoked by
164164 /// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
165 virtual void InstructionSelect(SelectionDAG &DAG);
165 virtual void InstructionSelect();
166166
167167 virtual const char *getPassName() const {
168168 return "Alpha DAG->DAG Pattern Instruction Selection";
172172 /// inline asm expressions.
173173 virtual bool SelectInlineAsmMemoryOperand(const SDValue &Op,
174174 char ConstraintCode,
175 std::vector &OutOps,
176 SelectionDAG &DAG) {
175 std::vector &OutOps) {
177176 SDValue Op0;
178177 switch (ConstraintCode) {
179178 default: return true;
231230
232231 /// InstructionSelect - This callback is invoked by
233232 /// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
234 void AlphaDAGToDAGISel::InstructionSelect(SelectionDAG &DAG) {
233 void AlphaDAGToDAGISel::InstructionSelect() {
235234 DEBUG(BB->dump());
236235
237236 // Select target instructions for the DAG.
238237 SelectRoot();
239 DAG.RemoveDeadNodes();
238 CurDAG->RemoveDeadNodes();
240239 }
241240
242241 // Select - Convert the specified operand from a target-independent to a
284284 /// inline asm expressions.
285285 virtual bool SelectInlineAsmMemoryOperand(const SDValue &Op,
286286 char ConstraintCode,
287 std::vector &OutOps,
288 SelectionDAG &DAG) {
287 std::vector &OutOps) {
289288 SDValue Op0, Op1;
290289 switch (ConstraintCode) {
291290 default: return true;
318317
319318 /// InstructionSelect - This callback is invoked by
320319 /// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
321 virtual void InstructionSelect(SelectionDAG &DAG);
320 virtual void InstructionSelect();
322321
323322 virtual const char *getPassName() const {
324323 return "Cell SPU DAG->DAG Pattern Instruction Selection";
341340 /// InstructionSelect - This callback is invoked by
342341 /// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
343342 void
344 SPUDAGToDAGISel::InstructionSelect(SelectionDAG &DAG)
343 SPUDAGToDAGISel::InstructionSelect()
345344 {
346345 DEBUG(BB->dump());
347346
348347 // Select target instructions for the DAG.
349348 SelectRoot();
350 DAG.RemoveDeadNodes();
349 CurDAG->RemoveDeadNodes();
351350 }
352351
353352 /*!
7979
8080 /// InstructionSelect - This callback is invoked by
8181 /// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
82 virtual void InstructionSelect(SelectionDAG &DAG);
82 virtual void InstructionSelect();
8383
8484 virtual const char *getPassName() const {
8585 return "IA64 (Itanium) DAG->DAG Instruction Selector";
9595
9696 /// InstructionSelect - This callback is invoked by
9797 /// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
98 void IA64DAGToDAGISel::InstructionSelect(SelectionDAG &DAG) {
98 void IA64DAGToDAGISel::InstructionSelect() {
9999 DEBUG(BB->dump());
100100
101101 // Select target instructions for the DAG.
102102 SelectRoot();
103 DAG.RemoveDeadNodes();
103 CurDAG->RemoveDeadNodes();
104104 }
105105
106106 SDNode *IA64DAGToDAGISel::SelectDIV(SDValue Op) {
6565 TM(tm), MipsLowering(*TM.getTargetLowering()),
6666 Subtarget(tm.getSubtarget()) {}
6767
68 virtual void InstructionSelect(SelectionDAG &SD);
68 virtual void InstructionSelect();
6969
7070 // Pass Name
7171 virtual const char *getPassName() const {
102102 /// InstructionSelect - This callback is invoked by
103103 /// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
104104 void MipsDAGToDAGISel::
105 InstructionSelect(SelectionDAG &SD)
105 InstructionSelect()
106106 {
107107 DEBUG(BB->dump());
108108 // Codegen the basic block.
118118 DOUT << "===== Instruction selection ends:\n";
119119 #endif
120120
121 SD.RemoveDeadNodes();
121 CurDAG->RemoveDeadNodes();
122122 }
123123
124124 /// getGlobalBaseReg - Output the instructions required to put the
5959 SelectionDAGISel(PIC16Lowering),
6060 TM(tm), PIC16Lowering(*TM.getTargetLowering()) {}
6161
62 virtual void InstructionSelect(SelectionDAG &SD);
62 virtual void InstructionSelect();
6363
6464 // Pass Name
6565 virtual const char *getPassName() const {
9797
9898 /// InstructionSelect - This callback is invoked by
9999 /// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
100 void PIC16DAGToDAGISel::InstructionSelect(SelectionDAG &SD)
100 void PIC16DAGToDAGISel::InstructionSelect()
101101 {
102102 DEBUG(BB->dump());
103103 // Codegen the basic block.
112112
113113 DOUT << "===== Instruction selection ends:\n";
114114
115 SD.RemoveDeadNodes();
115 CurDAG->RemoveDeadNodes();
116116 }
117117
118118
143143 /// inline asm expressions.
144144 virtual bool SelectInlineAsmMemoryOperand(const SDValue &Op,
145145 char ConstraintCode,
146 std::vector &OutOps,
147 SelectionDAG &DAG) {
146 std::vector &OutOps) {
148147 SDValue Op0, Op1;
149148 switch (ConstraintCode) {
150149 default: return true;
174173
175174 /// InstructionSelect - This callback is invoked by
176175 /// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
177 virtual void InstructionSelect(SelectionDAG &DAG);
176 virtual void InstructionSelect();
178177
179178 void InsertVRSaveCode(Function &Fn);
180179
202201
203202 /// InstructionSelect - This callback is invoked by
204203 /// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
205 void PPCDAGToDAGISel::InstructionSelect(SelectionDAG &DAG) {
204 void PPCDAGToDAGISel::InstructionSelect() {
206205 DEBUG(BB->dump());
207206
208207 // Select target instructions for the DAG.
209208 SelectRoot();
210 DAG.RemoveDeadNodes();
209 CurDAG->RemoveDeadNodes();
211210 }
212211
213212 /// InsertVRSaveCode - Once the entire function has been instruction selected,
4848
4949 /// InstructionSelect - This callback is invoked by
5050 /// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
51 virtual void InstructionSelect(SelectionDAG &DAG);
51 virtual void InstructionSelect();
5252
5353 virtual const char *getPassName() const {
5454 return "SPARC DAG->DAG Pattern Instruction Selection";
6161
6262 /// InstructionSelect - This callback is invoked by
6363 /// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
64 void SparcDAGToDAGISel::InstructionSelect(SelectionDAG &DAG) {
64 void SparcDAGToDAGISel::InstructionSelect() {
6565 DEBUG(BB->dump());
6666
6767 // Select target instructions for the DAG.
6868 SelectRoot();
69 DAG.RemoveDeadNodes();
69 CurDAG->RemoveDeadNodes();
7070 }
7171
7272 bool SparcDAGToDAGISel::SelectADDRri(SDValue Op, SDValue Addr,
146146
147147 /// InstructionSelect - This callback is invoked by
148148 /// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
149 virtual void InstructionSelect(SelectionDAG &DAG);
149 virtual void InstructionSelect();
150150
151151 /// InstructionSelectPostProcessing - Post processing of selected and
152152 /// scheduled basic blocks.
177177 bool TryFoldLoad(SDValue P, SDValue N,
178178 SDValue &Base, SDValue &Scale,
179179 SDValue &Index, SDValue &Disp);
180 void PreprocessForRMW(SelectionDAG &DAG);
181 void PreprocessForFPConvert(SelectionDAG &DAG);
180 void PreprocessForRMW();
181 void PreprocessForFPConvert();
182182
183183 /// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
184184 /// inline asm expressions.
185185 virtual bool SelectInlineAsmMemoryOperand(const SDValue &Op,
186186 char ConstraintCode,
187 std::vector &OutOps,
188 SelectionDAG &DAG);
187 std::vector &OutOps);
189188
190189 void EmitSpecialCodeForMain(MachineBasicBlock *BB, MachineFrameInfo *MFI);
191190
371370 /// MoveBelowTokenFactor - Replace TokenFactor operand with load's chain operand
372371 /// and move load below the TokenFactor. Replace store's chain operand with
373372 /// load's chain result.
374 static void MoveBelowTokenFactor(SelectionDAG &DAG, SDValue Load,
373 static void MoveBelowTokenFactor(SelectionDAG *CurDAG, SDValue Load,
375374 SDValue Store, SDValue TF) {
376375 std::vector Ops;
377376 for (unsigned i = 0, e = TF.Val->getNumOperands(); i != e; ++i)
379378 Ops.push_back(Load.Val->getOperand(0));
380379 else
381380 Ops.push_back(TF.Val->getOperand(i));
382 DAG.UpdateNodeOperands(TF, &Ops[0], Ops.size());
383 DAG.UpdateNodeOperands(Load, TF, Load.getOperand(1), Load.getOperand(2));
384 DAG.UpdateNodeOperands(Store, Load.getValue(1), Store.getOperand(1),
385 Store.getOperand(2), Store.getOperand(3));
381 CurDAG->UpdateNodeOperands(TF, &Ops[0], Ops.size());
382 CurDAG->UpdateNodeOperands(Load, TF, Load.getOperand(1), Load.getOperand(2));
383 CurDAG->UpdateNodeOperands(Store, Load.getValue(1), Store.getOperand(1),
384 Store.getOperand(2), Store.getOperand(3));
386385 }
387386
388387 /// isRMWLoad - Return true if N is a load that's part of RMW sub-DAG.
451450 /// \ /
452451 /// \ /
453452 /// [Store]
454 void X86DAGToDAGISel::PreprocessForRMW(SelectionDAG &DAG) {
455 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(),
456 E = DAG.allnodes_end(); I != E; ++I) {
453 void X86DAGToDAGISel::PreprocessForRMW() {
454 for (SelectionDAG::allnodes_iterator I = CurDAG->allnodes_begin(),
455 E = CurDAG->allnodes_end(); I != E; ++I) {
457456 if (!ISD::isNON_TRUNCStore(I))
458457 continue;
459458 SDValue Chain = I->getOperand(0);
503502 }
504503
505504 if (RModW) {
506 MoveBelowTokenFactor(DAG, Load, SDValue(I, 0), Chain);
505 MoveBelowTokenFactor(CurDAG, Load, SDValue(I, 0), Chain);
507506 ++NumLoadMoved;
508507 }
509508 }
518517 /// hack on these between the call expansion and the node legalization. As such
519518 /// this pass basically does "really late" legalization of these inline with the
520519 /// X86 isel pass.
521 void X86DAGToDAGISel::PreprocessForFPConvert(SelectionDAG &DAG) {
522 for (SelectionDAG::allnodes_iterator I = DAG.allnodes_begin(),
523 E = DAG.allnodes_end(); I != E; ) {
520 void X86DAGToDAGISel::PreprocessForFPConvert() {
521 for (SelectionDAG::allnodes_iterator I = CurDAG->allnodes_begin(),
522 E = CurDAG->allnodes_end(); I != E; ) {
524523 SDNode *N = I++; // Preincrement iterator to avoid invalidation issues.
525524 if (N->getOpcode() != ISD::FP_ROUND && N->getOpcode() != ISD::FP_EXTEND)
526525 continue;
552551 else
553552 MemVT = SrcIsSSE ? SrcVT : DstVT;
554553
555 SDValue MemTmp = DAG.CreateStackTemporary(MemVT);
554 SDValue MemTmp = CurDAG->CreateStackTemporary(MemVT);
556555
557556 // FIXME: optimize the case where the src/dest is a load or store?
558 SDValue Store = DAG.getTruncStore(DAG.getEntryNode(), N->getOperand(0),
559 MemTmp, NULL, 0, MemVT);
560 SDValue Result = DAG.getExtLoad(ISD::EXTLOAD, DstVT, Store, MemTmp,
561 NULL, 0, MemVT);
557 SDValue Store = CurDAG->getTruncStore(CurDAG->getEntryNode(),
558 N->getOperand(0),
559 MemTmp, NULL, 0, MemVT);
560 SDValue Result = CurDAG->getExtLoad(ISD::EXTLOAD, DstVT, Store, MemTmp,
561 NULL, 0, MemVT);
562562
563563 // We're about to replace all uses of the FP_ROUND/FP_EXTEND with the
564564 // extload we created. This will cause general havok on the dag because
565565 // anything below the conversion could be folded into other existing nodes.
566566 // To avoid invalidating 'I', back it up to the convert node.
567567 --I;
568 DAG.ReplaceAllUsesOfValueWith(SDValue(N, 0), Result);
568 CurDAG->ReplaceAllUsesOfValueWith(SDValue(N, 0), Result);
569569
570570 // Now that we did that, the node is dead. Increment the iterator to the
571571 // next node to process, then delete N.
572572 ++I;
573 DAG.DeleteNode(N);
573 CurDAG->DeleteNode(N);
574574 }
575575 }
576576
577577 /// InstructionSelectBasicBlock - This callback is invoked by SelectionDAGISel
578578 /// when it has created a SelectionDAG for us to codegen.
579 void X86DAGToDAGISel::InstructionSelect(SelectionDAG &DAG) {
579 void X86DAGToDAGISel::InstructionSelect() {
580580 CurBB = BB; // BB can change as result of isel.
581581
582582 DEBUG(BB->dump());
583583 if (!Fast)
584 PreprocessForRMW(DAG);
584 PreprocessForRMW();
585585
586586 // FIXME: This should only happen when not -fast.
587 PreprocessForFPConvert(DAG);
587 PreprocessForFPConvert();
588588
589589 // Codegen the basic block.
590590 #ifndef NDEBUG
596596 DOUT << "===== Instruction selection ends:\n";
597597 #endif
598598
599 DAG.RemoveDeadNodes();
599 CurDAG->RemoveDeadNodes();
600600 }
601601
602602 void X86DAGToDAGISel::InstructionSelectPostProcessing() {
15981598
15991599 bool X86DAGToDAGISel::
16001600 SelectInlineAsmMemoryOperand(const SDValue &Op, char ConstraintCode,
1601 std::vector &OutOps, SelectionDAG &DAG){
1601 std::vector &OutOps) {
16021602 SDValue Op0, Op1, Op2, Op3;
16031603 switch (ConstraintCode) {
16041604 case 'o': // offsetable ??
18631863 // Emit boilerplate.
18641864 OS << "SDNode *Select_INLINEASM(SDValue N) {\n"
18651865 << " std::vector Ops(N.Val->op_begin(), N.Val->op_end());\n"
1866 << " SelectInlineAsmMemoryOperands(Ops, *CurDAG);\n\n"
1866 << " SelectInlineAsmMemoryOperands(Ops);\n\n"
18671867
18681868 << " // Ensure that the asm operands are themselves selected.\n"
18691869 << " for (unsigned j = 0, e = Ops.size(); j != e; ++j)\n"