llvm.org GIT mirror llvm / f31408d
Disable the register+memory forms of the bt instructions for now. Thanks to Eli for pointing out that these forms don't ignore the high bits of their index operands, and as such are not immediately suitable for use by isel. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62194 91177308-0d34-0410-b5e6-96231b3b80d8 Dan Gohman 11 years ago
3 changed file(s) with 26 addition(s) and 13 deletion(s). Raw diff Collapse all Expand all
923923 "bt{q}\t{$src2, $src1|$src1, $src2}",
924924 [(X86bt GR64:$src1, GR64:$src2),
925925 (implicit EFLAGS)]>, TB;
926 def BT64mr : RI<0xA3, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2),
927 "bt{q}\t{$src2, $src1|$src1, $src2}",
928 [(X86bt (loadi64 addr:$src1), GR64:$src2),
929 (implicit EFLAGS)]>, TB;
926
927 // Unlike with the register+register form, the memory+register form of the
928 // bt instruction does not ignore the high bits of the index. From ISel's
929 // perspective, this is pretty bizarre. Disable these instructions for now.
930 //def BT64mr : RI<0xA3, MRMDestMem, (outs), (ins i64mem:$src1, GR64:$src2),
931 // "bt{q}\t{$src2, $src1|$src1, $src2}",
932 // [(X86bt (loadi64 addr:$src1), GR64:$src2),
933 // (implicit EFLAGS)]>, TB;
930934
931935 def BT64ri8 : Ii8<0xBA, MRM4r, (outs), (ins GR64:$src1, i64i8imm:$src2),
932936 "bt{q}\t{$src2, $src1|$src1, $src2}",
26812681 "bt{l}\t{$src2, $src1|$src1, $src2}",
26822682 [(X86bt GR32:$src1, GR32:$src2),
26832683 (implicit EFLAGS)]>, TB;
2684 def BT16mr : I<0xA3, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2),
2685 "bt{w}\t{$src2, $src1|$src1, $src2}",
2686 [(X86bt (loadi16 addr:$src1), GR16:$src2),
2687 (implicit EFLAGS)]>, OpSize, TB, Requires<[FastBTMem]>;
2688 def BT32mr : I<0xA3, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2),
2689 "bt{l}\t{$src2, $src1|$src1, $src2}",
2690 [(X86bt (loadi32 addr:$src1), GR32:$src2),
2691 (implicit EFLAGS)]>, TB, Requires<[FastBTMem]>;
2684
2685 // Unlike with the register+register form, the memory+register form of the
2686 // bt instruction does not ignore the high bits of the index. From ISel's
2687 // perspective, this is pretty bizarre. Disable these instructions for now.
2688 //def BT16mr : I<0xA3, MRMDestMem, (outs), (ins i16mem:$src1, GR16:$src2),
2689 // "bt{w}\t{$src2, $src1|$src1, $src2}",
2690 // [(X86bt (loadi16 addr:$src1), GR16:$src2),
2691 // (implicit EFLAGS)]>, OpSize, TB, Requires<[FastBTMem]>;
2692 //def BT32mr : I<0xA3, MRMDestMem, (outs), (ins i32mem:$src1, GR32:$src2),
2693 // "bt{l}\t{$src2, $src1|$src1, $src2}",
2694 // [(X86bt (loadi32 addr:$src1), GR32:$src2),
2695 // (implicit EFLAGS)]>, TB, Requires<[FastBTMem]>;
26922696
26932697 def BT16ri8 : Ii8<0xBA, MRM4r, (outs), (ins GR16:$src1, i16i8imm:$src2),
26942698 "bt{w}\t{$src2, $src1|$src1, $src2}",
0 ; RUN: llvm-as < %s | llc | grep btl
1 ; RUN: llvm-as < %s | llc -mcpu=pentium4 | grep btl | grep esp
1 ; RUN: llvm-as < %s | llc -mcpu=pentium4 | grep btl | not grep esp
22 ; RUN: llvm-as < %s | llc -mcpu=penryn | grep btl | not grep esp
33 ; PR3253
4
5 ; The register+memory form of the BT instruction should be usable on
6 ; pentium4, however it is currently disabled due to the register+memory
7 ; form having different semantics than the register+register form.
8
49 target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:32:64-f32:32:32-f64:32:64-v64:64:64-v128:128:128-a0:0:64-f80:128:128"
510 target triple = "i386-apple-darwin8"
611