llvm.org GIT mirror llvm / f30ce39
Revert "[DAGCombine] Move AND nodes to multiple load leaves" This reverts commit r320679. Causes miscompiles. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@320698 91177308-0d34-0410-b5e6-96231b3b80d8 Benjamin Kramer 2 years ago
2 changed file(s) with 635 addition(s) and 701 deletion(s). Raw diff Collapse all Expand all
503503 /// width reduced to ExtVT.
504504 bool isLegalNarrowLoad(LoadSDNode *LoadN, ISD::LoadExtType ExtType,
505505 EVT &ExtVT, unsigned ShAmt = 0);
506
507 /// Used by BackwardsPropagateMask to find suitable loads.
508 bool SearchForAndLoads(SDNode *N, SmallPtrSetImpl &Loads,
509 ConstantSDNode *Mask, SDNode *&UncombinedNode);
510 /// Attempt to propagate a given AND node back to load leaves so that they
511 /// can be combined into narrow loads.
512 bool BackwardsPropagateMask(SDNode *N, SelectionDAG &DAG);
513506
514507 /// Helper function for MergeConsecutiveStores which merges the
515508 /// component store chains.
38043797 return true;
38053798 }
38063799
3807 bool DAGCombiner::SearchForAndLoads(SDNode *N,
3808 SmallPtrSetImpl &Loads,
3809 ConstantSDNode *Mask,
3810 SDNode *&NodeToMask) {
3811 // Recursively search for the operands, looking for loads which can be
3812 // narrowed.
3813 for (unsigned i = 0, e = N->getNumOperands(); i < e; ++i) {
3814 SDValue Op = N->getOperand(i);
3815
3816 // Constants should already be fixed up...
3817 if (isa(Op))
3818 continue;
3819
3820 if (!Op.hasOneUse() || Op.getValueType().isVector())
3821 return false;
3822
3823 switch(Op.getOpcode()) {
3824 case ISD::LOAD: {
3825 auto *Load = cast(Op);
3826 EVT ExtVT;
3827 if (isAndLoadExtLoad(Mask, Load, Load->getValueType(0), ExtVT) &&
3828 isLegalNarrowLoad(Load, ISD::ZEXTLOAD, ExtVT)) {
3829 // Only add this load if we can make it more narrow.
3830 if (ExtVT.bitsLT(Load->getMemoryVT()))
3831 Loads.insert(Load);
3832 continue;
3833 }
3834 return false;
3835 }
3836 case ISD::ZERO_EXTEND:
3837 case ISD::ANY_EXTEND:
3838 case ISD::AssertZext: {
3839 unsigned ActiveBits = Mask->getAPIntValue().countTrailingOnes();
3840 EVT ExtVT = EVT::getIntegerVT(*DAG.getContext(), ActiveBits);
3841 EVT VT = Op.getOpcode() == ISD::AssertZext ?
3842 cast(Op.getOperand(1))->getVT() :
3843 Op.getOperand(0).getValueType();
3844
3845 // We can accept extending nodes if the mask is wider or an equal
3846 // width to the original type.
3847 if (ExtVT.bitsGE(VT))
3848 continue;
3849 break;
3850 }
3851 case ISD::OR:
3852 case ISD::XOR:
3853 case ISD::AND:
3854 if (!SearchForAndLoads(Op.getNode(), Loads, Mask, NodeToMask))
3855 return false;
3856 continue;
3857 }
3858
3859 // Allow one node which will masked along with any loads found.
3860 if (NodeToMask)
3861 return false;
3862 NodeToMask = Op.getNode();
3863 }
3864 return true;
3865 }
3866
3867 bool DAGCombiner::BackwardsPropagateMask(SDNode *N, SelectionDAG &DAG) {
3868 auto *Mask = dyn_cast(N->getOperand(1));
3869 if (!Mask)
3870 return false;
3871
3872 if (!Mask->getAPIntValue().isMask())
3873 return false;
3874
3875 // No need to do anything if the and directly uses a load.
3876 if (isa(N->getOperand(0)))
3877 return false;
3878
3879 SmallPtrSet Loads;
3880 SDNode *FixupNode = nullptr;
3881 if (SearchForAndLoads(N, Loads, Mask, FixupNode)) {
3882 if (Loads.size() == 0)
3883 return false;
3884
3885 SDValue MaskOp = N->getOperand(1);
3886
3887 // If it exists, fixup the single node we allow in the tree that needs
3888 // masking.
3889 if (FixupNode) {
3890 SDValue And = DAG.getNode(ISD::AND, SDLoc(FixupNode),
3891 FixupNode->getValueType(0),
3892 SDValue(FixupNode, 0), MaskOp);
3893 DAG.ReplaceAllUsesOfValueWith(SDValue(FixupNode, 0), And);
3894 DAG.UpdateNodeOperands(And.getNode(), SDValue(FixupNode, 0),
3895 MaskOp);
3896 }
3897
3898 for (auto *Load : Loads) {
3899 SDValue And = DAG.getNode(ISD::AND, SDLoc(Load), Load->getValueType(0),
3900 SDValue(Load, 0), MaskOp);
3901 DAG.ReplaceAllUsesOfValueWith(SDValue(Load, 0), And);
3902 DAG.UpdateNodeOperands(And.getNode(), SDValue(Load, 0), MaskOp);
3903 SDValue NewLoad = ReduceLoadWidth(And.getNode());
3904 assert(NewLoad &&
3905 "Shouldn't be masking the load if it can't be narrowed");
3906 CombineTo(Load, NewLoad, NewLoad.getValue(1));
3907 }
3908 DAG.ReplaceAllUsesWith(N, N->getOperand(0).getNode());
3909 return true;
3910 }
3911 return false;
3912 }
3913
39143800 SDValue DAGCombiner::visitAND(SDNode *N) {
39153801 SDValue N0 = N->getOperand(0);
39163802 SDValue N1 = N->getOperand(1);
41083994
41093995 AddToWorklist(N);
41103996 CombineTo(LN0, Res, Res.getValue(1));
4111 return SDValue(N, 0);
4112 }
4113 }
4114
4115 if (Level >= AfterLegalizeTypes) {
4116 // Attempt to propagate the AND back up to the leaves which, if they're
4117 // loads, can be combined to narrow loads and the AND node can be removed.
4118 // Perform after legalization so that extend nodes will already be
4119 // combined into the loads.
4120 if (BackwardsPropagateMask(N, DAG)) {
41213997 return SDValue(N, 0);
41223998 }
41233999 }
44 ; RUN: llc -mtriple=thumbv8m.main %s -o - | FileCheck %s --check-prefix=THUMB2
55
66 define arm_aapcscc zeroext i1 @cmp_xor8_short_short(i16* nocapture readonly %a,
7 ; ARM-LABEL: cmp_xor8_short_short:
8 ; ARM: @ %bb.0: @ %entry
9 ; ARM-NEXT: ldrh r0, [r0]
10 ; ARM-NEXT: ldrh r1, [r1]
11 ; ARM-NEXT: eor r1, r1, r0
12 ; ARM-NEXT: mov r0, #0
13 ; ARM-NEXT: tst r1, #255
14 ; ARM-NEXT: movweq r0, #1
15 ; ARM-NEXT: bx lr
16 ;
17 ; ARMEB-LABEL: cmp_xor8_short_short:
18 ; ARMEB: @ %bb.0: @ %entry
19 ; ARMEB-NEXT: ldrh r0, [r0]
20 ; ARMEB-NEXT: ldrh r1, [r1]
21 ; ARMEB-NEXT: eor r1, r1, r0
22 ; ARMEB-NEXT: mov r0, #0
23 ; ARMEB-NEXT: tst r1, #255
24 ; ARMEB-NEXT: movweq r0, #1
25 ; ARMEB-NEXT: bx lr
26 ;
27 ; THUMB1-LABEL: cmp_xor8_short_short:
28 ; THUMB1: @ %bb.0: @ %entry
29 ; THUMB1-NEXT: ldrh r0, [r0]
30 ; THUMB1-NEXT: ldrh r2, [r1]
31 ; THUMB1-NEXT: eors r2, r0
32 ; THUMB1-NEXT: movs r0, #1
33 ; THUMB1-NEXT: movs r1, #0
34 ; THUMB1-NEXT: lsls r2, r2, #24
35 ; THUMB1-NEXT: beq .LBB0_2
36 ; THUMB1-NEXT: @ %bb.1: @ %entry
37 ; THUMB1-NEXT: mov r0, r1
38 ; THUMB1-NEXT: .LBB0_2: @ %entry
39 ; THUMB1-NEXT: bx lr
40 ;
41 ; THUMB2-LABEL: cmp_xor8_short_short:
42 ; THUMB2: @ %bb.0: @ %entry
43 ; THUMB2-NEXT: ldrh r0, [r0]
44 ; THUMB2-NEXT: ldrh r1, [r1]
45 ; THUMB2-NEXT: eors r0, r1
46 ; THUMB2-NEXT: lsls r0, r0, #24
47 ; THUMB2-NEXT: mov.w r0, #0
48 ; THUMB2-NEXT: it eq
49 ; THUMB2-NEXT: moveq r0, #1
50 ; THUMB2-NEXT: bx lr
751 i16* nocapture readonly %b) {
8 ; ARM-LABEL: cmp_xor8_short_short:
9 ; ARM: ldrb r2, [r0]
10 ; ARM-NEXT: mov r0, #0
11 ; ARM-NEXT: ldrb r1, [r1]
12 ; ARM-NEXT: teq r1, r2
13 ; ARM-NEXT: movweq r0, #1
14 ; ARM-NEXT: bx lr
15 ;
16 ; ARMEB-LABEL: cmp_xor8_short_short:
17 ; ARMEB: ldrb r2, [r0, #1]
18 ; ARMEB-NEXT: mov r0, #0
19 ; ARMEB-NEXT: ldrb r1, [r1, #1]
20 ; ARMEB-NEXT: teq r1, r2
21 ; ARMEB-NEXT: movweq r0, #1
22 ; ARMEB-NEXT: bx lr
23 ;
24 ; THUMB1-LABEL: cmp_xor8_short_short:
25 ; THUMB1: ldrb r0, [r0]
26 ; THUMB1-NEXT: ldrb r2, [r1]
27 ; THUMB1-NEXT: eors r2, r0
28 ; THUMB1-NEXT: movs r0, #1
29 ; THUMB1-NEXT: movs r1, #0
30 ; THUMB1-NEXT: cmp r2, #0
31 ; THUMB1-NEXT: beq .LBB0_2
32 ; THUMB1-NEXT: @ %bb.1: @ %entry
33 ; THUMB1-NEXT: mov r0, r1
34 ; THUMB1-NEXT: .LBB0_2: @ %entry
35 ; THUMB1-NEXT: bx lr
36 ;
37 ; THUMB2-LABEL: cmp_xor8_short_short:
38 ; THUMB2: ldrb r2, [r0]
39 ; THUMB2-NEXT: movs r0, #0
40 ; THUMB2-NEXT: ldrb r1, [r1]
41 ; THUMB2-NEXT: teq.w r1, r2
42 ; THUMB2-NEXT: it eq
43 ; THUMB2-NEXT: moveq r0, #1
44 ; THUMB2-NEXT: bx lr
4552 entry:
4653 %0 = load i16, i16* %a, align 2
4754 %1 = load i16, i16* %b, align 2
5259 }
5360
5461 define arm_aapcscc zeroext i1 @cmp_xor8_short_int(i16* nocapture readonly %a,
62 ; ARM-LABEL: cmp_xor8_short_int:
63 ; ARM: @ %bb.0: @ %entry
64 ; ARM-NEXT: ldrh r0, [r0]
65 ; ARM-NEXT: ldr r1, [r1]
66 ; ARM-NEXT: eor r1, r1, r0
67 ; ARM-NEXT: mov r0, #0
68 ; ARM-NEXT: tst r1, #255
69 ; ARM-NEXT: movweq r0, #1
70 ; ARM-NEXT: bx lr
71 ;
72 ; ARMEB-LABEL: cmp_xor8_short_int:
73 ; ARMEB: @ %bb.0: @ %entry
74 ; ARMEB-NEXT: ldrh r0, [r0]
75 ; ARMEB-NEXT: ldr r1, [r1]
76 ; ARMEB-NEXT: eor r1, r1, r0
77 ; ARMEB-NEXT: mov r0, #0
78 ; ARMEB-NEXT: tst r1, #255
79 ; ARMEB-NEXT: movweq r0, #1
80 ; ARMEB-NEXT: bx lr
81 ;
82 ; THUMB1-LABEL: cmp_xor8_short_int:
83 ; THUMB1: @ %bb.0: @ %entry
84 ; THUMB1-NEXT: ldrh r0, [r0]
85 ; THUMB1-NEXT: ldr r2, [r1]
86 ; THUMB1-NEXT: eors r2, r0
87 ; THUMB1-NEXT: movs r0, #1
88 ; THUMB1-NEXT: movs r1, #0
89 ; THUMB1-NEXT: lsls r2, r2, #24
90 ; THUMB1-NEXT: beq .LBB1_2
91 ; THUMB1-NEXT: @ %bb.1: @ %entry
92 ; THUMB1-NEXT: mov r0, r1
93 ; THUMB1-NEXT: .LBB1_2: @ %entry
94 ; THUMB1-NEXT: bx lr
95 ;
96 ; THUMB2-LABEL: cmp_xor8_short_int:
97 ; THUMB2: @ %bb.0: @ %entry
98 ; THUMB2-NEXT: ldrh r0, [r0]
99 ; THUMB2-NEXT: ldr r1, [r1]
100 ; THUMB2-NEXT: eors r0, r1
101 ; THUMB2-NEXT: lsls r0, r0, #24
102 ; THUMB2-NEXT: mov.w r0, #0
103 ; THUMB2-NEXT: it eq
104 ; THUMB2-NEXT: moveq r0, #1
105 ; THUMB2-NEXT: bx lr
55106 i32* nocapture readonly %b) {
56 ; ARM-LABEL: cmp_xor8_short_int:
57 ; ARM: ldrb r2, [r0]
58 ; ARM-NEXT: mov r0, #0
59 ; ARM-NEXT: ldrb r1, [r1]
60 ; ARM-NEXT: teq r1, r2
61 ; ARM-NEXT: movweq r0, #1
62 ; ARM-NEXT: bx lr
63 ;
64 ; ARMEB-LABEL: cmp_xor8_short_int:
65 ; ARMEB: ldrb r2, [r0, #1]
66 ; ARMEB-NEXT: mov r0, #0
67 ; ARMEB-NEXT: ldrb r1, [r1, #3]
68 ; ARMEB-NEXT: teq r1, r2
69 ; ARMEB-NEXT: movweq r0, #1
70 ; ARMEB-NEXT: bx lr
71 ;
72 ; THUMB1-LABEL: cmp_xor8_short_int:
73 ; THUMB1: ldrb r0, [r0]
74 ; THUMB1-NEXT: ldrb r2, [r1]
75 ; THUMB1-NEXT: eors r2, r0
76 ; THUMB1-NEXT: movs r0, #1
77 ; THUMB1-NEXT: movs r1, #0
78 ; THUMB1-NEXT: cmp r2, #0
79 ; THUMB1-NEXT: beq .LBB1_2
80 ; THUMB1-NEXT: @ %bb.1: @ %entry
81 ; THUMB1-NEXT: mov r0, r1
82 ; THUMB1-NEXT: .LBB1_2: @ %entry
83 ; THUMB1-NEXT: bx lr
84 ;
85 ; THUMB2-LABEL: cmp_xor8_short_int:
86 ; THUMB2: ldrb r2, [r0]
87 ; THUMB2-NEXT: movs r0, #0
88 ; THUMB2-NEXT: ldrb r1, [r1]
89 ; THUMB2-NEXT: teq.w r1, r2
90 ; THUMB2-NEXT: it eq
91 ; THUMB2-NEXT: moveq r0, #1
92 ; THUMB2-NEXT: bx lr
93107 entry:
94108 %0 = load i16, i16* %a, align 2
95109 %conv = zext i16 %0 to i32
101115 }
102116
103117 define arm_aapcscc zeroext i1 @cmp_xor8_int_int(i32* nocapture readonly %a,
118 ; ARM-LABEL: cmp_xor8_int_int:
119 ; ARM: @ %bb.0: @ %entry
120 ; ARM-NEXT: ldr r0, [r0]
121 ; ARM-NEXT: ldr r1, [r1]
122 ; ARM-NEXT: eor r1, r1, r0
123 ; ARM-NEXT: mov r0, #0
124 ; ARM-NEXT: tst r1, #255
125 ; ARM-NEXT: movweq r0, #1
126 ; ARM-NEXT: bx lr
127 ;
128 ; ARMEB-LABEL: cmp_xor8_int_int:
129 ; ARMEB: @ %bb.0: @ %entry
130 ; ARMEB-NEXT: ldr r0, [r0]
131 ; ARMEB-NEXT: ldr r1, [r1]
132 ; ARMEB-NEXT: eor r1, r1, r0
133 ; ARMEB-NEXT: mov r0, #0
134 ; ARMEB-NEXT: tst r1, #255
135 ; ARMEB-NEXT: movweq r0, #1
136 ; ARMEB-NEXT: bx lr
137 ;
138 ; THUMB1-LABEL: cmp_xor8_int_int:
139 ; THUMB1: @ %bb.0: @ %entry
140 ; THUMB1-NEXT: ldr r0, [r0]
141 ; THUMB1-NEXT: ldr r2, [r1]
142 ; THUMB1-NEXT: eors r2, r0
143 ; THUMB1-NEXT: movs r0, #1
144 ; THUMB1-NEXT: movs r1, #0
145 ; THUMB1-NEXT: lsls r2, r2, #24
146 ; THUMB1-NEXT: beq .LBB2_2
147 ; THUMB1-NEXT: @ %bb.1: @ %entry
148 ; THUMB1-NEXT: mov r0, r1
149 ; THUMB1-NEXT: .LBB2_2: @ %entry
150 ; THUMB1-NEXT: bx lr
151 ;
152 ; THUMB2-LABEL: cmp_xor8_int_int:
153 ; THUMB2: @ %bb.0: @ %entry
154 ; THUMB2-NEXT: ldr r0, [r0]
155 ; THUMB2-NEXT: ldr r1, [r1]
156 ; THUMB2-NEXT: eors r0, r1
157 ; THUMB2-NEXT: lsls r0, r0, #24
158 ; THUMB2-NEXT: mov.w r0, #0
159 ; THUMB2-NEXT: it eq
160 ; THUMB2-NEXT: moveq r0, #1
161 ; THUMB2-NEXT: bx lr
104162 i32* nocapture readonly %b) {
105 ; ARM-LABEL: cmp_xor8_int_int:
106 ; ARM: ldrb r2, [r0]
107 ; ARM-NEXT: mov r0, #0
108 ; ARM-NEXT: ldrb r1, [r1]
109 ; ARM-NEXT: teq r1, r2
110 ; ARM-NEXT: movweq r0, #1
111 ; ARM-NEXT: bx lr
112 ;
113 ; ARMEB-LABEL: cmp_xor8_int_int:
114 ; ARMEB: ldrb r2, [r0, #3]
115 ; ARMEB-NEXT: mov r0, #0
116 ; ARMEB-NEXT: ldrb r1, [r1, #3]
117 ; ARMEB-NEXT: teq r1, r2
118 ; ARMEB-NEXT: movweq r0, #1
119 ; ARMEB-NEXT: bx lr
120 ;
121 ; THUMB1-LABEL: cmp_xor8_int_int:
122 ; THUMB1: ldrb r0, [r0]
123 ; THUMB1-NEXT: ldrb r2, [r1]
124 ; THUMB1-NEXT: eors r2, r0
125 ; THUMB1-NEXT: movs r0, #1
126 ; THUMB1-NEXT: movs r1, #0
127 ; THUMB1-NEXT: cmp r2, #0
128 ; THUMB1-NEXT: beq .LBB2_2
129 ; THUMB1-NEXT: @ %bb.1: @ %entry
130 ; THUMB1-NEXT: mov r0, r1
131 ; THUMB1-NEXT: .LBB2_2: @ %entry
132 ; THUMB1-NEXT: bx lr
133 ;
134 ; THUMB2-LABEL: cmp_xor8_int_int:
135 ; THUMB2: ldrb r2, [r0]
136 ; THUMB2-NEXT: movs r0, #0
137 ; THUMB2-NEXT: ldrb r1, [r1]
138 ; THUMB2-NEXT: teq.w r1, r2
139 ; THUMB2-NEXT: it eq
140 ; THUMB2-NEXT: moveq r0, #1
141 ; THUMB2-NEXT: bx lr
142163 entry:
143164 %0 = load i32, i32* %a, align 4
144165 %1 = load i32, i32* %b, align 4
149170 }
150171
151172 define arm_aapcscc zeroext i1 @cmp_xor16(i32* nocapture readonly %a,
173 ; ARM-LABEL: cmp_xor16:
174 ; ARM: @ %bb.0: @ %entry
175 ; ARM-NEXT: ldr r0, [r0]
176 ; ARM-NEXT: movw r2, #65535
177 ; ARM-NEXT: ldr r1, [r1]
178 ; ARM-NEXT: eor r1, r1, r0
179 ; ARM-NEXT: mov r0, #0
180 ; ARM-NEXT: tst r1, r2
181 ; ARM-NEXT: movweq r0, #1
182 ; ARM-NEXT: bx lr
183 ;
184 ; ARMEB-LABEL: cmp_xor16:
185 ; ARMEB: @ %bb.0: @ %entry
186 ; ARMEB-NEXT: ldr r0, [r0]
187 ; ARMEB-NEXT: movw r2, #65535
188 ; ARMEB-NEXT: ldr r1, [r1]
189 ; ARMEB-NEXT: eor r1, r1, r0
190 ; ARMEB-NEXT: mov r0, #0
191 ; ARMEB-NEXT: tst r1, r2
192 ; ARMEB-NEXT: movweq r0, #1
193 ; ARMEB-NEXT: bx lr
194 ;
195 ; THUMB1-LABEL: cmp_xor16:
196 ; THUMB1: @ %bb.0: @ %entry
197 ; THUMB1-NEXT: ldr r0, [r0]
198 ; THUMB1-NEXT: ldr r2, [r1]
199 ; THUMB1-NEXT: eors r2, r0
200 ; THUMB1-NEXT: movs r0, #1
201 ; THUMB1-NEXT: movs r1, #0
202 ; THUMB1-NEXT: lsls r2, r2, #16
203 ; THUMB1-NEXT: beq .LBB3_2
204 ; THUMB1-NEXT: @ %bb.1: @ %entry
205 ; THUMB1-NEXT: mov r0, r1
206 ; THUMB1-NEXT: .LBB3_2: @ %entry
207 ; THUMB1-NEXT: bx lr
208 ;
209 ; THUMB2-LABEL: cmp_xor16:
210 ; THUMB2: @ %bb.0: @ %entry
211 ; THUMB2-NEXT: ldr r0, [r0]
212 ; THUMB2-NEXT: ldr r1, [r1]
213 ; THUMB2-NEXT: eors r0, r1
214 ; THUMB2-NEXT: lsls r0, r0, #16
215 ; THUMB2-NEXT: mov.w r0, #0
216 ; THUMB2-NEXT: it eq
217 ; THUMB2-NEXT: moveq r0, #1
218 ; THUMB2-NEXT: bx lr
152219 i32* nocapture readonly %b) {
153 ; ARM-LABEL: cmp_xor16:
154 ; ARM: ldrh r2, [r0]
155 ; ARM-NEXT: mov r0, #0
156 ; ARM-NEXT: ldrh r1, [r1]
157 ; ARM-NEXT: teq r1, r2
158 ; ARM-NEXT: movweq r0, #1
159 ; ARM-NEXT: bx lr
160 ;
161 ; ARMEB-LABEL: cmp_xor16:
162 ; ARMEB: ldrh r2, [r0, #2]
163 ; ARMEB-NEXT: mov r0, #0
164 ; ARMEB-NEXT: ldrh r1, [r1, #2]
165 ; ARMEB-NEXT: teq r1, r2
166 ; ARMEB-NEXT: movweq r0, #1
167 ; ARMEB-NEXT: bx lr
168 ;
169 ; THUMB1-LABEL: cmp_xor16:
170 ; THUMB1: ldrh r0, [r0]
171 ; THUMB1-NEXT: ldrh r2, [r1]
172 ; THUMB1-NEXT: eors r2, r0
173 ; THUMB1-NEXT: movs r0, #1
174 ; THUMB1-NEXT: movs r1, #0
175 ; THUMB1-NEXT: cmp r2, #0
176 ; THUMB1-NEXT: beq .LBB3_2
177 ; THUMB1-NEXT: @ %bb.1: @ %entry
178 ; THUMB1-NEXT: mov r0, r1
179 ; THUMB1-NEXT: .LBB3_2: @ %entry
180 ; THUMB1-NEXT: bx lr
181 ;
182 ; THUMB2-LABEL: cmp_xor16:
183 ; THUMB2: ldrh r2, [r0]
184 ; THUMB2-NEXT: movs r0, #0
185 ; THUMB2-NEXT: ldrh r1, [r1]
186 ; THUMB2-NEXT: teq.w r1, r2
187 ; THUMB2-NEXT: it eq
188 ; THUMB2-NEXT: moveq r0, #1
189 ; THUMB2-NEXT: bx lr
190220 entry:
191221 %0 = load i32, i32* %a, align 4
192222 %1 = load i32, i32* %b, align 4
197227 }
198228
199229 define arm_aapcscc zeroext i1 @cmp_or8_short_short(i16* nocapture readonly %a,
230 ; ARM-LABEL: cmp_or8_short_short:
231 ; ARM: @ %bb.0: @ %entry
232 ; ARM-NEXT: ldrh r0, [r0]
233 ; ARM-NEXT: ldrh r1, [r1]
234 ; ARM-NEXT: orr r1, r1, r0
235 ; ARM-NEXT: mov r0, #0
236 ; ARM-NEXT: tst r1, #255
237 ; ARM-NEXT: movweq r0, #1
238 ; ARM-NEXT: bx lr
239 ;
240 ; ARMEB-LABEL: cmp_or8_short_short:
241 ; ARMEB: @ %bb.0: @ %entry
242 ; ARMEB-NEXT: ldrh r0, [r0]
243 ; ARMEB-NEXT: ldrh r1, [r1]
244 ; ARMEB-NEXT: orr r1, r1, r0
245 ; ARMEB-NEXT: mov r0, #0
246 ; ARMEB-NEXT: tst r1, #255
247 ; ARMEB-NEXT: movweq r0, #1
248 ; ARMEB-NEXT: bx lr
249 ;
250 ; THUMB1-LABEL: cmp_or8_short_short:
251 ; THUMB1: @ %bb.0: @ %entry
252 ; THUMB1-NEXT: ldrh r0, [r0]
253 ; THUMB1-NEXT: ldrh r2, [r1]
254 ; THUMB1-NEXT: orrs r2, r0
255 ; THUMB1-NEXT: movs r0, #1
256 ; THUMB1-NEXT: movs r1, #0
257 ; THUMB1-NEXT: lsls r2, r2, #24
258 ; THUMB1-NEXT: beq .LBB4_2
259 ; THUMB1-NEXT: @ %bb.1: @ %entry
260 ; THUMB1-NEXT: mov r0, r1
261 ; THUMB1-NEXT: .LBB4_2: @ %entry
262 ; THUMB1-NEXT: bx lr
263 ;
264 ; THUMB2-LABEL: cmp_or8_short_short:
265 ; THUMB2: @ %bb.0: @ %entry
266 ; THUMB2-NEXT: ldrh r0, [r0]
267 ; THUMB2-NEXT: ldrh r1, [r1]
268 ; THUMB2-NEXT: orrs r0, r1
269 ; THUMB2-NEXT: lsls r0, r0, #24
270 ; THUMB2-NEXT: mov.w r0, #0
271 ; THUMB2-NEXT: it eq
272 ; THUMB2-NEXT: moveq r0, #1
273 ; THUMB2-NEXT: bx lr
200274 i16* nocapture readonly %b) {
201 ; ARM-LABEL: cmp_or8_short_short:
202 ; ARM: ldrb r0, [r0]
203 ; ARM-NEXT: ldrb r1, [r1]
204 ; ARM-NEXT: orrs r0, r1, r0
205 ; ARM-NEXT: mov r0, #0
206 ; ARM-NEXT: movweq r0, #1
207 ; ARM-NEXT: bx lr
208 ;
209 ; ARMEB-LABEL: cmp_or8_short_short:
210 ; ARMEB: ldrb r0, [r0, #1]
211 ; ARMEB-NEXT: ldrb r1, [r1, #1]
212 ; ARMEB-NEXT: orrs r0, r1, r0
213 ; ARMEB-NEXT: mov r0, #0
214 ; ARMEB-NEXT: movweq r0, #1
215 ; ARMEB-NEXT: bx lr
216 ;
217 ; THUMB1-LABEL: cmp_or8_short_short:
218 ; THUMB1: ldrb r0, [r0]
219 ; THUMB1-NEXT: ldrb r2, [r1]
220 ; THUMB1-NEXT: orrs r2, r0
221 ; THUMB1-NEXT: movs r0, #1
222 ; THUMB1-NEXT: movs r1, #0
223 ; THUMB1-NEXT: cmp r2, #0
224 ; THUMB1-NEXT: beq .LBB4_2
225 ; THUMB1-NEXT: @ %bb.1: @ %entry
226 ; THUMB1-NEXT: mov r0, r1
227 ; THUMB1-NEXT: .LBB4_2: @ %entry
228 ; THUMB1-NEXT: bx lr
229 ;
230 ; THUMB2-LABEL: cmp_or8_short_short:
231 ; THUMB2: ldrb r0, [r0]
232 ; THUMB2-NEXT: ldrb r1, [r1]
233 ; THUMB2-NEXT: orrs r0, r1
234 ; THUMB2-NEXT: mov.w r0, #0
235 ; THUMB2-NEXT: it eq
236 ; THUMB2-NEXT: moveq r0, #1
237 ; THUMB2-NEXT: bx lr
238275 entry:
239276 %0 = load i16, i16* %a, align 2
240277 %1 = load i16, i16* %b, align 2
245282 }
246283
247284 define arm_aapcscc zeroext i1 @cmp_or8_short_int(i16* nocapture readonly %a,
285 ; ARM-LABEL: cmp_or8_short_int:
286 ; ARM: @ %bb.0: @ %entry
287 ; ARM-NEXT: ldrh r0, [r0]
288 ; ARM-NEXT: ldr r1, [r1]
289 ; ARM-NEXT: orr r1, r1, r0
290 ; ARM-NEXT: mov r0, #0
291 ; ARM-NEXT: tst r1, #255
292 ; ARM-NEXT: movweq r0, #1
293 ; ARM-NEXT: bx lr
294 ;
295 ; ARMEB-LABEL: cmp_or8_short_int:
296 ; ARMEB: @ %bb.0: @ %entry
297 ; ARMEB-NEXT: ldrh r0, [r0]
298 ; ARMEB-NEXT: ldr r1, [r1]
299 ; ARMEB-NEXT: orr r1, r1, r0
300 ; ARMEB-NEXT: mov r0, #0
301 ; ARMEB-NEXT: tst r1, #255
302 ; ARMEB-NEXT: movweq r0, #1
303 ; ARMEB-NEXT: bx lr
304 ;
305 ; THUMB1-LABEL: cmp_or8_short_int:
306 ; THUMB1: @ %bb.0: @ %entry
307 ; THUMB1-NEXT: ldrh r0, [r0]
308 ; THUMB1-NEXT: ldr r2, [r1]
309 ; THUMB1-NEXT: orrs r2, r0
310 ; THUMB1-NEXT: movs r0, #1
311 ; THUMB1-NEXT: movs r1, #0
312 ; THUMB1-NEXT: lsls r2, r2, #24
313 ; THUMB1-NEXT: beq .LBB5_2
314 ; THUMB1-NEXT: @ %bb.1: @ %entry
315 ; THUMB1-NEXT: mov r0, r1
316 ; THUMB1-NEXT: .LBB5_2: @ %entry
317 ; THUMB1-NEXT: bx lr
318 ;
319 ; THUMB2-LABEL: cmp_or8_short_int:
320 ; THUMB2: @ %bb.0: @ %entry
321 ; THUMB2-NEXT: ldrh r0, [r0]
322 ; THUMB2-NEXT: ldr r1, [r1]
323 ; THUMB2-NEXT: orrs r0, r1
324 ; THUMB2-NEXT: lsls r0, r0, #24
325 ; THUMB2-NEXT: mov.w r0, #0
326 ; THUMB2-NEXT: it eq
327 ; THUMB2-NEXT: moveq r0, #1
328 ; THUMB2-NEXT: bx lr
248329 i32* nocapture readonly %b) {
249 ; ARM-LABEL: cmp_or8_short_int:
250 ; ARM: ldrb r0, [r0]
251 ; ARM-NEXT: ldrb r1, [r1]
252 ; ARM-NEXT: orrs r0, r1, r0
253 ; ARM-NEXT: mov r0, #0
254 ; ARM-NEXT: movweq r0, #1
255 ; ARM-NEXT: bx lr
256 ;
257 ; ARMEB-LABEL: cmp_or8_short_int:
258 ; ARMEB: ldrb r0, [r0, #1]
259 ; ARMEB-NEXT: ldrb r1, [r1, #3]
260 ; ARMEB-NEXT: orrs r0, r1, r0
261 ; ARMEB-NEXT: mov r0, #0
262 ; ARMEB-NEXT: movweq r0, #1
263 ; ARMEB-NEXT: bx lr
264 ;
265 ; THUMB1-LABEL: cmp_or8_short_int:
266 ; THUMB1: ldrb r0, [r0]
267 ; THUMB1-NEXT: ldrb r2, [r1]
268 ; THUMB1-NEXT: orrs r2, r0
269 ; THUMB1-NEXT: movs r0, #1
270 ; THUMB1-NEXT: movs r1, #0
271 ; THUMB1-NEXT: cmp r2, #0
272 ; THUMB1-NEXT: beq .LBB5_2
273 ; THUMB1-NEXT: @ %bb.1: @ %entry
274 ; THUMB1-NEXT: mov r0, r1
275 ; THUMB1-NEXT: .LBB5_2: @ %entry
276 ; THUMB1-NEXT: bx lr
277 ;
278 ; THUMB2-LABEL: cmp_or8_short_int:
279 ; THUMB2: ldrb r0, [r0]
280 ; THUMB2-NEXT: ldrb r1, [r1]
281 ; THUMB2-NEXT: orrs r0, r1
282 ; THUMB2-NEXT: mov.w r0, #0
283 ; THUMB2-NEXT: it eq
284 ; THUMB2-NEXT: moveq r0, #1
285 ; THUMB2-NEXT: bx lr
286330 entry:
287331 %0 = load i16, i16* %a, align 2
288332 %conv = zext i16 %0 to i32
294338 }
295339
296340 define arm_aapcscc zeroext i1 @cmp_or8_int_int(i32* nocapture readonly %a,
341 ; ARM-LABEL: cmp_or8_int_int:
342 ; ARM: @ %bb.0: @ %entry
343 ; ARM-NEXT: ldr r0, [r0]
344 ; ARM-NEXT: ldr r1, [r1]
345 ; ARM-NEXT: orr r1, r1, r0
346 ; ARM-NEXT: mov r0, #0
347 ; ARM-NEXT: tst r1, #255
348 ; ARM-NEXT: movweq r0, #1
349 ; ARM-NEXT: bx lr
350 ;
351 ; ARMEB-LABEL: cmp_or8_int_int:
352 ; ARMEB: @ %bb.0: @ %entry
353 ; ARMEB-NEXT: ldr r0, [r0]
354 ; ARMEB-NEXT: ldr r1, [r1]
355 ; ARMEB-NEXT: orr r1, r1, r0
356 ; ARMEB-NEXT: mov r0, #0
357 ; ARMEB-NEXT: tst r1, #255
358 ; ARMEB-NEXT: movweq r0, #1
359 ; ARMEB-NEXT: bx lr
360 ;
361 ; THUMB1-LABEL: cmp_or8_int_int:
362 ; THUMB1: @ %bb.0: @ %entry
363 ; THUMB1-NEXT: ldr r0, [r0]
364 ; THUMB1-NEXT: ldr r2, [r1]
365 ; THUMB1-NEXT: orrs r2, r0
366 ; THUMB1-NEXT: movs r0, #1
367 ; THUMB1-NEXT: movs r1, #0
368 ; THUMB1-NEXT: lsls r2, r2, #24
369 ; THUMB1-NEXT: beq .LBB6_2
370 ; THUMB1-NEXT: @ %bb.1: @ %entry
371 ; THUMB1-NEXT: mov r0, r1
372 ; THUMB1-NEXT: .LBB6_2: @ %entry
373 ; THUMB1-NEXT: bx lr
374 ;
375 ; THUMB2-LABEL: cmp_or8_int_int:
376 ; THUMB2: @ %bb.0: @ %entry
377 ; THUMB2-NEXT: ldr r0, [r0]
378 ; THUMB2-NEXT: ldr r1, [r1]
379 ; THUMB2-NEXT: orrs r0, r1
380 ; THUMB2-NEXT: lsls r0, r0, #24
381 ; THUMB2-NEXT: mov.w r0, #0
382 ; THUMB2-NEXT: it eq
383 ; THUMB2-NEXT: moveq r0, #1
384 ; THUMB2-NEXT: bx lr
297385 i32* nocapture readonly %b) {
298 ; ARM-LABEL: cmp_or8_int_int:
299 ; ARM: ldrb r0, [r0]
300 ; ARM-NEXT: ldrb r1, [r1]
301 ; ARM-NEXT: orrs r0, r1, r0
302 ; ARM-NEXT: mov r0, #0
303 ; ARM-NEXT: movweq r0, #1
304 ; ARM-NEXT: bx lr
305 ;
306 ; ARMEB-LABEL: cmp_or8_int_int:
307 ; ARMEB: ldrb r0, [r0, #3]
308 ; ARMEB-NEXT: ldrb r1, [r1, #3]
309 ; ARMEB-NEXT: orrs r0, r1, r0
310 ; ARMEB-NEXT: mov r0, #0
311 ; ARMEB-NEXT: movweq r0, #1
312 ; ARMEB-NEXT: bx lr
313 ;
314 ; THUMB1-LABEL: cmp_or8_int_int:
315 ; THUMB1: ldrb r0, [r0]
316 ; THUMB1-NEXT: ldrb r2, [r1]
317 ; THUMB1-NEXT: orrs r2, r0
318 ; THUMB1-NEXT: movs r0, #1
319 ; THUMB1-NEXT: movs r1, #0
320 ; THUMB1-NEXT: cmp r2, #0
321 ; THUMB1-NEXT: beq .LBB6_2
322 ; THUMB1-NEXT: @ %bb.1: @ %entry
323 ; THUMB1-NEXT: mov r0, r1
324 ; THUMB1-NEXT: .LBB6_2: @ %entry
325 ; THUMB1-NEXT: bx lr
326 ;
327 ; THUMB2-LABEL: cmp_or8_int_int:
328 ; THUMB2: ldrb r0, [r0]
329 ; THUMB2-NEXT: ldrb r1, [r1]
330 ; THUMB2-NEXT: orrs r0, r1
331 ; THUMB2-NEXT: mov.w r0, #0
332 ; THUMB2-NEXT: it eq
333 ; THUMB2-NEXT: moveq r0, #1
334 ; THUMB2-NEXT: bx lr
335386 entry:
336387 %0 = load i32, i32* %a, align 4
337388 %1 = load i32, i32* %b, align 4
342393 }
343394
344395 define arm_aapcscc zeroext i1 @cmp_or16(i32* nocapture readonly %a,
396 ; ARM-LABEL: cmp_or16:
397 ; ARM: @ %bb.0: @ %entry
398 ; ARM-NEXT: ldr r0, [r0]
399 ; ARM-NEXT: movw r2, #65535
400 ; ARM-NEXT: ldr r1, [r1]
401 ; ARM-NEXT: orr r1, r1, r0
402 ; ARM-NEXT: mov r0, #0
403 ; ARM-NEXT: tst r1, r2
404 ; ARM-NEXT: movweq r0, #1
405 ; ARM-NEXT: bx lr
406 ;
407 ; ARMEB-LABEL: cmp_or16:
408 ; ARMEB: @ %bb.0: @ %entry
409 ; ARMEB-NEXT: ldr r0, [r0]
410 ; ARMEB-NEXT: movw r2, #65535
411 ; ARMEB-NEXT: ldr r1, [r1]
412 ; ARMEB-NEXT: orr r1, r1, r0
413 ; ARMEB-NEXT: mov r0, #0
414 ; ARMEB-NEXT: tst r1, r2
415 ; ARMEB-NEXT: movweq r0, #1
416 ; ARMEB-NEXT: bx lr
417 ;
418 ; THUMB1-LABEL: cmp_or16:
419 ; THUMB1: @ %bb.0: @ %entry
420 ; THUMB1-NEXT: ldr r0, [r0]
421 ; THUMB1-NEXT: ldr r2, [r1]
422 ; THUMB1-NEXT: orrs r2, r0
423 ; THUMB1-NEXT: movs r0, #1
424 ; THUMB1-NEXT: movs r1, #0
425 ; THUMB1-NEXT: lsls r2, r2, #16
426 ; THUMB1-NEXT: beq .LBB7_2
427 ; THUMB1-NEXT: @ %bb.1: @ %entry
428 ; THUMB1-NEXT: mov r0, r1
429 ; THUMB1-NEXT: .LBB7_2: @ %entry
430 ; THUMB1-NEXT: bx lr
431 ;
432 ; THUMB2-LABEL: cmp_or16:
433 ; THUMB2: @ %bb.0: @ %entry
434 ; THUMB2-NEXT: ldr r0, [r0]
435 ; THUMB2-NEXT: ldr r1, [r1]
436 ; THUMB2-NEXT: orrs r0, r1
437 ; THUMB2-NEXT: lsls r0, r0, #16
438 ; THUMB2-NEXT: mov.w r0, #0
439 ; THUMB2-NEXT: it eq
440 ; THUMB2-NEXT: moveq r0, #1
441 ; THUMB2-NEXT: bx lr
345442 i32* nocapture readonly %b) {
346 ; ARM-LABEL: cmp_or16:
347 ; ARM: ldrh r0, [r0]
348 ; ARM-NEXT: ldrh r1, [r1]
349 ; ARM-NEXT: orrs r0, r1, r0
350 ; ARM-NEXT: mov r0, #0
351 ; ARM-NEXT: movweq r0, #1
352 ; ARM-NEXT: bx lr
353 ;
354 ; ARMEB-LABEL: cmp_or16:
355 ; ARMEB: ldrh r0, [r0, #2]
356 ; ARMEB-NEXT: ldrh r1, [r1, #2]
357 ; ARMEB-NEXT: orrs r0, r1, r0
358 ; ARMEB-NEXT: mov r0, #0
359 ; ARMEB-NEXT: movweq r0, #1
360 ; ARMEB-NEXT: bx lr
361 ;
362 ; THUMB1-LABEL: cmp_or16:
363 ; THUMB1: ldrh r0, [r0]
364 ; THUMB1-NEXT: ldrh r2, [r1]
365 ; THUMB1-NEXT: orrs r2, r0
366 ; THUMB1-NEXT: movs r0, #1
367 ; THUMB1-NEXT: movs r1, #0
368 ; THUMB1-NEXT: cmp r2, #0
369 ; THUMB1-NEXT: beq .LBB7_2
370 ; THUMB1-NEXT: @ %bb.1: @ %entry
371 ; THUMB1-NEXT: mov r0, r1
372 ; THUMB1-NEXT: .LBB7_2: @ %entry
373 ; THUMB1-NEXT: bx lr
374 ;
375 ; THUMB2-LABEL: cmp_or16:
376 ; THUMB2: ldrh r0, [r0]
377 ; THUMB2-NEXT: ldrh r1, [r1]
378 ; THUMB2-NEXT: orrs r0, r1
379 ; THUMB2-NEXT: mov.w r0, #0
380 ; THUMB2-NEXT: it eq
381 ; THUMB2-NEXT: moveq r0, #1
382 ; THUMB2-NEXT: bx lr
383443 entry:
384444 %0 = load i32, i32* %a, align 4
385445 %1 = load i32, i32* %b, align 4
390450 }
391451
392452 define arm_aapcscc zeroext i1 @cmp_and8_short_short(i16* nocapture readonly %a,
453 ; ARM-LABEL: cmp_and8_short_short:
454 ; ARM: @ %bb.0: @ %entry
455 ; ARM-NEXT: ldrh r1, [r1]
456 ; ARM-NEXT: ldrh r0, [r0]
457 ; ARM-NEXT: and r1, r0, r1
458 ; ARM-NEXT: mov r0, #0
459 ; ARM-NEXT: tst r1, #255
460 ; ARM-NEXT: movweq r0, #1
461 ; ARM-NEXT: bx lr
462 ;
463 ; ARMEB-LABEL: cmp_and8_short_short:
464 ; ARMEB: @ %bb.0: @ %entry
465 ; ARMEB-NEXT: ldrh r1, [r1]
466 ; ARMEB-NEXT: ldrh r0, [r0]
467 ; ARMEB-NEXT: and r1, r0, r1
468 ; ARMEB-NEXT: mov r0, #0
469 ; ARMEB-NEXT: tst r1, #255
470 ; ARMEB-NEXT: movweq r0, #1
471 ; ARMEB-NEXT: bx lr
472 ;
473 ; THUMB1-LABEL: cmp_and8_short_short:
474 ; THUMB1: @ %bb.0: @ %entry
475 ; THUMB1-NEXT: ldrh r1, [r1]
476 ; THUMB1-NEXT: ldrh r2, [r0]
477 ; THUMB1-NEXT: ands r2, r1
478 ; THUMB1-NEXT: movs r0, #1
479 ; THUMB1-NEXT: movs r1, #0
480 ; THUMB1-NEXT: lsls r2, r2, #24
481 ; THUMB1-NEXT: beq .LBB8_2
482 ; THUMB1-NEXT: @ %bb.1: @ %entry
483 ; THUMB1-NEXT: mov r0, r1
484 ; THUMB1-NEXT: .LBB8_2: @ %entry
485 ; THUMB1-NEXT: bx lr
486 ;
487 ; THUMB2-LABEL: cmp_and8_short_short:
488 ; THUMB2: @ %bb.0: @ %entry
489 ; THUMB2-NEXT: ldrh r1, [r1]
490 ; THUMB2-NEXT: ldrh r0, [r0]
491 ; THUMB2-NEXT: ands r0, r1
492 ; THUMB2-NEXT: lsls r0, r0, #24
493 ; THUMB2-NEXT: mov.w r0, #0
494 ; THUMB2-NEXT: it eq
495 ; THUMB2-NEXT: moveq r0, #1
496 ; THUMB2-NEXT: bx lr
393497 i16* nocapture readonly %b) {
394 ; ARM-LABEL: cmp_and8_short_short:
395 ; ARM: ldrb r2, [r0]
396 ; ARM-NEXT: mov r0, #0
397 ; ARM-NEXT: ldrb r1, [r1]
398 ; ARM-NEXT: tst r2, r1
399 ; ARM-NEXT: movweq r0, #1
400 ; ARM-NEXT: bx lr
401 ;
402 ; ARMEB-LABEL: cmp_and8_short_short:
403 ; ARMEB: ldrb r2, [r0, #1]
404 ; ARMEB-NEXT: mov r0, #0
405 ; ARMEB-NEXT: ldrb r1, [r1, #1]
406 ; ARMEB-NEXT: tst r2, r1
407 ; ARMEB-NEXT: movweq r0, #1
408 ; ARMEB-NEXT: bx lr
409 ;
410 ; THUMB1-LABEL: cmp_and8_short_short:
411 ; THUMB1: ldrb r2, [r1]
412 ; THUMB1-NEXT: ldrb r3, [r0]
413 ; THUMB1-NEXT: movs r0, #1
414 ; THUMB1-NEXT: movs r1, #0
415 ; THUMB1-NEXT: tst r3, r2
416 ; THUMB1-NEXT: beq .LBB8_2
417 ; THUMB1-NEXT: @ %bb.1: @ %entry
418 ; THUMB1-NEXT: mov r0, r1
419 ; THUMB1-NEXT: .LBB8_2: @ %entry
420 ; THUMB1-NEXT: bx lr
421 ;
422 ; THUMB2-LABEL: cmp_and8_short_short:
423 ; THUMB2: ldrb r2, [r0]
424 ; THUMB2-NEXT: movs r0, #0
425 ; THUMB2-NEXT: ldrb r1, [r1]
426 ; THUMB2-NEXT: tst r2, r1
427 ; THUMB2-NEXT: it eq
428 ; THUMB2-NEXT: moveq r0, #1
429 ; THUMB2-NEXT: bx lr
430498 entry:
431499 %0 = load i16, i16* %a, align 2
432500 %1 = load i16, i16* %b, align 2
437505 }
438506
439507 define arm_aapcscc zeroext i1 @cmp_and8_short_int(i16* nocapture readonly %a,
508 ; ARM-LABEL: cmp_and8_short_int:
509 ; ARM: @ %bb.0: @ %entry
510 ; ARM-NEXT: ldrh r0, [r0]
511 ; ARM-NEXT: ldr r1, [r1]
512 ; ARM-NEXT: and r1, r1, r0
513 ; ARM-NEXT: mov r0, #0
514 ; ARM-NEXT: tst r1, #255
515 ; ARM-NEXT: movweq r0, #1
516 ; ARM-NEXT: bx lr
517 ;
518 ; ARMEB-LABEL: cmp_and8_short_int:
519 ; ARMEB: @ %bb.0: @ %entry
520 ; ARMEB-NEXT: ldrh r0, [r0]
521 ; ARMEB-NEXT: ldr r1, [r1]
522 ; ARMEB-NEXT: and r1, r1, r0
523 ; ARMEB-NEXT: mov r0, #0
524 ; ARMEB-NEXT: tst r1, #255
525 ; ARMEB-NEXT: movweq r0, #1
526 ; ARMEB-NEXT: bx lr
527 ;
528 ; THUMB1-LABEL: cmp_and8_short_int:
529 ; THUMB1: @ %bb.0: @ %entry
530 ; THUMB1-NEXT: ldrh r0, [r0]
531 ; THUMB1-NEXT: ldr r2, [r1]
532 ; THUMB1-NEXT: ands r2, r0
533 ; THUMB1-NEXT: movs r0, #1
534 ; THUMB1-NEXT: movs r1, #0
535 ; THUMB1-NEXT: lsls r2, r2, #24
536 ; THUMB1-NEXT: beq .LBB9_2
537 ; THUMB1-NEXT: @ %bb.1: @ %entry
538 ; THUMB1-NEXT: mov r0, r1
539 ; THUMB1-NEXT: .LBB9_2: @ %entry
540 ; THUMB1-NEXT: bx lr
541 ;
542 ; THUMB2-LABEL: cmp_and8_short_int:
543 ; THUMB2: @ %bb.0: @ %entry
544 ; THUMB2-NEXT: ldrh r0, [r0]
545 ; THUMB2-NEXT: ldr r1, [r1]
546 ; THUMB2-NEXT: ands r0, r1
547 ; THUMB2-NEXT: lsls r0, r0, #24
548 ; THUMB2-NEXT: mov.w r0, #0
549 ; THUMB2-NEXT: it eq
550 ; THUMB2-NEXT: moveq r0, #1
551 ; THUMB2-NEXT: bx lr
440552 i32* nocapture readonly %b) {
441 ; ARM-LABEL: cmp_and8_short_int:
442 ; ARM: ldrb r2, [r0]
443 ; ARM-NEXT: mov r0, #0
444 ; ARM-NEXT: ldrb r1, [r1]
445 ; ARM-NEXT: tst r1, r2
446 ; ARM-NEXT: movweq r0, #1
447 ; ARM-NEXT: bx lr
448 ;
449 ; ARMEB-LABEL: cmp_and8_short_int:
450 ; ARMEB: ldrb r2, [r0, #1]
451 ; ARMEB-NEXT: mov r0, #0
452 ; ARMEB-NEXT: ldrb r1, [r1, #3]
453 ; ARMEB-NEXT: tst r1, r2
454 ; ARMEB-NEXT: movweq r0, #1
455 ; ARMEB-NEXT: bx lr
456 ;
457 ; THUMB1-LABEL: cmp_and8_short_int:
458 ; THUMB1: ldrb r2, [r0]
459 ; THUMB1-NEXT: ldrb r3, [r1]
460 ; THUMB1-NEXT: movs r0, #1
461 ; THUMB1-NEXT: movs r1, #0
462 ; THUMB1-NEXT: tst r3, r2
463 ; THUMB1-NEXT: beq .LBB9_2
464 ; THUMB1-NEXT: @ %bb.1: @ %entry
465 ; THUMB1-NEXT: mov r0, r1
466 ; THUMB1-NEXT: .LBB9_2: @ %entry
467 ; THUMB1-NEXT: bx lr
468 ;
469 ; THUMB2-LABEL: cmp_and8_short_int:
470 ; THUMB2: ldrb r2, [r0]
471 ; THUMB2-NEXT: movs r0, #0
472 ; THUMB2-NEXT: ldrb r1, [r1]
473 ; THUMB2-NEXT: tst r1, r2
474 ; THUMB2-NEXT: it eq
475 ; THUMB2-NEXT: moveq r0, #1
476 ; THUMB2-NEXT: bx lr
477553 entry:
478554 %0 = load i16, i16* %a, align 2
479555 %1 = load i32, i32* %b, align 4
485561 }
486562
487563 define arm_aapcscc zeroext i1 @cmp_and8_int_int(i32* nocapture readonly %a,
564 ; ARM-LABEL: cmp_and8_int_int:
565 ; ARM: @ %bb.0: @ %entry
566 ; ARM-NEXT: ldr r1, [r1]
567 ; ARM-NEXT: ldr r0, [r0]
568 ; ARM-NEXT: and r1, r0, r1
569 ; ARM-NEXT: mov r0, #0
570 ; ARM-NEXT: tst r1, #255
571 ; ARM-NEXT: movweq r0, #1
572 ; ARM-NEXT: bx lr
573 ;
574 ; ARMEB-LABEL: cmp_and8_int_int:
575 ; ARMEB: @ %bb.0: @ %entry
576 ; ARMEB-NEXT: ldr r1, [r1]
577 ; ARMEB-NEXT: ldr r0, [r0]
578 ; ARMEB-NEXT: and r1, r0, r1
579 ; ARMEB-NEXT: mov r0, #0
580 ; ARMEB-NEXT: tst r1, #255
581 ; ARMEB-NEXT: movweq r0, #1
582 ; ARMEB-NEXT: bx lr
583 ;
584 ; THUMB1-LABEL: cmp_and8_int_int:
585 ; THUMB1: @ %bb.0: @ %entry
586 ; THUMB1-NEXT: ldr r1, [r1]
587 ; THUMB1-NEXT: ldr r2, [r0]
588 ; THUMB1-NEXT: ands r2, r1
589 ; THUMB1-NEXT: movs r0, #1
590 ; THUMB1-NEXT: movs r1, #0
591 ; THUMB1-NEXT: lsls r2, r2, #24
592 ; THUMB1-NEXT: beq .LBB10_2
593 ; THUMB1-NEXT: @ %bb.1: @ %entry
594 ; THUMB1-NEXT: mov r0, r1
595 ; THUMB1-NEXT: .LBB10_2: @ %entry
596 ; THUMB1-NEXT: bx lr
597 ;
598 ; THUMB2-LABEL: cmp_and8_int_int:
599 ; THUMB2: @ %bb.0: @ %entry
600 ; THUMB2-NEXT: ldr r1, [r1]
601 ; THUMB2-NEXT: ldr r0, [r0]
602 ; THUMB2-NEXT: ands r0, r1
603 ; THUMB2-NEXT: lsls r0, r0, #24
604 ; THUMB2-NEXT: mov.w r0, #0
605 ; THUMB2-NEXT: it eq
606 ; THUMB2-NEXT: moveq r0, #1
607 ; THUMB2-NEXT: bx lr
488608 i32* nocapture readonly %b) {
489 ; ARM-LABEL: cmp_and8_int_int:
490 ; ARM: ldrb r2, [r0]
491 ; ARM-NEXT: mov r0, #0
492 ; ARM-NEXT: ldrb r1, [r1]
493 ; ARM-NEXT: tst r2, r1
494 ; ARM-NEXT: movweq r0, #1
495 ; ARM-NEXT: bx lr
496 ;
497 ; ARMEB-LABEL: cmp_and8_int_int:
498 ; ARMEB: ldrb r2, [r0, #3]
499 ; ARMEB-NEXT: mov r0, #0
500 ; ARMEB-NEXT: ldrb r1, [r1, #3]
501 ; ARMEB-NEXT: tst r2, r1
502 ; ARMEB-NEXT: movweq r0, #1
503 ; ARMEB-NEXT: bx lr
504 ;
505 ; THUMB1-LABEL: cmp_and8_int_int:
506 ; THUMB1: ldrb r2, [r1]
507 ; THUMB1-NEXT: ldrb r3, [r0]
508 ; THUMB1-NEXT: movs r0, #1
509 ; THUMB1-NEXT: movs r1, #0
510 ; THUMB1-NEXT: tst r3, r2
511 ; THUMB1-NEXT: beq .LBB10_2
512 ; THUMB1-NEXT: @ %bb.1: @ %entry
513 ; THUMB1-NEXT: mov r0, r1
514 ; THUMB1-NEXT: .LBB10_2: @ %entry
515 ; THUMB1-NEXT: bx lr
516 ;
517 ; THUMB2-LABEL: cmp_and8_int_int:
518 ; THUMB2: ldrb r2, [r0]
519 ; THUMB2-NEXT: movs r0, #0
520 ; THUMB2-NEXT: ldrb r1, [r1]
521 ; THUMB2-NEXT: tst r2, r1
522 ; THUMB2-NEXT: it eq
523 ; THUMB2-NEXT: moveq r0, #1
524 ; THUMB2-NEXT: bx lr
525609 entry:
526610 %0 = load i32, i32* %a, align 4
527611 %1 = load i32, i32* %b, align 4
532616 }
533617
534618 define arm_aapcscc zeroext i1 @cmp_and16(i32* nocapture readonly %a,
619 ; ARM-LABEL: cmp_and16:
620 ; ARM: @ %bb.0: @ %entry
621 ; ARM-NEXT: ldr r1, [r1]
622 ; ARM-NEXT: movw r2, #65535
623 ; ARM-NEXT: ldr r0, [r0]
624 ; ARM-NEXT: and r1, r0, r1
625 ; ARM-NEXT: mov r0, #0
626 ; ARM-NEXT: tst r1, r2
627 ; ARM-NEXT: movweq r0, #1
628 ; ARM-NEXT: bx lr
629 ;
630 ; ARMEB-LABEL: cmp_and16:
631 ; ARMEB: @ %bb.0: @ %entry
632 ; ARMEB-NEXT: ldr r1, [r1]
633 ; ARMEB-NEXT: movw r2, #65535
634 ; ARMEB-NEXT: ldr r0, [r0]
635 ; ARMEB-NEXT: and r1, r0, r1
636 ; ARMEB-NEXT: mov r0, #0
637 ; ARMEB-NEXT: tst r1, r2
638 ; ARMEB-NEXT: movweq r0, #1
639 ; ARMEB-NEXT: bx lr
640 ;
641 ; THUMB1-LABEL: cmp_and16:
642 ; THUMB1: @ %bb.0: @ %entry
643 ; THUMB1-NEXT: ldr r1, [r1]
644 ; THUMB1-NEXT: ldr r2, [r0]
645 ; THUMB1-NEXT: ands r2, r1
646 ; THUMB1-NEXT: movs r0, #1
647 ; THUMB1-NEXT: movs r1, #0
648 ; THUMB1-NEXT: lsls r2, r2, #16
649 ; THUMB1-NEXT: beq .LBB11_2
650 ; THUMB1-NEXT: @ %bb.1: @ %entry
651 ; THUMB1-NEXT: mov r0, r1
652 ; THUMB1-NEXT: .LBB11_2: @ %entry
653 ; THUMB1-NEXT: bx lr
654 ;
655 ; THUMB2-LABEL: cmp_and16:
656 ; THUMB2: @ %bb.0: @ %entry
657 ; THUMB2-NEXT: ldr r1, [r1]
658 ; THUMB2-NEXT: ldr r0, [r0]
659 ; THUMB2-NEXT: ands r0, r1
660 ; THUMB2-NEXT: lsls r0, r0, #16
661 ; THUMB2-NEXT: mov.w r0, #0
662 ; THUMB2-NEXT: it eq
663 ; THUMB2-NEXT: moveq r0, #1
664 ; THUMB2-NEXT: bx lr
535665 i32* nocapture readonly %b) {
536 ; ARM-LABEL: cmp_and16:
537 ; ARM: ldrh r2, [r0]
538 ; ARM-NEXT: mov r0, #0
539 ; ARM-NEXT: ldrh r1, [r1]
540 ; ARM-NEXT: tst r2, r1
541 ; ARM-NEXT: movweq r0, #1
542 ; ARM-NEXT: bx lr
543 ;
544 ; ARMEB-LABEL: cmp_and16:
545 ; ARMEB: ldrh r2, [r0, #2]
546 ; ARMEB-NEXT: mov r0, #0
547 ; ARMEB-NEXT: ldrh r1, [r1, #2]
548 ; ARMEB-NEXT: tst r2, r1
549 ; ARMEB-NEXT: movweq r0, #1
550 ; ARMEB-NEXT: bx lr
551 ;
552 ; THUMB1-LABEL: cmp_and16:
553 ; THUMB1: ldrh r2, [r1]
554 ; THUMB1-NEXT: ldrh r3, [r0]
555 ; THUMB1-NEXT: movs r0, #1
556 ; THUMB1-NEXT: movs r1, #0
557 ; THUMB1-NEXT: tst r3, r2
558 ; THUMB1-NEXT: beq .LBB11_2
559 ; THUMB1-NEXT: @ %bb.1: @ %entry
560 ; THUMB1-NEXT: mov r0, r1
561 ; THUMB1-NEXT: .LBB11_2: @ %entry
562 ; THUMB1-NEXT: bx lr
563 ;
564 ; THUMB2-LABEL: cmp_and16:
565 ; THUMB2: ldrh r2, [r0]
566 ; THUMB2-NEXT: movs r0, #0
567 ; THUMB2-NEXT: ldrh r1, [r1]
568 ; THUMB2-NEXT: tst r2, r1
569 ; THUMB2-NEXT: it eq
570 ; THUMB2-NEXT: moveq r0, #1
571 ; THUMB2-NEXT: bx lr
572666 entry:
573667 %0 = load i32, i32* %a, align 4
574668 %1 = load i32, i32* %b, align 4
580674
581675 define arm_aapcscc i32 @add_and16(i32* nocapture readonly %a, i32 %y, i32 %z) {
582676 ; ARM-LABEL: add_and16:
583 ; ARM: add r1, r1, r2
584 ; ARM-NEXT: ldrh r0, [r0]
585 ; ARM-NEXT: uxth r1, r1
677 ; ARM: @ %bb.0: @ %entry
678 ; ARM-NEXT: ldr r0, [r0]
679 ; ARM-NEXT: add r1, r1, r2
586680 ; ARM-NEXT: orr r0, r0, r1
681 ; ARM-NEXT: uxth r0, r0
587682 ; ARM-NEXT: bx lr
588683 ;
589684 ; ARMEB-LABEL: add_and16:
590 ; ARMEB: add r1, r1, r2
591 ; ARMEB-NEXT: ldrh r0, [r0, #2]
592 ; ARMEB-NEXT: uxth r1, r1
685 ; ARMEB: @ %bb.0: @ %entry
686 ; ARMEB-NEXT: ldr r0, [r0]
687 ; ARMEB-NEXT: add r1, r1, r2
593688 ; ARMEB-NEXT: orr r0, r0, r1
689 ; ARMEB-NEXT: uxth r0, r0
594690 ; ARMEB-NEXT: bx lr
595691 ;
596692 ; THUMB1-LABEL: add_and16:
597 ; THUMB1: adds r1, r1, r2
598 ; THUMB1-NEXT: uxth r1, r1
599 ; THUMB1-NEXT: ldrh r0, [r0]
693 ; THUMB1: @ %bb.0: @ %entry
694 ; THUMB1-NEXT: adds r1, r1, r2
695 ; THUMB1-NEXT: ldr r0, [r0]
600696 ; THUMB1-NEXT: orrs r0, r1
697 ; THUMB1-NEXT: uxth r0, r0
601698 ; THUMB1-NEXT: bx lr
602699 ;
603700 ; THUMB2-LABEL: add_and16:
604 ; THUMB2: add r1, r2
605 ; THUMB2-NEXT: ldrh r0, [r0]
606 ; THUMB2-NEXT: uxth r1, r1
701 ; THUMB2: @ %bb.0: @ %entry
702 ; THUMB2-NEXT: ldr r0, [r0]
703 ; THUMB2-NEXT: add r1, r2
607704 ; THUMB2-NEXT: orrs r0, r1
705 ; THUMB2-NEXT: uxth r0, r0
608706 ; THUMB2-NEXT: bx lr
609707 entry:
610708 %x = load i32, i32* %a, align 4
616714
617715 define arm_aapcscc i32 @test1(i32* %a, i32* %b, i32 %x, i32 %y) {
618716 ; ARM-LABEL: test1:
619 ; ARM: mul r2, r2, r3
620 ; ARM-NEXT: ldrh r1, [r1]
621 ; ARM-NEXT: ldrh r0, [r0]
717 ; ARM: @ %bb.0: @ %entry
718 ; ARM-NEXT: mul r2, r2, r3
719 ; ARM-NEXT: ldr r1, [r1]
720 ; ARM-NEXT: ldr r0, [r0]
622721 ; ARM-NEXT: eor r0, r0, r1
623 ; ARM-NEXT: uxth r1, r2
624 ; ARM-NEXT: orr r0, r0, r1
722 ; ARM-NEXT: orr r0, r0, r2
723 ; ARM-NEXT: uxth r0, r0
625724 ; ARM-NEXT: bx lr
626725 ;
627726 ; ARMEB-LABEL: test1:
628 ; ARMEB: mul r2, r2, r3
629 ; ARMEB-NEXT: ldrh r1, [r1, #2]
630 ; ARMEB-NEXT: ldrh r0, [r0, #2]
727 ; ARMEB: @ %bb.0: @ %entry
728 ; ARMEB-NEXT: mul r2, r2, r3
729 ; ARMEB-NEXT: ldr r1, [r1]
730 ; ARMEB-NEXT: ldr r0, [r0]
631731 ; ARMEB-NEXT: eor r0, r0, r1
632 ; ARMEB-NEXT: uxth r1, r2
633 ; ARMEB-NEXT: orr r0, r0, r1
732 ; ARMEB-NEXT: orr r0, r0, r2
733 ; ARMEB-NEXT: uxth r0, r0
634734 ; ARMEB-NEXT: bx lr
635735 ;
636736 ; THUMB1-LABEL: test1:
637 ; THUMB1: ldrh r1, [r1]
638 ; THUMB1-NEXT: ldrh r4, [r0]
639 ; THUMB1-NEXT: eors r4, r1
737 ; THUMB1: @ %bb.0: @ %entry
640738 ; THUMB1-NEXT: muls r2, r3, r2
641 ; THUMB1-NEXT: uxth r0, r2
642 ; THUMB1-NEXT: orrs r0, r4
643 ; THUMB1-NEXT: pop
739 ; THUMB1-NEXT: ldr r1, [r1]
740 ; THUMB1-NEXT: ldr r0, [r0]
741 ; THUMB1-NEXT: eors r0, r1
742 ; THUMB1-NEXT: orrs r0, r2
743 ; THUMB1-NEXT: uxth r0, r0
744 ; THUMB1-NEXT: bx lr
644745 ;
645746 ; THUMB2-LABEL: test1:
646 ; THUMB2: ldrh r1, [r1]
647 ; THUMB2-NEXT: ldrh r0, [r0]
747 ; THUMB2: @ %bb.0: @ %entry
748 ; THUMB2-NEXT: muls r2, r3, r2
749 ; THUMB2-NEXT: ldr r1, [r1]
750 ; THUMB2-NEXT: ldr r0, [r0]
648751 ; THUMB2-NEXT: eors r0, r1
649 ; THUMB2-NEXT: mul r1, r2, r3
650 ; THUMB2-NEXT: uxth r1, r1
651 ; THUMB2-NEXT: orrs r0, r1
752 ; THUMB2-NEXT: orrs r0, r2
753 ; THUMB2-NEXT: uxth r0, r0
652754 ; THUMB2-NEXT: bx lr
653755 entry:
654756 %0 = load i32, i32* %a, align 4
662764
663765 define arm_aapcscc i32 @test2(i32* %a, i32* %b, i32 %x, i32 %y) {
664766 ; ARM-LABEL: test2:
665 ; ARM: ldr r1, [r1]
767 ; ARM: @ %bb.0: @ %entry
768 ; ARM-NEXT: ldr r1, [r1]
666769 ; ARM-NEXT: ldr r0, [r0]
667770 ; ARM-NEXT: mul r1, r2, r1
668771 ; ARM-NEXT: eor r0, r0, r3
671774 ; ARM-NEXT: bx lr
672775 ;
673776 ; ARMEB-LABEL: test2:
674 ; ARMEB: ldr r1, [r1]
777 ; ARMEB: @ %bb.0: @ %entry
778 ; ARMEB-NEXT: ldr r1, [r1]
675779 ; ARMEB-NEXT: ldr r0, [r0]
676780 ; ARMEB-NEXT: mul r1, r2, r1
677781 ; ARMEB-NEXT: eor r0, r0, r3
680784 ; ARMEB-NEXT: bx lr
681785 ;
682786 ; THUMB1-LABEL: test2:
683 ; THUMB1: ldr r1, [r1]
787 ; THUMB1: @ %bb.0: @ %entry
788 ; THUMB1-NEXT: ldr r1, [r1]
684789 ; THUMB1-NEXT: muls r1, r2, r1
685790 ; THUMB1-NEXT: ldr r0, [r0]
686791 ; THUMB1-NEXT: eors r0, r3
689794 ; THUMB1-NEXT: bx lr
690795 ;
691796 ; THUMB2-LABEL: test2:
692 ; THUMB2: ldr r1, [r1]
797 ; THUMB2: @ %bb.0: @ %entry
798 ; THUMB2-NEXT: ldr r1, [r1]
693799 ; THUMB2-NEXT: ldr r0, [r0]
694800 ; THUMB2-NEXT: muls r1, r2, r1
695801 ; THUMB2-NEXT: eors r0, r3
708814
709815 define arm_aapcscc i32 @test3(i32* %a, i32* %b, i32 %x, i16* %y) {
710816 ; ARM-LABEL: test3:
711 ; ARM: ldr r0, [r0]
817 ; ARM: @ %bb.0: @ %entry
818 ; ARM-NEXT: ldr r0, [r0]
712819 ; ARM-NEXT: mul r1, r2, r0
713820 ; ARM-NEXT: ldrh r2, [r3]
714821 ; ARM-NEXT: eor r0, r0, r2
717824 ; ARM-NEXT: bx lr
718825 ;
719826 ; ARMEB-LABEL: test3:
720 ; ARMEB: ldr r0, [r0]
827 ; ARMEB: @ %bb.0: @ %entry
828 ; ARMEB-NEXT: ldr r0, [r0]
721829 ; ARMEB-NEXT: mul r1, r2, r0
722830 ; ARMEB-NEXT: ldrh r2, [r3]
723831 ; ARMEB-NEXT: eor r0, r0, r2
726834 ; ARMEB-NEXT: bx lr
727835 ;
728836 ; THUMB1-LABEL: test3:
729 ; THUMB1: ldr r0, [r0]
837 ; THUMB1: @ %bb.0: @ %entry
838 ; THUMB1-NEXT: ldr r0, [r0]
730839 ; THUMB1-NEXT: muls r2, r0, r2
731840 ; THUMB1-NEXT: ldrh r1, [r3]
732841 ; THUMB1-NEXT: eors r1, r0
735844 ; THUMB1-NEXT: bx lr
736845 ;
737846 ; THUMB2-LABEL: test3:
738 ; THUMB2: ldr r0, [r0]
847 ; THUMB2: @ %bb.0: @ %entry
848 ; THUMB2-NEXT: ldr r0, [r0]
739849 ; THUMB2-NEXT: mul r1, r2, r0
740850 ; THUMB2-NEXT: ldrh r2, [r3]
741851 ; THUMB2-NEXT: eors r0, r2
755865
756866 define arm_aapcscc i32 @test4(i32* %a, i32* %b, i32 %x, i32 %y) {
757867 ; ARM-LABEL: test4:
758 ; ARM: mul r2, r2, r3
759 ; ARM-NEXT: ldrh r1, [r1]
760 ; ARM-NEXT: ldrh r0, [r0]
868 ; ARM: @ %bb.0: @ %entry
869 ; ARM-NEXT: mul r2, r2, r3
870 ; ARM-NEXT: ldr r1, [r1]
871 ; ARM-NEXT: ldr r0, [r0]
761872 ; ARM-NEXT: eor r0, r0, r1
762 ; ARM-NEXT: uxth r1, r2
763 ; ARM-NEXT: orr r0, r0, r1
873 ; ARM-NEXT: orr r0, r0, r2
874 ; ARM-NEXT: uxth r0, r0
764875 ; ARM-NEXT: bx lr
765876 ;
766877 ; ARMEB-LABEL: test4:
767 ; ARMEB: mul r2, r2, r3
768 ; ARMEB-NEXT: ldrh r1, [r1, #2]
769 ; ARMEB-NEXT: ldrh r0, [r0, #2]
878 ; ARMEB: @ %bb.0: @ %entry
879 ; ARMEB-NEXT: mul r2, r2, r3
880 ; ARMEB-NEXT: ldr r1, [r1]
881 ; ARMEB-NEXT: ldr r0, [r0]
770882 ; ARMEB-NEXT: eor r0, r0, r1
771 ; ARMEB-NEXT: uxth r1, r2
772 ; ARMEB-NEXT: orr r0, r0, r1
883 ; ARMEB-NEXT: orr r0, r0, r2
884 ; ARMEB-NEXT: uxth r0, r0
773885 ; ARMEB-NEXT: bx lr
774886 ;
775887 ; THUMB1-LABEL: test4:
776 ; THUMB1: ldrh r1, [r1]
777 ; THUMB1-NEXT: ldrh r4, [r0]
778 ; THUMB1-NEXT: eors r4, r1
888 ; THUMB1: @ %bb.0: @ %entry
779889 ; THUMB1-NEXT: muls r2, r3, r2
780 ; THUMB1-NEXT: uxth r0, r2
781 ; THUMB1-NEXT: orrs r0, r4
782 ; THUMB1-NEXT: pop
890 ; THUMB1-NEXT: ldr r1, [r1]
891 ; THUMB1-NEXT: ldr r0, [r0]
892 ; THUMB1-NEXT: eors r0, r1
893 ; THUMB1-NEXT: orrs r0, r2
894 ; THUMB1-NEXT: uxth r0, r0
895 ; THUMB1-NEXT: bx lr
783896 ;
784897 ; THUMB2-LABEL: test4:
785 ; THUMB2: ldrh r1, [r1]
786 ; THUMB2-NEXT: ldrh r0, [r0]
898 ; THUMB2: @ %bb.0: @ %entry
899 ; THUMB2-NEXT: muls r2, r3, r2
900 ; THUMB2-NEXT: ldr r1, [r1]
901 ; THUMB2-NEXT: ldr r0, [r0]
787902 ; THUMB2-NEXT: eors r0, r1
788 ; THUMB2-NEXT: mul r1, r2, r3
789 ; THUMB2-NEXT: uxth r1, r1
790 ; THUMB2-NEXT: orrs r0, r1
903 ; THUMB2-NEXT: orrs r0, r2
904 ; THUMB2-NEXT: uxth r0, r0
791905 ; THUMB2-NEXT: bx lr
792906 entry:
793907 %0 = load i32, i32* %a, align 4
801915
802916 define arm_aapcscc i32 @test5(i32* %a, i32* %b, i32 %x, i16 zeroext %y) {
803917 ; ARM-LABEL: test5:
804 ; ARM: ldr r1, [r1]
805 ; ARM-NEXT: ldrh r0, [r0]
918 ; ARM: @ %bb.0: @ %entry
919 ; ARM-NEXT: ldr r1, [r1]
920 ; ARM-NEXT: ldr r0, [r0]
806921 ; ARM-NEXT: mul r1, r2, r1
807922 ; ARM-NEXT: eor r0, r0, r3
808 ; ARM-NEXT: uxth r1, r1
809923 ; ARM-NEXT: orr r0, r0, r1
924 ; ARM-NEXT: uxth r0, r0
810925 ; ARM-NEXT: bx lr
811926 ;
812927 ; ARMEB-LABEL: test5:
813 ; ARMEB: ldr r1, [r1]
814 ; ARMEB-NEXT: ldrh r0, [r0, #2]
928 ; ARMEB: @ %bb.0: @ %entry
929 ; ARMEB-NEXT: ldr r1, [r1]
930 ; ARMEB-NEXT: ldr r0, [r0]
815931 ; ARMEB-NEXT: mul r1, r2, r1
816932 ; ARMEB-NEXT: eor r0, r0, r3
817 ; ARMEB-NEXT: uxth r1, r1
818933 ; ARMEB-NEXT: orr r0, r0, r1
934 ; ARMEB-NEXT: uxth r0, r0
819935 ; ARMEB-NEXT: bx lr
820936 ;
821937 ; THUMB1-LABEL: test5:
822 ; THUMB1: ldrh r4, [r0]
823 ; THUMB1-NEXT: eors r4, r3
824 ; THUMB1-NEXT: ldr r0, [r1]
825 ; THUMB1-NEXT: muls r0, r2, r0
938 ; THUMB1: @ %bb.0: @ %entry
939 ; THUMB1-NEXT: ldr r1, [r1]
940 ; THUMB1-NEXT: muls r1, r2, r1
941 ; THUMB1-NEXT: ldr r0, [r0]
942 ; THUMB1-NEXT: eors r0, r3
943 ; THUMB1-NEXT: orrs r0, r1
826944 ; THUMB1-NEXT: uxth r0, r0
827 ; THUMB1-NEXT: orrs r0, r4
828 ; THUMB1-NEXT: pop
945 ; THUMB1-NEXT: bx lr
829946 ;
830947 ; THUMB2-LABEL: test5:
831 ; THUMB2: ldr r1, [r1]
832 ; THUMB2-NEXT: ldrh r0, [r0]
948 ; THUMB2: @ %bb.0: @ %entry
949 ; THUMB2-NEXT: ldr r1, [r1]
950 ; THUMB2-NEXT: ldr r0, [r0]
833951 ; THUMB2-NEXT: muls r1, r2, r1
834952 ; THUMB2-NEXT: eors r0, r3
835 ; THUMB2-NEXT: uxth r1, r1
836953 ; THUMB2-NEXT: orrs r0, r1
954 ; THUMB2-NEXT: uxth r0, r0
837955 ; THUMB2-NEXT: bx lr
838956 entry:
839957 %0 = load i32, i32* %a, align 4
845963 %and = and i32 %or, 65535
846964 ret i32 %and
847965 }
848
849 define arm_aapcscc i1 @test6(i8* %x, i8 %y, i8 %z) {
850 ; ARM-LABEL: test6:
851 ; ARM: ldrb r0, [r0]
852 ; ARM: uxtb r2, r2
853 ; ARM: and r0, r0, r1
854 ; ARM: uxtb r1, r0
855
856 ; ARMEB-LABEL: test6:
857 ; ARMEB: ldrb r0, [r0]
858 ; ARMEB: uxtb r2, r2
859 ; ARMEB: and r0, r0, r1
860 ; ARMEB: uxtb r1, r0
861
862 ; THUMB1-LABEL: test6:
863 ; THUMB1: ldrb r0, [r0]
864 ; THUMB1: ands r0, r1
865 ; THUMB1: uxtb r3, r0
866 ; THUMB1: uxtb r2, r2
867
868 ; THUMB2-LABEL: test6:
869 ; THUMB2: ldrb r0, [r0]
870 ; THUMB2: uxtb r2, r2
871 ; THUMB2: ands r0, r1
872 ; THUMB2: uxtb r1, r0
873 entry:
874 %0 = load i8, i8* %x, align 4
875 %1 = and i8 %0, %y
876 %2 = icmp eq i8 %1, %z
877 ret i1 %2
878 }
879
880 define arm_aapcscc i1 @test7(i16* %x, i16 %y, i8 %z) {
881 ; ARM-LABEL: test7:
882 ; ARM: ldrb r0, [r0]
883 ; ARM: uxtb r2, r2
884 ; ARM: and r1, r0, r1
885
886 ; ARMEB-LABEL: test7:
887 ; ARMEB: ldrb r0, [r0, #1]
888 ; ARMEB: uxtb r2, r2
889 ; ARMEB: and r1, r0, r1
890
891 ; THUMB1-LABEL: test7:
892 ; THUMB1: ldrb r3, [r0]
893 ; THUMB1: ands r3, r1
894 ; THUMB1: uxtb r2, r2
895
896 ; THUMB2-LABEL: test7:
897 ; THUMB2: ldrb r0, [r0]
898 ; THUMB2: uxtb r2, r2
899 ; THUMB2: ands r1, r0
900 entry:
901 %0 = load i16, i16* %x, align 4
902 %1 = and i16 %0, %y
903 %2 = trunc i16 %1 to i8
904 %3 = icmp eq i8 %2, %z
905 ret i1 %3
906 }
907