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Merging r318788: ------------------------------------------------------------------------ r318788 | mcrosier | 2017-11-21 10:08:34 -0800 (Tue, 21 Nov 2017) | 16 lines [AArch64] Mark mrs of TPIDR_EL0 (thread pointer) as *having* side effects. This partially reverts r298851. The the underlying issue is that we don't currently model the dependency between mrs (read system register) and msr (write system register) instructions. Something like the below should never be reordered: msr TPIDR_EL0, x0 ;; set thread pointer mrs x8, TPIDR_EL0 ;; read thread pointer but was being reordered after r298851. The functional part of the patch that wasn't reverted needed to remain in place in order to not break r299462. PR35317 ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_50@318854 91177308-0d34-0410-b5e6-96231b3b80d8 Tom Stellard 1 year, 8 months ago
2 changed file(s) with 1 addition(s) and 62 deletion(s). Raw diff Collapse all Expand all
440440 def MSRpstateImm4 : MSRpstateImm0_15;
441441
442442 // The thread pointer (on Linux, at least, where this has been implemented) is
443 // TPIDR_EL0. Add pseudo op so we can mark it as not having any side effects.
444 let hasSideEffects = 0 in
443 // TPIDR_EL0.
445444 def MOVbaseTLS : Pseudo<(outs GPR64:$dst), (ins),
446445 [(set GPR64:$dst, AArch64threadpointer)]>, Sched<[WriteSys]>;
447446
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test/CodeGen/AArch64/thread-pointer.ll less more
None ; RUN: llc -mtriple=aarch64-linux-gnu -verify-machineinstrs -o - %s | FileCheck %s
1
2 @x = thread_local local_unnamed_addr global i32 0, align 4
3 @y = thread_local local_unnamed_addr global i32 0, align 4
4
5 ; Machine LICM should hoist the mrs into the loop preheader.
6 ; CHECK-LABEL: @test1
7 ; CHECK: BB#1:
8 ; CHECK: mrs x[[BASE:[0-9]+]], TPIDR_EL0
9 ; CHECK: add x[[REG1:[0-9]+]], x[[BASE]], :tprel_hi12:x
10 ; CHECK: add x[[REG2:[0-9]+]], x[[REG1]], :tprel_lo12_nc:x
11 ;
12 ; CHECK: .LBB0_2:
13 ; CHECK: ldr w0, [x[[REG2]]]
14 ; CHECK: bl bar
15 ; CHECK: subs w[[REG3:[0-9]+]], w{{[0-9]+}}, #1
16 ; CHECK: b.ne .LBB0_2
17
18 define void @test1(i32 %n) local_unnamed_addr {
19 entry:
20 %cmp3 = icmp sgt i32 %n, 0
21 br i1 %cmp3, label %bb1, label %bb2
22
23 bb1:
24 br label %for.body
25
26 for.body:
27 %i.04 = phi i32 [ %inc, %for.body ], [ 0, %bb1 ]
28 %0 = load i32, i32* @x, align 4
29 tail call void @bar(i32 %0) #2
30 %inc = add nuw nsw i32 %i.04, 1
31 %exitcond = icmp eq i32 %inc, %n
32 br i1 %exitcond, label %bb2, label %for.body
33
34 bb2:
35 ret void
36 }
37
38 ; Machine CSE should combine the the mrs between the load of %x and %y.
39 ; CHECK-LABEL: @test2
40 ; CHECK: mrs x{{[0-9]+}}, TPIDR_EL0
41 ; CHECK-NOT: mrs x{{[0-9]+}}, TPIDR_EL0
42 ; CHECK: ret
43 define void @test2(i32 %c) local_unnamed_addr #0 {
44 entry:
45 %0 = load i32, i32* @x, align 4
46 tail call void @bar(i32 %0) #2
47 %cmp = icmp eq i32 %c, 0
48 br i1 %cmp, label %if.end, label %if.then
49
50 if.then:
51 %1 = load i32, i32* @y, align 4
52 tail call void @bar(i32 %1) #2
53 br label %if.end
54
55 if.end:
56 ret void
57 }
58
59 declare void @bar(i32) local_unnamed_addr