llvm.org GIT mirror llvm / f2cfb7b
[RISCV] Do a sign-extension in a compare-and-swap of 32 bit in RV64A AtomicCmpSwapWithSuccess is legalised into an AtomicCmpSwap plus a comparison. This requires an extension of the value which, by default, is a zero-extension. When we later lower AtomicCmpSwap into a PseudoCmpXchg32 and then expanded in RISCVExpandPseudoInsts.cpp, the lr.w instruction does a sign-extension. This mismatch of extensions causes the comparison to fail when the compared value is negative. This change overrides TargetLowering::getExtendForAtomicOps for RISC-V so it does a sign-extension instead. Differential Revision: https://reviews.llvm.org/D58829 Patch by Ferran Pallarès Roca. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@355869 91177308-0d34-0410-b5e6-96231b3b80d8 Alex Bradbury 1 year, 8 months ago
2 changed file(s) with 33 addition(s) and 0 deletion(s). Raw diff Collapse all Expand all
105105 Instruction *emitTrailingFence(IRBuilder<> &Builder, Instruction *Inst,
106106 AtomicOrdering Ord) const override;
107107
108 ISD::NodeType getExtendForAtomicOps() const override {
109 return ISD::SIGN_EXTEND;
110 }
111
108112 private:
109113 void analyzeInputArgs(MachineFunction &MF, CCState &CCInfo,
110114 const SmallVectorImpl &Ins,
0 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
1 ; RUN: llc -mtriple=riscv64 -mattr=+a -verify-machineinstrs < %s \
2 ; RUN: | FileCheck -check-prefix=RV64IA %s
3
4 ; This test ensures that the output of the 'lr.w' instruction is sign-extended.
5 ; Previously, the default zero-extension was being used and 'cmp' parameter
6 ; higher bits were masked to zero for the comparison.
7
8 define i1 @cmpxchg_i32_seq_cst_seq_cst(i32* %ptr, i32 signext %cmp,
9 i32 signext %val) {
10 ; RV64IA-LABEL: cmpxchg_i32_seq_cst_seq_cst:
11 ; RV64IA: # %bb.0: # %entry
12 ; RV64IA-NEXT: .LBB0_1: # %entry
13 ; RV64IA-NEXT: # =>This Inner Loop Header: Depth=1
14 ; RV64IA-NEXT: lr.w.aqrl a3, (a0)
15 ; RV64IA-NEXT: bne a3, a1, .LBB0_3
16 ; RV64IA-NEXT: # %bb.2: # %entry
17 ; RV64IA-NEXT: # in Loop: Header=BB0_1 Depth=1
18 ; RV64IA-NEXT: sc.w.aqrl a4, a2, (a0)
19 ; RV64IA-NEXT: bnez a4, .LBB0_1
20 ; RV64IA-NEXT: .LBB0_3: # %entry
21 ; RV64IA-NEXT: xor a0, a3, a1
22 ; RV64IA-NEXT: seqz a0, a0
23 ; RV64IA-NEXT: ret
24 entry:
25 %0 = cmpxchg i32* %ptr, i32 %cmp, i32 %val seq_cst seq_cst
26 %1 = extractvalue { i32, i1 } %0, 1
27 ret i1 %1
28 }