llvm.org GIT mirror llvm / f2c9fef
[C++11] Add 'override' keyword to virtual methods that override their base class. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@203378 91177308-0d34-0410-b5e6-96231b3b80d8 Craig Topper 6 years ago
21 changed file(s) with 348 addition(s) and 344 deletion(s). Raw diff Collapse all Expand all
2525 const MCRegisterInfo &MRI)
2626 : MCInstPrinter(MAI, MII, MRI) {}
2727
28 virtual void printRegName(raw_ostream &OS, unsigned RegNo) const;
29 virtual void printInst(const MCInst *MI, raw_ostream &OS, StringRef Annot);
28 void printRegName(raw_ostream &OS, unsigned RegNo) const override;
29 void printInst(const MCInst *MI, raw_ostream &OS, StringRef Annot) override;
3030
3131 // Autogenerated by tblgen, returns true if we successfully printed an
3232 // alias.
5555 MCE(mce), PICBaseOffset(0), Is64BitMode(false),
5656 IsPIC(TM.getRelocationModel() == Reloc::PIC_) {}
5757
58 bool runOnMachineFunction(MachineFunction &MF);
59
60 virtual const char *getPassName() const {
58 bool runOnMachineFunction(MachineFunction &MF) override;
59
60 const char *getPassName() const override {
6161 return "X86 Machine Code Emitter";
6262 }
6363
7575
7676 void emitInstruction(MachineInstr &MI, const MCInstrDesc *Desc);
7777
78 void getAnalysisUsage(AnalysisUsage &AU) const {
78 void getAnalysisUsage(AnalysisUsage &AU) const override {
7979 AU.setPreservesAll();
8080 AU.addRequired();
8181 MachineFunctionPass::getAnalysisUsage(AU);
6161 X86ScalarSSEf32 = Subtarget->hasSSE1();
6262 }
6363
64 virtual bool TargetSelectInstruction(const Instruction *I);
64 bool TargetSelectInstruction(const Instruction *I) override;
6565
6666 /// \brief The specified machine instr operand is a vreg, and that
6767 /// vreg is being provided by the specified load instruction. If possible,
6868 /// try to fold the load as an operand to the instruction, returning true if
6969 /// possible.
70 virtual bool tryToFoldLoadIntoMI(MachineInstr *MI, unsigned OpNo,
71 const LoadInst *LI);
72
73 virtual bool FastLowerArguments();
70 bool tryToFoldLoadIntoMI(MachineInstr *MI, unsigned OpNo,
71 const LoadInst *LI) override;
72
73 bool FastLowerArguments() override;
7474
7575 #include "X86GenFastISel.inc"
7676
127127
128128 bool handleConstantAddresses(const Value *V, X86AddressMode &AM);
129129
130 unsigned TargetMaterializeConstant(const Constant *C);
131
132 unsigned TargetMaterializeAlloca(const AllocaInst *C);
133
134 unsigned TargetMaterializeFloatZero(const ConstantFP *CF);
130 unsigned TargetMaterializeConstant(const Constant *C) override;
131
132 unsigned TargetMaterializeAlloca(const AllocaInst *C) override;
133
134 unsigned TargetMaterializeFloatZero(const ConstantFP *CF) override;
135135
136136 /// isScalarFPTypeInSSEReg - Return true if the specified scalar FP type is
137137 /// computed in an SSE register, not on the X87 floating point stack.
3838 /// where appropriate.
3939 bool processBasicBlock(MachineFunction &MF, MachineFunction::iterator MFI);
4040
41 virtual const char *getPassName() const { return "X86 Atom LEA Fixup";}
41 const char *getPassName() const override { return "X86 Atom LEA Fixup";}
4242
4343 /// \brief Given a machine register, look for the instruction
4444 /// which writes it in the current basic block. If found,
7979 /// \brief Loop over all of the basic blocks,
8080 /// replacing instructions by equivalent LEA instructions
8181 /// if needed and when possible.
82 virtual bool runOnMachineFunction(MachineFunction &MF);
82 bool runOnMachineFunction(MachineFunction &MF) override;
8383
8484 private:
8585 MachineFunction *MF;
5858 memset(RegMap, 0, sizeof(RegMap));
5959 }
6060
61 virtual void getAnalysisUsage(AnalysisUsage &AU) const {
61 void getAnalysisUsage(AnalysisUsage &AU) const override {
6262 AU.setPreservesCFG();
6363 AU.addRequired();
6464 AU.addPreservedID(MachineLoopInfoID);
6666 MachineFunctionPass::getAnalysisUsage(AU);
6767 }
6868
69 virtual bool runOnMachineFunction(MachineFunction &MF);
70
71 virtual const char *getPassName() const { return "X86 FP Stackifier"; }
69 bool runOnMachineFunction(MachineFunction &MF) override;
70
71 const char *getPassName() const override { return "X86 FP Stackifier"; }
7272
7373 private:
7474 const TargetInstrInfo *TII; // Machine instruction info.
3939
4040 /// emitProlog/emitEpilog - These methods insert prolog and epilog code into
4141 /// the function.
42 void emitPrologue(MachineFunction &MF) const;
43 void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const;
42 void emitPrologue(MachineFunction &MF) const override;
43 void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const override;
4444
45 void adjustForSegmentedStacks(MachineFunction &MF) const;
45 void adjustForSegmentedStacks(MachineFunction &MF) const override;
4646
47 void adjustForHiPEPrologue(MachineFunction &MF) const;
47 void adjustForHiPEPrologue(MachineFunction &MF) const override;
4848
4949 void processFunctionBeforeCalleeSavedScan(MachineFunction &MF,
50 RegScavenger *RS = NULL) const;
50 RegScavenger *RS = NULL) const override;
5151
5252 bool spillCalleeSavedRegisters(MachineBasicBlock &MBB,
5353 MachineBasicBlock::iterator MI,
5454 const std::vector &CSI,
55 const TargetRegisterInfo *TRI) const;
55 const TargetRegisterInfo *TRI) const override;
5656
5757 bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
58 MachineBasicBlock::iterator MI,
59 const std::vector &CSI,
60 const TargetRegisterInfo *TRI) const;
58 MachineBasicBlock::iterator MI,
59 const std::vector &CSI,
60 const TargetRegisterInfo *TRI) const override;
6161
62 bool hasFP(const MachineFunction &MF) const;
63 bool hasReservedCallFrame(const MachineFunction &MF) const;
62 bool hasFP(const MachineFunction &MF) const override;
63 bool hasReservedCallFrame(const MachineFunction &MF) const override;
6464
65 int getFrameIndexOffset(const MachineFunction &MF, int FI) const;
65 int getFrameIndexOffset(const MachineFunction &MF, int FI) const override;
6666 int getFrameIndexReference(const MachineFunction &MF, int FI,
67 unsigned &FrameReg) const;
67 unsigned &FrameReg) const override;
6868
6969 void eliminateCallFramePseudoInstr(MachineFunction &MF,
70 MachineBasicBlock &MBB,
71 MachineBasicBlock::iterator MI) const;
70 MachineBasicBlock &MBB,
71 MachineBasicBlock::iterator MI) const override;
7272 };
7373
7474 } // End llvm namespace
155155 Subtarget(&tm.getSubtarget()),
156156 OptForSize(false) {}
157157
158 virtual const char *getPassName() const {
158 const char *getPassName() const override {
159159 return "X86 DAG->DAG Instruction Selection";
160160 }
161161
162 virtual void EmitFunctionEntryCode();
163
164 virtual bool IsProfitableToFold(SDValue N, SDNode *U, SDNode *Root) const;
165
166 virtual void PreprocessISelDAG();
162 void EmitFunctionEntryCode() override;
163
164 bool IsProfitableToFold(SDValue N, SDNode *U, SDNode *Root) const override;
165
166 void PreprocessISelDAG() override;
167167
168168 inline bool immSext8(SDNode *N) const {
169169 return isInt<8>(cast(N)->getSExtValue());
180180 #include "X86GenDAGISel.inc"
181181
182182 private:
183 SDNode *Select(SDNode *N);
183 SDNode *Select(SDNode *N) override;
184184 SDNode *SelectGather(SDNode *N, unsigned Opc);
185185 SDNode *SelectAtomic64(SDNode *Node, unsigned Opc);
186186 SDNode *SelectAtomicLoadArith(SDNode *Node, MVT NVT);
218218
219219 /// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
220220 /// inline asm expressions.
221 virtual bool SelectInlineAsmMemoryOperand(const SDValue &Op,
222 char ConstraintCode,
223 std::vector &OutOps);
221 bool SelectInlineAsmMemoryOperand(const SDValue &Op,
222 char ConstraintCode,
223 std::vector &OutOps) override;
224224
225225 void EmitSpecialCodeForMain(MachineBasicBlock *BB, MachineFrameInfo *MFI);
226226
525525 public:
526526 explicit X86TargetLowering(X86TargetMachine &TM);
527527
528 virtual unsigned getJumpTableEncoding() const;
529
530 virtual MVT getScalarShiftAmountTy(EVT LHSTy) const { return MVT::i8; }
531
532 virtual const MCExpr *
528 unsigned getJumpTableEncoding() const override;
529
530 MVT getScalarShiftAmountTy(EVT LHSTy) const override { return MVT::i8; }
531
532 const MCExpr *
533533 LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI,
534534 const MachineBasicBlock *MBB, unsigned uid,
535 MCContext &Ctx) const;
535 MCContext &Ctx) const override;
536536
537537 /// getPICJumpTableRelocaBase - Returns relocation base for the given PIC
538538 /// jumptable.
539 virtual SDValue getPICJumpTableRelocBase(SDValue Table,
540 SelectionDAG &DAG) const;
541 virtual const MCExpr *
539 SDValue getPICJumpTableRelocBase(SDValue Table,
540 SelectionDAG &DAG) const override;
541 const MCExpr *
542542 getPICJumpTableRelocBaseExpr(const MachineFunction *MF,
543 unsigned JTI, MCContext &Ctx) const;
543 unsigned JTI, MCContext &Ctx) const override;
544544
545545 /// getByValTypeAlignment - Return the desired alignment for ByVal aggregate
546546 /// function arguments in the caller parameter area. For X86, aggregates
547547 /// that contains are placed at 16-byte boundaries while the rest are at
548548 /// 4-byte boundaries.
549 virtual unsigned getByValTypeAlignment(Type *Ty) const;
549 unsigned getByValTypeAlignment(Type *Ty) const override;
550550
551551 /// getOptimalMemOpType - Returns the target specific optimal type for load
552552 /// and store operations as a result of memset, memcpy, and memmove
559559 /// source is constant so it does not need to be loaded.
560560 /// It returns EVT::Other if the type should be determined using generic
561561 /// target-independent logic.
562 virtual EVT
563 getOptimalMemOpType(uint64_t Size, unsigned DstAlign, unsigned SrcAlign,
564 bool IsMemset, bool ZeroMemset, bool MemcpyStrSrc,
565 MachineFunction &MF) const;
562 EVT getOptimalMemOpType(uint64_t Size, unsigned DstAlign, unsigned SrcAlign,
563 bool IsMemset, bool ZeroMemset, bool MemcpyStrSrc,
564 MachineFunction &MF) const override;
566565
567566 /// isSafeMemOpType - Returns true if it's safe to use load / store of the
568567 /// specified type to expand memcpy / memset inline. This is mostly true
570569 /// targets without SSE2 f64 load / store are done with fldl / fstpl which
571570 /// also does type conversion. Note the specified type doesn't have to be
572571 /// legal as the hook is used before type legalization.
573 virtual bool isSafeMemOpType(MVT VT) const;
572 bool isSafeMemOpType(MVT VT) const override;
574573
575574 /// allowsUnalignedMemoryAccesses - Returns true if the target allows
576575 /// unaligned memory accesses. of the specified type. Returns whether it
577576 /// is "fast" by reference in the second argument.
578 virtual bool allowsUnalignedMemoryAccesses(EVT VT, unsigned AS,
579 bool *Fast) const;
577 bool allowsUnalignedMemoryAccesses(EVT VT, unsigned AS,
578 bool *Fast) const override;
580579
581580 /// LowerOperation - Provide custom lowering hooks for some operations.
582581 ///
583 virtual SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const;
582 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
584583
585584 /// ReplaceNodeResults - Replace the results of node with an illegal result
586585 /// type with new values built out of custom code.
587586 ///
588 virtual void ReplaceNodeResults(SDNode *N, SmallVectorImpl&Results,
589 SelectionDAG &DAG) const;
590
591
592 virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const;
587 void ReplaceNodeResults(SDNode *N, SmallVectorImpl&Results,
588 SelectionDAG &DAG) const override;
589
590
591 SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
593592
594593 /// isTypeDesirableForOp - Return true if the target has native support for
595594 /// the specified value type and it is 'desirable' to use the type for the
596595 /// given node type. e.g. On x86 i16 is legal, but undesirable since i16
597596 /// instruction encodings are longer and some i16 instructions are slow.
598 virtual bool isTypeDesirableForOp(unsigned Opc, EVT VT) const;
597 bool isTypeDesirableForOp(unsigned Opc, EVT VT) const override;
599598
600599 /// isTypeDesirable - Return true if the target has native support for the
601600 /// specified value type and it is 'desirable' to use the type. e.g. On x86
602601 /// i16 is legal, but undesirable since i16 instruction encodings are longer
603602 /// and some i16 instructions are slow.
604 virtual bool IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const;
605
606 virtual MachineBasicBlock *
603 bool IsDesirableToPromoteOp(SDValue Op, EVT &PVT) const override;
604
605 MachineBasicBlock *
607606 EmitInstrWithCustomInserter(MachineInstr *MI,
608 MachineBasicBlock *MBB) const;
607 MachineBasicBlock *MBB) const override;
609608
610609
611610 /// getTargetNodeName - This method returns the name of a target specific
612611 /// DAG node.
613 virtual const char *getTargetNodeName(unsigned Opcode) const;
612 const char *getTargetNodeName(unsigned Opcode) const override;
614613
615614 /// getSetCCResultType - Return the value type to use for ISD::SETCC.
616 virtual EVT getSetCCResultType(LLVMContext &Context, EVT VT) const;
615 EVT getSetCCResultType(LLVMContext &Context, EVT VT) const override;
617616
618617 /// computeMaskedBitsForTargetNode - Determine which of the bits specified
619618 /// in Mask are known to be either zero or one and return them in the
620619 /// KnownZero/KnownOne bitsets.
621 virtual void computeMaskedBitsForTargetNode(const SDValue Op,
622 APInt &KnownZero,
623 APInt &KnownOne,
624 const SelectionDAG &DAG,
625 unsigned Depth = 0) const;
620 void computeMaskedBitsForTargetNode(const SDValue Op,
621 APInt &KnownZero,
622 APInt &KnownOne,
623 const SelectionDAG &DAG,
624 unsigned Depth = 0) const override;
626625
627626 // ComputeNumSignBitsForTargetNode - Determine the number of bits in the
628627 // operation that are sign bits.
629 virtual unsigned ComputeNumSignBitsForTargetNode(SDValue Op,
630 unsigned Depth) const;
631
632 virtual bool
633 isGAPlusOffset(SDNode *N, const GlobalValue* &GA, int64_t &Offset) const;
628 unsigned ComputeNumSignBitsForTargetNode(SDValue Op,
629 unsigned Depth) const override;
630
631 bool isGAPlusOffset(SDNode *N, const GlobalValue* &GA,
632 int64_t &Offset) const override;
634633
635634 SDValue getReturnAddressFrameIndex(SelectionDAG &DAG) const;
636635
637 virtual bool ExpandInlineAsm(CallInst *CI) const;
638
639 ConstraintType getConstraintType(const std::string &Constraint) const;
636 bool ExpandInlineAsm(CallInst *CI) const override;
637
638 ConstraintType
639 getConstraintType(const std::string &Constraint) const override;
640640
641641 /// Examine constraint string and operand type and determine a weight value.
642642 /// The operand object must already have been set up with the operand type.
643 virtual ConstraintWeight getSingleConstraintMatchWeight(
644 AsmOperandInfo &info, const char *constraint) const;
645
646 virtual const char *LowerXConstraint(EVT ConstraintVT) const;
643 ConstraintWeight
644 getSingleConstraintMatchWeight(AsmOperandInfo &info,
645 const char *constraint) const override;
646
647 const char *LowerXConstraint(EVT ConstraintVT) const override;
647648
648649 /// LowerAsmOperandForConstraint - Lower the specified operand into the Ops
649650 /// vector. If it is invalid, don't add anything to Ops. If hasMemory is
650651 /// true it means one of the asm constraint of the inline asm instruction
651652 /// being processed is 'm'.
652 virtual void LowerAsmOperandForConstraint(SDValue Op,
653 std::string &Constraint,
654 std::vector &Ops,
655 SelectionDAG &DAG) const;
653 void LowerAsmOperandForConstraint(SDValue Op,
654 std::string &Constraint,
655 std::vector &Ops,
656 SelectionDAG &DAG) const override;
656657
657658 /// getRegForInlineAsmConstraint - Given a physical register constraint
658659 /// (e.g. {edx}), return the register number and the register class for the
660661 /// error, this returns a register number of 0.
661662 std::pair
662663 getRegForInlineAsmConstraint(const std::string &Constraint,
663 MVT VT) const;
664 MVT VT) const override;
664665
665666 /// isLegalAddressingMode - Return true if the addressing mode represented
666667 /// by AM is legal for this target, for a load/store of the specified type.
667 virtual bool isLegalAddressingMode(const AddrMode &AM, Type *Ty)const;
668 bool isLegalAddressingMode(const AddrMode &AM, Type *Ty) const override;
668669
669670 /// isLegalICmpImmediate - Return true if the specified immediate is legal
670671 /// icmp immediate, that is the target has icmp instructions which can
671672 /// compare a register against the immediate without having to materialize
672673 /// the immediate into a register.
673 virtual bool isLegalICmpImmediate(int64_t Imm) const;
674 bool isLegalICmpImmediate(int64_t Imm) const override;
674675
675676 /// isLegalAddImmediate - Return true if the specified immediate is legal
676677 /// add immediate, that is the target has add instructions which can
677678 /// add a register and the immediate without having to materialize
678679 /// the immediate into a register.
679 virtual bool isLegalAddImmediate(int64_t Imm) const;
680
681
682 virtual bool isVectorShiftByScalarCheap(Type *Ty) const;
680 bool isLegalAddImmediate(int64_t Imm) const override;
681
682
683 bool isVectorShiftByScalarCheap(Type *Ty) const override;
683684
684685 /// isTruncateFree - Return true if it's free to truncate a value of
685686 /// type Ty1 to type Ty2. e.g. On x86 it's free to truncate a i32 value in
686687 /// register EAX to i16 by referencing its sub-register AX.
687 virtual bool isTruncateFree(Type *Ty1, Type *Ty2) const;
688 virtual bool isTruncateFree(EVT VT1, EVT VT2) const;
689
690 virtual bool allowTruncateForTailCall(Type *Ty1, Type *Ty2) const;
688 bool isTruncateFree(Type *Ty1, Type *Ty2) const override;
689 bool isTruncateFree(EVT VT1, EVT VT2) const override;
690
691 bool allowTruncateForTailCall(Type *Ty1, Type *Ty2) const override;
691692
692693 /// isZExtFree - Return true if any actual instruction that defines a
693694 /// value of type Ty1 implicit zero-extends the value to Ty2 in the result
697698 /// does not necessarily apply to truncate instructions. e.g. on x86-64,
698699 /// all instructions that define 32-bit values implicit zero-extend the
699700 /// result out to 64 bits.
700 virtual bool isZExtFree(Type *Ty1, Type *Ty2) const;
701 virtual bool isZExtFree(EVT VT1, EVT VT2) const;
702 virtual bool isZExtFree(SDValue Val, EVT VT2) const;
701 bool isZExtFree(Type *Ty1, Type *Ty2) const override;
702 bool isZExtFree(EVT VT1, EVT VT2) const override;
703 bool isZExtFree(SDValue Val, EVT VT2) const override;
703704
704705 /// isFMAFasterThanFMulAndFAdd - Return true if an FMA operation is faster
705706 /// than a pair of fmul and fadd instructions. fmuladd intrinsics will be
706707 /// expanded to FMAs when this method returns true, otherwise fmuladd is
707708 /// expanded to fmul + fadd.
708 virtual bool isFMAFasterThanFMulAndFAdd(EVT VT) const;
709 bool isFMAFasterThanFMulAndFAdd(EVT VT) const override;
709710
710711 /// isNarrowingProfitable - Return true if it's profitable to narrow
711712 /// operations of type VT1 to VT2. e.g. on x86, it's profitable to narrow
712713 /// from i32 to i8 but not from i32 to i16.
713 virtual bool isNarrowingProfitable(EVT VT1, EVT VT2) const;
714 bool isNarrowingProfitable(EVT VT1, EVT VT2) const override;
714715
715716 /// isFPImmLegal - Returns true if the target can instruction select the
716717 /// specified FP immediate natively. If false, the legalizer will
717718 /// materialize the FP immediate as a load from a constant pool.
718 virtual bool isFPImmLegal(const APFloat &Imm, EVT VT) const;
719 bool isFPImmLegal(const APFloat &Imm, EVT VT) const override;
719720
720721 /// isShuffleMaskLegal - Targets can use this to indicate that they only
721722 /// support *some* VECTOR_SHUFFLE operations, those with specific masks.
722723 /// By default, if a target supports the VECTOR_SHUFFLE node, all mask
723724 /// values are assumed to be legal.
724 virtual bool isShuffleMaskLegal(const SmallVectorImpl &Mask,
725 EVT VT) const;
725 bool isShuffleMaskLegal(const SmallVectorImpl &Mask,
726 EVT VT) const override;
726727
727728 /// isVectorClearMaskLegal - Similar to isShuffleMaskLegal. This is
728729 /// used by Targets can use this to indicate if there is a suitable
729730 /// VECTOR_SHUFFLE that can be used to replace a VAND with a constant
730731 /// pool entry.
731 virtual bool isVectorClearMaskLegal(const SmallVectorImpl &Mask,
732 EVT VT) const;
732 bool isVectorClearMaskLegal(const SmallVectorImpl &Mask,
733 EVT VT) const override;
733734
734735 /// ShouldShrinkFPConstant - If true, then instruction selection should
735736 /// seek to shrink the FP constant of the specified type to a smaller type
736737 /// in order to save space and / or reduce runtime.
737 virtual bool ShouldShrinkFPConstant(EVT VT) const {
738 bool ShouldShrinkFPConstant(EVT VT) const override {
738739 // Don't shrink FP constpool if SSE2 is available since cvtss2sd is more
739740 // expensive than a straight movsd. On the other hand, it's important to
740741 // shrink long double fp constant since fldt is very slow.
766767
767768 /// \brief Returns true if it is beneficial to convert a load of a constant
768769 /// to just the constant itself.
769 virtual bool shouldConvertConstantLoadToIntImm(const APInt &Imm,
770 Type *Ty) const;
770 bool shouldConvertConstantLoadToIntImm(const APInt &Imm,
771 Type *Ty) const override;
771772
772773 /// createFastISel - This method returns a target specific FastISel object,
773774 /// or null if the target does not support "fast" ISel.
774 virtual FastISel *createFastISel(FunctionLoweringInfo &funcInfo,
775 const TargetLibraryInfo *libInfo) const;
775 FastISel *createFastISel(FunctionLoweringInfo &funcInfo,
776 const TargetLibraryInfo *libInfo) const override;
776777
777778 /// getStackCookieLocation - Return true if the target stores stack
778779 /// protector cookies at a fixed offset in some non-standard address
779780 /// space, and populates the address space and offset as
780781 /// appropriate.
781 virtual bool getStackCookieLocation(unsigned &AddressSpace, unsigned &Offset) const;
782 bool getStackCookieLocation(unsigned &AddressSpace,
783 unsigned &Offset) const override;
782784
783785 SDValue BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain, SDValue StackSlot,
784786 SelectionDAG &DAG) const;
785787
786 virtual bool isNoopAddrSpaceCast(unsigned SrcAS,
787 unsigned DestAS) const override;
788 bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const override;
788789
789790 /// \brief Reset the operation actions based on target options.
790 virtual void resetOperationActions();
791 void resetOperationActions() override;
791792
792793 protected:
793794 std::pair
794 findRepresentativeClass(MVT VT) const;
795 findRepresentativeClass(MVT VT) const override;
795796
796797 private:
797798 /// Subtarget - Keep a pointer to the X86Subtarget around so that we can
903904 SDValue LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG) const;
904905 SDValue LowerSIGN_EXTEND_INREG(SDValue Op, SelectionDAG &DAG) const;
905906
906 virtual SDValue
907 SDValue
907908 LowerFormalArguments(SDValue Chain,
908909 CallingConv::ID CallConv, bool isVarArg,
909910 const SmallVectorImpl &Ins,
910911 SDLoc dl, SelectionDAG &DAG,
911 SmallVectorImpl &InVals) const;
912 virtual SDValue
913 LowerCall(CallLoweringInfo &CLI,
914 SmallVectorImpl &InVals) const;
915
916 virtual SDValue
917 LowerReturn(SDValue Chain,
918 CallingConv::ID CallConv, bool isVarArg,
919 const SmallVectorImpl &Outs,
920 const SmallVectorImpl &OutVals,
921 SDLoc dl, SelectionDAG &DAG) const;
922
923 virtual bool isUsedByReturnOnly(SDNode *N, SDValue &Chain) const;
924
925 virtual bool mayBeEmittedAsTailCall(CallInst *CI) const;
926
927 virtual MVT
928 getTypeForExtArgOrReturn(MVT VT, ISD::NodeType ExtendKind) const;
929
930 virtual bool
931 CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF,
932 bool isVarArg,
933 const SmallVectorImpl &Outs,
934 LLVMContext &Context) const;
935
936 virtual const uint16_t *getScratchRegisters(CallingConv::ID CC) const;
912 SmallVectorImpl &InVals) const override;
913 SDValue LowerCall(CallLoweringInfo &CLI,
914 SmallVectorImpl &InVals) const override;
915
916 SDValue LowerReturn(SDValue Chain,
917 CallingConv::ID CallConv, bool isVarArg,
918 const SmallVectorImpl &Outs,
919 const SmallVectorImpl &OutVals,
920 SDLoc dl, SelectionDAG &DAG) const override;
921
922 bool isUsedByReturnOnly(SDNode *N, SDValue &Chain) const override;
923
924 bool mayBeEmittedAsTailCall(CallInst *CI) const override;
925
926 MVT getTypeForExtArgOrReturn(MVT VT,
927 ISD::NodeType ExtendKind) const override;
928
929 bool CanLowerReturn(CallingConv::ID CallConv, MachineFunction &MF,
930 bool isVarArg,
931 const SmallVectorImpl &Outs,
932 LLVMContext &Context) const override;
933
934 const uint16_t *getScratchRegisters(CallingConv::ID CC) const override;
937935
938936 /// Utility function to emit atomic-load-arith operations (and, or, xor,
939937 /// nand, max, min, umax, umin). It takes the corresponding instruction to
52675267 static char ID;
52685268 CGBR() : MachineFunctionPass(ID) {}
52695269
5270 virtual bool runOnMachineFunction(MachineFunction &MF) {
5270 bool runOnMachineFunction(MachineFunction &MF) override {
52715271 const X86TargetMachine *TM =
52725272 static_cast(&MF.getTarget());
52735273
53145314 return true;
53155315 }
53165316
5317 virtual const char *getPassName() const {
5317 const char *getPassName() const override {
53185318 return "X86 PIC Global Base Reg Initialization";
53195319 }
53205320
5321 virtual void getAnalysisUsage(AnalysisUsage &AU) const {
5321 void getAnalysisUsage(AnalysisUsage &AU) const override {
53225322 AU.setPreservesCFG();
53235323 MachineFunctionPass::getAnalysisUsage(AU);
53245324 }
53345334 static char ID;
53355335 LDTLSCleanup() : MachineFunctionPass(ID) {}
53365336
5337 virtual bool runOnMachineFunction(MachineFunction &MF) {
5337 bool runOnMachineFunction(MachineFunction &MF) override {
53385338 X86MachineFunctionInfo* MFI = MF.getInfo();
53395339 if (MFI->getNumLocalDynamicTLSAccesses() < 2) {
53405340 // No point folding accesses if there isn't at least two.
54275427 return Copy;
54285428 }
54295429
5430 virtual const char *getPassName() const {
5430 const char *getPassName() const override {
54315431 return "Local Dynamic TLS Access Clean-up";
54325432 }
54335433
5434 virtual void getAnalysisUsage(AnalysisUsage &AU) const {
5434 void getAnalysisUsage(AnalysisUsage &AU) const override {
54355435 AU.setPreservesCFG();
54365436 AU.addRequired();
54375437 MachineFunctionPass::getAnalysisUsage(AU);
168168 /// true, then it's expected the pre-extension value is available as a subreg
169169 /// of the result register. This also returns the sub-register index in
170170 /// SubIdx.
171 virtual bool isCoalescableExtInstr(const MachineInstr &MI,
172 unsigned &SrcReg, unsigned &DstReg,
173 unsigned &SubIdx) const;
174
175 unsigned isLoadFromStackSlot(const MachineInstr *MI, int &FrameIndex) const;
171 bool isCoalescableExtInstr(const MachineInstr &MI,
172 unsigned &SrcReg, unsigned &DstReg,
173 unsigned &SubIdx) const override;
174
175 unsigned isLoadFromStackSlot(const MachineInstr *MI,
176 int &FrameIndex) const override;
176177 /// isLoadFromStackSlotPostFE - Check for post-frame ptr elimination
177178 /// stack locations as well. This uses a heuristic so it isn't
178179 /// reliable for correctness.
179180 unsigned isLoadFromStackSlotPostFE(const MachineInstr *MI,
180 int &FrameIndex) const;
181
182 unsigned isStoreToStackSlot(const MachineInstr *MI, int &FrameIndex) const;
181 int &FrameIndex) const override;
182
183 unsigned isStoreToStackSlot(const MachineInstr *MI,
184 int &FrameIndex) const override;
183185 /// isStoreToStackSlotPostFE - Check for post-frame ptr elimination
184186 /// stack locations as well. This uses a heuristic so it isn't
185187 /// reliable for correctness.
186188 unsigned isStoreToStackSlotPostFE(const MachineInstr *MI,
187 int &FrameIndex) const;
189 int &FrameIndex) const override;
188190
189191 bool isReallyTriviallyReMaterializable(const MachineInstr *MI,
190 AliasAnalysis *AA) const;
192 AliasAnalysis *AA) const override;
191193 void reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
192194 unsigned DestReg, unsigned SubIdx,
193195 const MachineInstr *Orig,
194 const TargetRegisterInfo &TRI) const;
196 const TargetRegisterInfo &TRI) const override;
195197
196198 /// Given an operand within a MachineInstr, insert preceding code to put it
197199 /// into the right format for a particular kind of LEA instruction. This may
216218 /// This method returns a null pointer if the transformation cannot be
217219 /// performed, otherwise it returns the new instruction.
218220 ///
219 virtual MachineInstr *convertToThreeAddress(MachineFunction::iterator &MFI,
220 MachineBasicBlock::iterator &MBBI,
221 LiveVariables *LV) const;
221 MachineInstr *convertToThreeAddress(MachineFunction::iterator &MFI,
222 MachineBasicBlock::iterator &MBBI,
223 LiveVariables *LV) const override;
222224
223225 /// commuteInstruction - We have a few instructions that must be hacked on to
224226 /// commute them.
225227 ///
226 virtual MachineInstr *commuteInstruction(MachineInstr *MI, bool NewMI) const;
228 MachineInstr *commuteInstruction(MachineInstr *MI, bool NewMI) const override;
227229
228230 // Branch analysis.
229 virtual bool isUnpredicatedTerminator(const MachineInstr* MI) const;
230 virtual bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
231 MachineBasicBlock *&FBB,
232 SmallVectorImpl &Cond,
233 bool AllowModify) const;
234 virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const;
235 virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
236 MachineBasicBlock *FBB,
237 const SmallVectorImpl &Cond,
238 DebugLoc DL) const;
239 virtual bool canInsertSelect(const MachineBasicBlock&,
240 const SmallVectorImpl &Cond,
241 unsigned, unsigned, int&, int&, int&) const;
242 virtual void insertSelect(MachineBasicBlock &MBB,
243 MachineBasicBlock::iterator MI, DebugLoc DL,
244 unsigned DstReg,
245 const SmallVectorImpl &Cond,
246 unsigned TrueReg, unsigned FalseReg) const;
247 virtual void copyPhysReg(MachineBasicBlock &MBB,
248 MachineBasicBlock::iterator MI, DebugLoc DL,
249 unsigned DestReg, unsigned SrcReg,
250 bool KillSrc) const;
251 virtual void storeRegToStackSlot(MachineBasicBlock &MBB,
252 MachineBasicBlock::iterator MI,
253 unsigned SrcReg, bool isKill, int FrameIndex,
254 const TargetRegisterClass *RC,
255 const TargetRegisterInfo *TRI) const;
231 bool isUnpredicatedTerminator(const MachineInstr* MI) const override;
232 bool AnalyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
233 MachineBasicBlock *&FBB,
234 SmallVectorImpl &Cond,
235 bool AllowModify) const override;
236 unsigned RemoveBranch(MachineBasicBlock &MBB) const override;
237 unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
238 MachineBasicBlock *FBB,
239 const SmallVectorImpl &Cond,
240 DebugLoc DL) const override;
241 bool canInsertSelect(const MachineBasicBlock&,
242 const SmallVectorImpl &Cond,
243 unsigned, unsigned, int&, int&, int&) const override;
244 void insertSelect(MachineBasicBlock &MBB,
245 MachineBasicBlock::iterator MI, DebugLoc DL,
246 unsigned DstReg,
247 const SmallVectorImpl &Cond,
248 unsigned TrueReg, unsigned FalseReg) const override;
249 void copyPhysReg(MachineBasicBlock &MBB,
250 MachineBasicBlock::iterator MI, DebugLoc DL,
251 unsigned DestReg, unsigned SrcReg,
252 bool KillSrc) const override;
253 void storeRegToStackSlot(MachineBasicBlock &MBB,
254 MachineBasicBlock::iterator MI,
255 unsigned SrcReg, bool isKill, int FrameIndex,
256 const TargetRegisterClass *RC,
257 const TargetRegisterInfo *TRI) const override;
256258
257259 virtual void storeRegToAddr(MachineFunction &MF, unsigned SrcReg, bool isKill,
258260 SmallVectorImpl &Addr,
261263 MachineInstr::mmo_iterator MMOEnd,
262264 SmallVectorImpl &NewMIs) const;
263265
264 virtual void loadRegFromStackSlot(MachineBasicBlock &MBB,
265 MachineBasicBlock::iterator MI,
266 unsigned DestReg, int FrameIndex,
267 const TargetRegisterClass *RC,
268 const TargetRegisterInfo *TRI) const;
266 void loadRegFromStackSlot(MachineBasicBlock &MBB,
267 MachineBasicBlock::iterator MI,
268 unsigned DestReg, int FrameIndex,
269 const TargetRegisterClass *RC,
270 const TargetRegisterInfo *TRI) const override;
269271
270272 virtual void loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
271273 SmallVectorImpl &Addr,
274276 MachineInstr::mmo_iterator MMOEnd,
275277 SmallVectorImpl &NewMIs) const;
276278
277 virtual bool expandPostRAPseudo(MachineBasicBlock::iterator MI) const;
279 bool expandPostRAPseudo(MachineBasicBlock::iterator MI) const override;
278280
279281 /// foldMemoryOperand - If this target supports it, fold a load or store of
280282 /// the specified stack slot into the specified machine instruction for the
282284 /// folding and return true, otherwise it should return false. If it folds
283285 /// the instruction, it is likely that the MachineInstruction the iterator
284286 /// references has been changed.
285 virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF,
286 MachineInstr* MI,
287 const SmallVectorImpl &Ops,
288 int FrameIndex) const;
287 MachineInstr* foldMemoryOperandImpl(MachineFunction &MF,
288 MachineInstr* MI,
289 const SmallVectorImpl &Ops,
290 int FrameIndex) const override;
289291
290292 /// foldMemoryOperand - Same as the previous version except it allows folding
291293 /// of any load and store from / to any address, not just from a specific
292294 /// stack slot.
293 virtual MachineInstr* foldMemoryOperandImpl(MachineFunction &MF,
294 MachineInstr* MI,
295 const SmallVectorImpl &Ops,
296 MachineInstr* LoadMI) const;
295 MachineInstr* foldMemoryOperandImpl(MachineFunction &MF,
296 MachineInstr* MI,
297 const SmallVectorImpl &Ops,
298 MachineInstr* LoadMI) const override;
297299
298300 /// canFoldMemoryOperand - Returns true if the specified load / store is
299301 /// folding is possible.
300 virtual bool canFoldMemoryOperand(const MachineInstr*,
301 const SmallVectorImpl &) const;
302 bool canFoldMemoryOperand(const MachineInstr*,
303 const SmallVectorImpl &) const override;
302304
303305 /// unfoldMemoryOperand - Separate a single instruction which folded a load or
304306 /// a store or a load and a store into two or more instruction. If this is
305307 /// possible, returns true as well as the new instructions by reference.
306 virtual bool unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI,
307 unsigned Reg, bool UnfoldLoad, bool UnfoldStore,
308 SmallVectorImpl &NewMIs) const;
309
310 virtual bool unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N,
311 SmallVectorImpl &NewNodes) const;
308 bool unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI,
309 unsigned Reg, bool UnfoldLoad, bool UnfoldStore,
310 SmallVectorImpl &NewMIs) const override;
311
312 bool unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N,
313 SmallVectorImpl &NewNodes) const override;
312314
313315 /// getOpcodeAfterMemoryUnfold - Returns the opcode of the would be new
314316 /// instruction after load / store are unfolded from an instruction of the
316318 /// possible. If LoadRegIndex is non-null, it is filled in with the operand
317319 /// index of the operand which will hold the register holding the loaded
318320 /// value.
319 virtual unsigned getOpcodeAfterMemoryUnfold(unsigned Opc,
320 bool UnfoldLoad, bool UnfoldStore,
321 unsigned *LoadRegIndex = 0) const;
321 unsigned getOpcodeAfterMemoryUnfold(unsigned Opc,
322 bool UnfoldLoad, bool UnfoldStore,
323 unsigned *LoadRegIndex = 0) const override;
322324
323325 /// areLoadsFromSameBasePtr - This is used by the pre-regalloc scheduler
324326 /// to determine if two loads are loading from the same base address. It
325327 /// should only return true if the base pointers are the same and the
326328 /// only differences between the two addresses are the offset. It also returns
327329 /// the offsets by reference.
328 virtual bool areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2,
329 int64_t &Offset1, int64_t &Offset2) const;
330 bool areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2, int64_t &Offset1,
331 int64_t &Offset2) const override;
330332
331333 /// shouldScheduleLoadsNear - This is a used by the pre-regalloc scheduler to
332334 /// determine (in conjunction with areLoadsFromSameBasePtr) if two loads should
336338 /// from the common base address. It returns true if it decides it's desirable
337339 /// to schedule the two loads together. "NumLoads" is the number of loads that
338340 /// have already been scheduled after Load1.
339 virtual bool shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2,
340 int64_t Offset1, int64_t Offset2,
341 unsigned NumLoads) const;
342
343 virtual bool shouldScheduleAdjacent(MachineInstr* First,
344 MachineInstr *Second) const override;
345
346 virtual void getNoopForMachoTarget(MCInst &NopInst) const;
347
348 virtual
349 bool ReverseBranchCondition(SmallVectorImpl &Cond) const;
341 bool shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2,
342 int64_t Offset1, int64_t Offset2,
343 unsigned NumLoads) const override;
344
345 bool shouldScheduleAdjacent(MachineInstr* First,
346 MachineInstr *Second) const override;
347
348 void getNoopForMachoTarget(MCInst &NopInst) const override;
349
350 bool
351 ReverseBranchCondition(SmallVectorImpl &Cond) const override;
350352
351353 /// isSafeToMoveRegClassDefs - Return true if it's safe to move a machine
352354 /// instruction that defines the specified register class.
353 bool isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const;
355 bool isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const override;
354356
355357 static bool isX86_64ExtendedReg(const MachineOperand &MO) {
356358 if (!MO.isReg()) return false;
364366 unsigned getGlobalBaseReg(MachineFunction *MF) const;
365367
366368 std::pair
367 getExecutionDomain(const MachineInstr *MI) const;
368
369 void setExecutionDomain(MachineInstr *MI, unsigned Domain) const;
370
371 unsigned getPartialRegUpdateClearance(const MachineInstr *MI, unsigned OpNum,
372 const TargetRegisterInfo *TRI) const;
369 getExecutionDomain(const MachineInstr *MI) const override;
370
371 void setExecutionDomain(MachineInstr *MI, unsigned Domain) const override;
372
373 unsigned
374 getPartialRegUpdateClearance(const MachineInstr *MI, unsigned OpNum,
375 const TargetRegisterInfo *TRI) const override;
373376 unsigned getUndefRegClearance(const MachineInstr *MI, unsigned &OpNum,
374 const TargetRegisterInfo *TRI) const;
377 const TargetRegisterInfo *TRI) const override;
375378 void breakPartialRegDependency(MachineBasicBlock::iterator MI, unsigned OpNum,
376 const TargetRegisterInfo *TRI) const;
379 const TargetRegisterInfo *TRI) const override;
377380
378381 MachineInstr* foldMemoryOperandImpl(MachineFunction &MF,
379382 MachineInstr* MI,
381384 const SmallVectorImpl &MOs,
382385 unsigned Size, unsigned Alignment) const;
383386
384 bool isHighLatencyDef(int opc) const;
387 bool isHighLatencyDef(int opc) const override;
385388
386389 bool hasHighOperandLatency(const InstrItineraryData *ItinData,
387390 const MachineRegisterInfo *MRI,
388391 const MachineInstr *DefMI, unsigned DefIdx,
389 const MachineInstr *UseMI, unsigned UseIdx) const;
392 const MachineInstr *UseMI,
393 unsigned UseIdx) const override;
390394
391395 /// analyzeCompare - For a comparison instruction, return the source registers
392396 /// in SrcReg and SrcReg2 if having two register operands, and the value it
393397 /// compares against in CmpValue. Return true if the comparison instruction
394398 /// can be analyzed.
395 virtual bool analyzeCompare(const MachineInstr *MI, unsigned &SrcReg,
396 unsigned &SrcReg2,
397 int &CmpMask, int &CmpValue) const;
399 bool analyzeCompare(const MachineInstr *MI, unsigned &SrcReg,
400 unsigned &SrcReg2, int &CmpMask,
401 int &CmpValue) const override;
398402
399403 /// optimizeCompareInstr - Check if there exists an earlier instruction that
400404 /// operates on the same source operands and sets flags in the same way as
401405 /// Compare; remove Compare if possible.
402 virtual bool optimizeCompareInstr(MachineInstr *CmpInstr, unsigned SrcReg,
403 unsigned SrcReg2, int CmpMask, int CmpValue,
404 const MachineRegisterInfo *MRI) const;
406 bool optimizeCompareInstr(MachineInstr *CmpInstr, unsigned SrcReg,
407 unsigned SrcReg2, int CmpMask, int CmpValue,
408 const MachineRegisterInfo *MRI) const override;
405409
406410 /// optimizeLoadInstr - Try to remove the load by folding it to a register
407411 /// operand at the use. We fold the load instructions if and only if the
410414 /// defined by the load we are trying to fold. DefMI returns the machine
411415 /// instruction that defines FoldAsLoadDefReg, and the function returns
412416 /// the machine instruction generated due to folding.
413 virtual MachineInstr* optimizeLoadInstr(MachineInstr *MI,
414 const MachineRegisterInfo *MRI,
415 unsigned &FoldAsLoadDefReg,
416 MachineInstr *&DefMI) const;
417 MachineInstr* optimizeLoadInstr(MachineInstr *MI,
418 const MachineRegisterInfo *MRI,
419 unsigned &FoldAsLoadDefReg,
420 MachineInstr *&DefMI) const override;
417421
418422 private:
419423 MachineInstr * convertToThreeAddressWithLEA(unsigned MIOpc,
3434 /// overwriting OLD with a branch to NEW. This is used for self-modifying
3535 /// code.
3636 ///
37 virtual void replaceMachineCodeForFunction(void *Old, void *New);
37 void replaceMachineCodeForFunction(void *Old, void *New) override;
3838
3939 /// emitGlobalValueIndirectSym - Use the specified JITCodeEmitter object
4040 /// to emit an indirect symbol which contains the address of the specified
4141 /// ptr.
42 virtual void *emitGlobalValueIndirectSym(const GlobalValue* GV, void *ptr,
43 JITCodeEmitter &JCE);
42 void *emitGlobalValueIndirectSym(const GlobalValue* GV, void *ptr,
43 JITCodeEmitter &JCE) override;
4444
4545 // getStubLayout - Returns the size and alignment of the largest call stub
4646 // on X86.
47 virtual StubLayout getStubLayout();
47 StubLayout getStubLayout() override;
4848
4949 /// emitFunctionStub - Use the specified JITCodeEmitter object to emit a
5050 /// small native function that simply calls the function at the specified
5151 /// address.
52 virtual void *emitFunctionStub(const Function* F, void *Target,
53 JITCodeEmitter &JCE);
52 void *emitFunctionStub(const Function* F, void *Target,
53 JITCodeEmitter &JCE) override;
5454
5555 /// getPICJumpTableEntry - Returns the value of the jumptable entry for the
5656 /// specific basic block.
57 virtual uintptr_t getPICJumpTableEntry(uintptr_t BB, uintptr_t JTBase);
57 uintptr_t getPICJumpTableEntry(uintptr_t BB, uintptr_t JTBase) override;
5858
5959 /// getLazyResolverFunction - Expose the lazy resolver to the JIT.
60 virtual LazyResolverFn getLazyResolverFunction(JITCompilerFn);
60 LazyResolverFn getLazyResolverFunction(JITCompilerFn) override;
6161
6262 /// relocate - Before the JIT can run a block of code that has been emitted,
6363 /// it must rewrite the code to contain the actual addresses of any
6464 /// referenced global symbols.
65 virtual void relocate(void *Function, MachineRelocation *MR,
66 unsigned NumRelocs, unsigned char* GOTBase);
65 void relocate(void *Function, MachineRelocation *MR,
66 unsigned NumRelocs, unsigned char* GOTBase) override;
6767
6868 /// allocateThreadLocalMemory - Each target has its own way of
6969 /// handling thread local variables. This method returns a value only
7070 /// meaningful to the target.
71 virtual char* allocateThreadLocalMemory(size_t size);
71 char* allocateThreadLocalMemory(size_t size) override;
7272
7373 /// setPICBase / getPICBase - Getter / setter of PICBase, used to compute
7474 /// PIC jumptable entry.
5050 PadShortFunc() : MachineFunctionPass(ID)
5151 , Threshold(4), TM(0), TII(0) {}
5252
53 virtual bool runOnMachineFunction(MachineFunction &MF);
54
55 virtual const char *getPassName() const {
53 bool runOnMachineFunction(MachineFunction &MF) override;
54
55 const char *getPassName() const override {
5656 return "X86 Atom pad short functions";
5757 }
5858
6161
6262 /// getCompactUnwindRegNum - This function maps the register to the number for
6363 /// compact unwind encoding. Return -1 if the register isn't valid.
64 int getCompactUnwindRegNum(unsigned RegNum, bool isEH) const;
64 int getCompactUnwindRegNum(unsigned RegNum, bool isEH) const override;
6565
6666 /// Code Generation virtual methods...
6767 ///
68 virtual bool trackLivenessAfterRegAlloc(const MachineFunction &MF) const;
68 bool trackLivenessAfterRegAlloc(const MachineFunction &MF) const override;
6969
7070 /// getMatchingSuperRegClass - Return a subclass of the specified register
7171 /// class A so that each register in it has a sub-register of the
7272 /// specified sub-register index which is in the specified register class B.
73 virtual const TargetRegisterClass *
73 const TargetRegisterClass *
7474 getMatchingSuperRegClass(const TargetRegisterClass *A,
75 const TargetRegisterClass *B, unsigned Idx) const;
75 const TargetRegisterClass *B,
76 unsigned Idx) const override;
7677
77 virtual const TargetRegisterClass *
78 getSubClassWithSubReg(const TargetRegisterClass *RC, unsigned Idx) const;
78 const TargetRegisterClass *
79 getSubClassWithSubReg(const TargetRegisterClass *RC,
80 unsigned Idx) const override;
7981
8082 const TargetRegisterClass*
81 getLargestLegalSuperClass(const TargetRegisterClass *RC) const;
83 getLargestLegalSuperClass(const TargetRegisterClass *RC) const override;
8284
8385 /// getPointerRegClass - Returns a TargetRegisterClass used for pointer
8486 /// values.
8587 const TargetRegisterClass *
86 getPointerRegClass(const MachineFunction &MF, unsigned Kind = 0) const;
88 getPointerRegClass(const MachineFunction &MF,
89 unsigned Kind = 0) const override;
8790
8891 /// getCrossCopyRegClass - Returns a legal register class to copy a register
8992 /// in the specified class to or from. Returns NULL if it is possible to copy
9093 /// between a two registers of the specified class.
9194 const TargetRegisterClass *
92 getCrossCopyRegClass(const TargetRegisterClass *RC) const;
95 getCrossCopyRegClass(const TargetRegisterClass *RC) const override;
9396
9497 unsigned getRegPressureLimit(const TargetRegisterClass *RC,
95 MachineFunction &MF) const;
98 MachineFunction &MF) const override;
9699
97100 /// getCalleeSavedRegs - Return a null-terminated list of all of the
98101 /// callee-save registers on this target.
99 const uint16_t *getCalleeSavedRegs(const MachineFunction* MF = 0) const;
100 const uint32_t *getCallPreservedMask(CallingConv::ID) const;
102 const uint16_t *
103 getCalleeSavedRegs(const MachineFunction* MF = 0) const override;
104 const uint32_t *getCallPreservedMask(CallingConv::ID) const override;
101105 const uint32_t *getNoPreservedMask() const;
102106
103107 /// getReservedRegs - Returns a bitset indexed by physical register number
104108 /// indicating if a register is a special register that has particular uses and
105109 /// should be considered unavailable at all times, e.g. SP, RA. This is used by
106110 /// register scavenger to determine what registers are free.
107 BitVector getReservedRegs(const MachineFunction &MF) const;
111 BitVector getReservedRegs(const MachineFunction &MF) const override;
108112
109113 bool hasBasePointer(const MachineFunction &MF) const;
110114
111115 bool canRealignStack(const MachineFunction &MF) const;
112116
113 bool needsStackRealignment(const MachineFunction &MF) const;
117 bool needsStackRealignment(const MachineFunction &MF) const override;
114118
115119 bool hasReservedSpillSlot(const MachineFunction &MF, unsigned Reg,
116 int &FrameIdx) const;
120 int &FrameIdx) const override;
117121
118122 void eliminateFrameIndex(MachineBasicBlock::iterator MI,
119123 int SPAdj, unsigned FIOperandNum,
120 RegScavenger *RS = NULL) const;
124 RegScavenger *RS = NULL) const override;
121125
122126 // Debug information queries.
123 unsigned getFrameRegister(const MachineFunction &MF) const;
127 unsigned getFrameRegister(const MachineFunction &MF) const override;
124128 unsigned getStackRegister() const { return StackPtr; }
125129 unsigned getBaseRegister() const { return BasePtr; }
126130 // FIXME: Move to FrameInfok
3232 explicit X86SelectionDAGInfo(const X86TargetMachine &TM);
3333 ~X86SelectionDAGInfo();
3434
35 virtual
3635 SDValue EmitTargetCodeForMemset(SelectionDAG &DAG, SDLoc dl,
3736 SDValue Chain,
3837 SDValue Dst, SDValue Src,
3938 SDValue Size, unsigned Align,
4039 bool isVolatile,
41 MachinePointerInfo DstPtrInfo) const;
40 MachinePointerInfo DstPtrInfo) const override;
4241
43 virtual
4442 SDValue EmitTargetCodeForMemcpy(SelectionDAG &DAG, SDLoc dl,
4543 SDValue Chain,
4644 SDValue Dst, SDValue Src,
4745 SDValue Size, unsigned Align,
4846 bool isVolatile, bool AlwaysInline,
4947 MachinePointerInfo DstPtrInfo,
50 MachinePointerInfo SrcPtrInfo) const;
48 MachinePointerInfo SrcPtrInfo) const override;
5149 };
5250
5351 }
239239 void AutoDetectSubtargetFeatures();
240240
241241 /// \brief Reset the features for the X86 target.
242 virtual void resetSubtargetFeatures(const MachineFunction *MF);
242 void resetSubtargetFeatures(const MachineFunction *MF) override;
243243 private:
244244 void initializeEnvironment();
245245 void resetSubtargetFeatures(StringRef CPU, StringRef FS);
410410 /// enablePostRAScheduler - run for Atom optimization.
411411 bool enablePostRAScheduler(CodeGenOpt::Level OptLevel,
412412 TargetSubtargetInfo::AntiDepBreakMode& Mode,
413 RegClassVector& CriticalPathRCs) const;
413 RegClassVector& CriticalPathRCs) const override;
414414
415415 bool postRAScheduler() const { return PostRAScheduler; }
416416
157157 return *getX86TargetMachine().getSubtargetImpl();
158158 }
159159
160 virtual bool addInstSelector();
161 virtual bool addILPOpts();
162 virtual bool addPreRegAlloc();
163 virtual bool addPostRegAlloc();
164 virtual bool addPreEmitPass();
160 bool addInstSelector() override;
161 bool addILPOpts() override;
162 bool addPreRegAlloc() override;
163 bool addPostRegAlloc() override;
164 bool addPreEmitPass() override;
165165 };
166166 } // namespace
167167
4545 Reloc::Model RM, CodeModel::Model CM,
4646 CodeGenOpt::Level OL);
4747
48 virtual const DataLayout *getDataLayout() const { return &DL; }
49 virtual const X86InstrInfo *getInstrInfo() const {
48 const DataLayout *getDataLayout() const override { return &DL; }
49 const X86InstrInfo *getInstrInfo() const override {
5050 return &InstrInfo;
5151 }
52 virtual const TargetFrameLowering *getFrameLowering() const {
52 const TargetFrameLowering *getFrameLowering() const override {
5353 return &FrameLowering;
5454 }
55 virtual X86JITInfo *getJITInfo() {
55 X86JITInfo *getJITInfo() override {
5656 return &JITInfo;
5757 }
58 virtual const X86Subtarget *getSubtargetImpl() const{ return &Subtarget; }
59 virtual const X86TargetLowering *getTargetLowering() const {
58 const X86Subtarget *getSubtargetImpl() const override { return &Subtarget; }
59 const X86TargetLowering *getTargetLowering() const override {
6060 return &TLInfo;
6161 }
62 virtual const X86SelectionDAGInfo *getSelectionDAGInfo() const {
62 const X86SelectionDAGInfo *getSelectionDAGInfo() const override {
6363 return &TSInfo;
6464 }
65 virtual const X86RegisterInfo *getRegisterInfo() const {
65 const X86RegisterInfo *getRegisterInfo() const override {
6666 return &getInstrInfo()->getRegisterInfo();
6767 }
68 virtual const InstrItineraryData *getInstrItineraryData() const {
68 const InstrItineraryData *getInstrItineraryData() const override {
6969 return &InstrItins;
7070 }
7171
7272 /// \brief Register X86 analysis passes with a pass manager.
73 virtual void addAnalysisPasses(PassManagerBase &PM);
73 void addAnalysisPasses(PassManagerBase &PM) override;
7474
7575 // Set up the pass pipeline.
76 virtual TargetPassConfig *createPassConfig(PassManagerBase &PM);
76 TargetPassConfig *createPassConfig(PassManagerBase &PM) override;
7777
78 virtual bool addCodeEmitter(PassManagerBase &PM,
79 JITCodeEmitter &JCE);
78 bool addCodeEmitter(PassManagerBase &PM, JITCodeEmitter &JCE) override;
8079 };
8180
8281 } // End llvm namespace
3434 static char ID;
3535 VZeroUpperInserter() : MachineFunctionPass(ID) {}
3636
37 virtual bool runOnMachineFunction(MachineFunction &MF);
37 bool runOnMachineFunction(MachineFunction &MF) override;
3838
3939 bool processBasicBlock(MachineFunction &MF, MachineBasicBlock &MBB);
4040
41 virtual const char *getPassName() const { return "X86 vzeroupper inserter";}
41 const char *getPassName() const override {return "X86 vzeroupper inserter";}
4242
4343 private:
4444 const TargetInstrInfo *TII; // Machine instruction info.
614614 void MatcherTableEmitter::EmitPredicateFunctions(formatted_raw_ostream &OS) {
615615 // Emit pattern predicates.
616616 if (!PatternPredicates.empty()) {
617 OS << "virtual bool CheckPatternPredicate(unsigned PredNo) const {\n";
617 OS << "bool CheckPatternPredicate(unsigned PredNo) const override {\n";
618618 OS << " switch (PredNo) {\n";
619619 OS << " default: llvm_unreachable(\"Invalid predicate in table?\");\n";
620620 for (unsigned i = 0, e = PatternPredicates.size(); i != e; ++i)
632632 PFsByName[I->first->getName()] = I->second;
633633
634634 if (!NodePredicates.empty()) {
635 OS << "virtual bool CheckNodePredicate(SDNode *Node,\n";
636 OS << " unsigned PredNo) const {\n";
635 OS << "bool CheckNodePredicate(SDNode *Node,\n";
636 OS << " unsigned PredNo) const override {\n";
637637 OS << " switch (PredNo) {\n";
638638 OS << " default: llvm_unreachable(\"Invalid predicate in table?\");\n";
639639 for (unsigned i = 0, e = NodePredicates.size(); i != e; ++i) {
652652 // Emit CompletePattern matchers.
653653 // FIXME: This should be const.
654654 if (!ComplexPatterns.empty()) {
655 OS << "virtual bool CheckComplexPattern(SDNode *Root, SDNode *Parent,\n";
656 OS << " SDValue N, unsigned PatternNo,\n";
657 OS << " SmallVectorImpl > &Result) {\n";
655 OS << "bool CheckComplexPattern(SDNode *Root, SDNode *Parent,\n";
656 OS << " SDValue N, unsigned PatternNo,\n";
657 OS << " SmallVectorImpl > &Result) override {\n";
658658 OS << " unsigned NextRes = Result.size();\n";
659659 OS << " switch (PatternNo) {\n";
660660 OS << " default: llvm_unreachable(\"Invalid pattern # in table?\");\n";
693693 // Emit SDNodeXForm handlers.
694694 // FIXME: This should be const.
695695 if (!NodeXForms.empty()) {
696 OS << "virtual SDValue RunSDNodeXForm(SDValue V, unsigned XFormNo) {\n";
696 OS << "SDValue RunSDNodeXForm(SDValue V, unsigned XFormNo) override {\n";
697697 OS << " switch (XFormNo) {\n";
698698 OS << " default: llvm_unreachable(\"Invalid xform # in table?\");\n";
699699
964964 OS << "struct " << ClassName << " : public TargetRegisterInfo {\n"
965965 << " explicit " << ClassName
966966 << "(unsigned RA, unsigned D = 0, unsigned E = 0, unsigned PC = 0);\n"
967 << " virtual bool needsStackRealignment(const MachineFunction &) const\n"
967 << " bool needsStackRealignment(const MachineFunction &) const override\n"
968968 << " { return false; }\n";
969969 if (!RegBank.getSubRegIndices().empty()) {
970 OS << " virtual unsigned composeSubRegIndicesImpl"
971 << "(unsigned, unsigned) const;\n"
972 << " virtual const TargetRegisterClass *"
973 "getSubClassWithSubReg(const TargetRegisterClass*, unsigned) const;\n";
974 }
975 OS << " virtual const RegClassWeight &getRegClassWeight("
976 << "const TargetRegisterClass *RC) const;\n"
977 << " virtual unsigned getRegUnitWeight(unsigned RegUnit) const;\n"
978 << " virtual unsigned getNumRegPressureSets() const;\n"
979 << " virtual const char *getRegPressureSetName(unsigned Idx) const;\n"
980 << " virtual unsigned getRegPressureSetLimit(unsigned Idx) const;\n"
981 << " virtual const int *getRegClassPressureSets("
982 << "const TargetRegisterClass *RC) const;\n"
983 << " virtual const int *getRegUnitPressureSets(unsigned RegUnit) const;\n"
970 OS << " unsigned composeSubRegIndicesImpl"
971 << "(unsigned, unsigned) const override;\n"
972 << " const TargetRegisterClass *getSubClassWithSubReg"
973 << "(const TargetRegisterClass*, unsigned) const override;\n";
974 }
975 OS << " const RegClassWeight &getRegClassWeight("
976 << "const TargetRegisterClass *RC) const override;\n"
977 << " unsigned getRegUnitWeight(unsigned RegUnit) const override;\n"
978 << " unsigned getNumRegPressureSets() const override;\n"
979 << " const char *getRegPressureSetName(unsigned Idx) const override;\n"
980 << " unsigned getRegPressureSetLimit(unsigned Idx) const override;\n"
981 << " const int *getRegClassPressureSets("
982 << "const TargetRegisterClass *RC) const override;\n"
983 << " const int *getRegUnitPressureSets("
984 << "unsigned RegUnit) const override;\n"
984985 << "};\n\n";
985986
986987 ArrayRef RegisterClasses = RegBank.getRegClasses();
14971497 << "StringRef FS);\n"
14981498 << "public:\n"
14991499 << " unsigned resolveSchedClass(unsigned SchedClass, const MachineInstr *DefMI,"
1500 << " const TargetSchedModel *SchedModel) const;\n"
1500 << " const TargetSchedModel *SchedModel) const override;\n"
15011501 << " DFAPacketizer *createDFAPacketizer(const InstrItineraryData *IID)"
15021502 << " const;\n"
15031503 << "};\n";