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[ARM] GlobalISel: Select i8 and i16 copies Teach the instruction selector that it's ok to copy small values from physical registers. First part of https://reviews.llvm.org/D27704 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@290104 91177308-0d34-0410-b5e6-96231b3b80d8 Diana Picus 3 years ago
2 changed file(s) with 69 addition(s) and 5 deletion(s). Raw diff Collapse all Expand all
4141 (void)RegBank;
4242 assert(RegBank && "Can't get reg bank for virtual register");
4343
44 assert(MRI.getType(DstReg).getSizeInBits() ==
45 RBI.getSizeInBits(I.getOperand(1).getReg(), MRI, TRI) &&
44 const unsigned DstSize = MRI.getType(DstReg).getSizeInBits();
45 unsigned SrcReg = I.getOperand(1).getReg();
46 const unsigned SrcSize = RBI.getSizeInBits(SrcReg, MRI, TRI);
47 (void)SrcSize;
48 assert((DstSize == SrcSize ||
49 // Copies are a means to setup initial types, the number of
50 // bits may not exactly match.
51 (TargetRegisterInfo::isPhysicalRegister(SrcReg) &&
52 DstSize <= SrcSize)) &&
4653 "Copy with different width?!");
4754
4855 assert(RegBank->getID() == ARM::GPRRegBankID && "Unsupported reg bank");
0 # RUN: llc -O0 -mtriple arm-- -global-isel -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s
11 --- |
2 define void @test_adds32() { ret void }
2 define void @test_add_s8() { ret void }
3 define void @test_add_s16() { ret void }
4 define void @test_add_s32() { ret void }
5
36 define void @test_load_from_stack() { ret void }
47 ...
58 ---
6 name: test_adds32
7 # CHECK-LABEL: name: test_adds32
9 name: test_add_s8
10 # CHECK-LABEL: name: test_add_s8
11 legalized: true
12 regBankSelected: true
13 selected: false
14 # CHECK: selected: true
15 registers:
16 - { id: 0, class: gprb }
17 - { id: 1, class: gprb }
18 - { id: 2, class: gprb }
19 # CHECK-DAG: id: 0, class: gpr
20 # CHECK-DAG: id: 1, class: gpr
21 # CHECK-DAG: id: 2, class: gpr
22 body: |
23 bb.0:
24 liveins: %r0, %r1
25
26 %0(s8) = COPY %r0
27 ; CHECK: [[VREGX:%[0-9]+]] = COPY %r0
28
29 %r0 = COPY %0(s8)
30 ; CHECK: %r0 = COPY [[VREGX]]
31
32 BX_RET 14, _, implicit %r0
33 ; CHECK: BX_RET 14, _, implicit %r0
34 ...
35 ---
36 name: test_add_s16
37 # CHECK-LABEL: name: test_add_s16
38 legalized: true
39 regBankSelected: true
40 selected: false
41 # CHECK: selected: true
42 registers:
43 - { id: 0, class: gprb }
44 - { id: 1, class: gprb }
45 - { id: 2, class: gprb }
46 # CHECK-DAG: id: 0, class: gpr
47 # CHECK-DAG: id: 1, class: gpr
48 # CHECK-DAG: id: 2, class: gpr
49 body: |
50 bb.0:
51 liveins: %r0, %r1
52
53 %0(s16) = COPY %r0
54 ; CHECK: [[VREGX:%[0-9]+]] = COPY %r0
55
56 %r0 = COPY %0(s16)
57 ; CHECK: %r0 = COPY [[VREGX]]
58
59 BX_RET 14, _, implicit %r0
60 ; CHECK: BX_RET 14, _, implicit %r0
61 ...
62 ---
63 name: test_add_s32
64 # CHECK-LABEL: name: test_add_s32
865 legalized: true
966 regBankSelected: true
1067 selected: false