llvm.org GIT mirror llvm / f281371
[ARM] Improve loop unrolling for Cortex-M - Set the default runtime unroll count to 4 and use the newly added UnrollRemainder option. - Create loop cost and force unroll for a cost less than 12. - Disable unrolling on Thumb1 only targets. Differential Revision: https://reviews.llvm.org/D36134 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@310997 91177308-0d34-0410-b5e6-96231b3b80d8 Sam Parker 2 years ago
2 changed file(s) with 152 addition(s) and 103 deletion(s). Raw diff Collapse all Expand all
565565 void ARMTTIImpl::getUnrollingPreferences(Loop *L, ScalarEvolution &SE,
566566 TTI::UnrollingPreferences &UP) {
567567 // Only currently enable these preferences for M-Class cores.
568 if (!ST->isMClass() || L->getNumBlocks() != 1)
568 if (!ST->isMClass())
569569 return BasicTTIImplBase::getUnrollingPreferences(L, SE, UP);
570
571 // Only enable on Thumb-2 targets for simple loops.
572 if (!ST->isThumb2() || L->getNumBlocks() != 1)
573 return;
570574
571575 // Disable loop unrolling for Oz and Os.
572576 UP.OptSizeThreshold = 0;
573577 UP.PartialOptSizeThreshold = 0;
578 BasicBlock *BB = L->getLoopLatch();
579 if (BB->getParent()->optForSize())
580 return;
574581
575582 // Scan the loop: don't unroll loops with calls as this could prevent
576583 // inlining.
577 BasicBlock *BB = L->getLoopLatch();
584 unsigned Cost = 0;
578585 for (auto &I : *BB) {
579586 if (isa(I) || isa(I)) {
580587 ImmutableCallSite CS(&I);
584591 }
585592 return;
586593 }
587 }
588
589 // Enable partial and runtime unrolling, set the initial threshold based upon
590 // the number of registers available.
594 SmallVector Operands(I.value_op_begin(),
595 I.value_op_end());
596 Cost += getUserCost(&I, Operands);
597 }
598
591599 UP.Partial = true;
592600 UP.Runtime = true;
593 UP.Threshold = ST->isThumb1Only() ? 75 : 150;
594 UP.PartialThreshold = ST->isThumb1Only() ? 75 : 150;
595 }
601 UP.UnrollRemainder = true;
602 UP.DefaultUnrollRuntimeCount = 4;
603
604 // Force unrolling small loops can be very useful because of the branch
605 // taken cost of the backedge.
606 if (Cost < 12)
607 UP.Force = true;
608 }
None ; RUN: opt -mtriple=armv7 -mcpu=cortex-a57 -loop-unroll -S %s -o - | FileCheck %s --check-prefix=CHECK-UNROLL-V7
1 ; RUN: opt -mtriple=thumbv7 -mcpu=cortex-a57 -loop-unroll -S %s -o - | FileCheck %s --check-prefix=CHECK-UNROLL-V7
2 ; RUN: opt -mtriple=thumbv8m -mcpu=cortex-m23 -loop-unroll -S %s -o - | FileCheck %s --check-prefix=CHECK-UNROLL-SMALL
3 ; RUN: opt -mtriple=thumbv7m -mcpu=cortex-m4 -loop-unroll -S %s -o - | FileCheck %s --check-prefix=CHECK-UNROLL
4 ; RUN: opt -mtriple=thumbv8m.main -mcpu=cortex-m33 -loop-unroll -S %s -o - | FileCheck %s --check-prefix=CHECK-UNROLL
0 ; RUN: opt -mtriple=armv7 -mcpu=cortex-a57 -loop-unroll -S %s -o - | FileCheck %s --check-prefix=CHECK-UNROLL-A
1 ; RUN: opt -mtriple=thumbv7 -mcpu=cortex-a57 -loop-unroll -S %s -o - | FileCheck %s --check-prefix=CHECK-UNROLL-A
2 ; RUN: opt -mtriple=thumbv8m -mcpu=cortex-m23 -loop-unroll -S %s -o - | FileCheck %s --check-prefix=CHECK-UNROLL-T1
3 ; RUN: opt -mtriple=thumbv8m.main -mcpu=cortex-m33 -loop-unroll -S %s -o - | FileCheck %s --check-prefix=CHECK-UNROLL-T2
4 ; RUN: opt -mtriple=thumbv7em -mcpu=cortex-m7 -loop-unroll -S %s -o - | FileCheck %s --check-prefix=CHECK-UNROLL-T2
55
66 ; CHECK-LABEL: partial
77 define arm_aapcs_vfpcc void @partial(i32* nocapture %C, i32* nocapture readonly %A, i32* nocapture readonly %B) local_unnamed_addr #0 {
1111 ; CHECK-LABEL: for.body
1212 for.body:
1313
14 ; CHECK-UNROLL-V7: [[IV0:%[a-z.0-9]+]] = phi i32 [ 0, %entry ], [ [[IV2:%[a-z.0-9]+]], %for.body ]
15 ; CHECK-UNROLL-V7: [[IV1:%[a-z.0-9]+]] = add nuw nsw i32 [[IV0]], 1
16 ; CHECK-UNROLL-V7: [[IV2]] = add nuw nsw i32 [[IV1]], 1
17 ; CHECK-UNROLL-V7: [[CMP:%[a-z.0-9]+]] = icmp eq i32 [[IV2]], 1024
18 ; CHECK-UNROLL-V7: br i1 [[CMP]], label [[END:%[a-z.]+]], label %for.body
19
20 ; CHECK-UNROLL-SMALL: [[IV0:%[a-z.0-9]+]] = phi i32 [ 0, %entry ], [ [[IV8:%[a-z.0-9]+]], %for.body ]
21 ; CHECK-UNROLL-SMALL: [[IV1:%[a-z.0-9]+]] = add nuw nsw i32 [[IV0]], 1
22 ; CHECK-UNROLL-SMALL: [[IV2:%[a-z.0-9]+]] = add nuw nsw i32 [[IV1]], 1
23 ; CHECK-UNROLL-SMALL: [[IV3:%[a-z.0-9]+]] = add nuw nsw i32 [[IV2]], 1
24 ; CHECK-UNROLL-SMALL: [[IV4:%[a-z.0-9]+]] = add nuw nsw i32 [[IV3]], 1
25 ; CHECK-UNROLL-SMALL: [[IV5:%[a-z.0-9]+]] = add nuw nsw i32 [[IV4]], 1
26 ; CHECK-UNROLL-SMALL: [[IV6:%[a-z.0-9]+]] = add nuw nsw i32 [[IV5]], 1
27 ; CHECK-UNROLL-SMALL: [[IV7:%[a-z.0-9]+]] = add nuw nsw i32 [[IV6]], 1
28 ; CHECK-UNROLL-SMALL: [[IV8]] = add nuw nsw i32 [[IV7]], 1
29 ; CHECK-UNROLL-SMALL: [[CMP:%[a-z.0-9]+]] = icmp eq i32 [[IV8]], 1024
30 ; CHECK-UNROLL-SMALL: br i1 [[CMP]], label [[END:%[a-z.]+]], label %for.body
31
32 ; CHECK-UNROLL: [[IV0:%[a-z.0-9]+]] = phi i32 [ 0, %entry ], [ [[IV16:%[a-z.0-9]+]], %for.body ]
33 ; CHECK-UNROLL: [[IV1:%[a-z.0-9]+]] = add nuw nsw i32 [[IV0]], 1
34 ; CHECK-UNROLL: [[IV2:%[a-z.0-9]+]] = add nuw nsw i32 [[IV1]], 1
35 ; CHECK-UNROLL: [[IV3:%[a-z.0-9]+]] = add nuw nsw i32 [[IV2]], 1
36 ; CHECK-UNROLL: [[IV4:%[a-z.0-9]+]] = add nuw nsw i32 [[IV3]], 1
37 ; CHECK-UNROLL: [[IV5:%[a-z.0-9]+]] = add nuw nsw i32 [[IV4]], 1
38 ; CHECK-UNROLL: [[IV6:%[a-z.0-9]+]] = add nuw nsw i32 [[IV5]], 1
39 ; CHECK-UNROLL: [[IV7:%[a-z.0-9]+]] = add nuw nsw i32 [[IV6]], 1
40 ; CHECK-UNROLL: [[IV8:%[a-z.0-9]+]] = add nuw nsw i32 [[IV7]], 1
41 ; CHECK-UNROLL: [[IV9:%[a-z.0-9]+]] = add nuw nsw i32 [[IV8]], 1
42 ; CHECK-UNROLL: [[IV10:%[a-z.0-9]+]] = add nuw nsw i32 [[IV9]], 1
43 ; CHECK-UNROLL: [[IV11:%[a-z.0-9]+]] = add nuw nsw i32 [[IV10]], 1
44 ; CHECK-UNROLL: [[IV12:%[a-z.0-9]+]] = add nuw nsw i32 [[IV11]], 1
45 ; CHECK-UNROLL: [[IV13:%[a-z.0-9]+]] = add nuw nsw i32 [[IV12]], 1
46 ; CHECK-UNROLL: [[IV14:%[a-z.0-9]+]] = add nuw nsw i32 [[IV13]], 1
47 ; CHECK-UNROLL: [[IV15:%[a-z.0-9]+]] = add nuw nsw i32 [[IV14]], 1
48 ; CHECK-UNROLL: [[IV16]] = add nuw nsw i32 [[IV15]], 1
49 ; CHECK-UNROLL: [[CMP:%[a-z.0-9]+]] = icmp eq i32 [[IV16]], 1024
50 ; CHECK-UNROLL: br i1 [[CMP]], label [[END:%[a-z.]+]], label %for.body
14 ; CHECK-UNROLL-A: [[IV0:%[a-z.0-9]+]] = phi i32 [ 0, %entry ], [ [[IV2:%[a-z.0-9]+]], %for.body ]
15 ; CHECK-UNROLL-A: [[IV1:%[a-z.0-9]+]] = add nuw nsw i32 [[IV0]], 1
16 ; CHECK-UNROLL-A: [[IV2]] = add nuw nsw i32 [[IV1]], 1
17 ; CHECK-UNROLL-A: [[CMP:%[a-z.0-9]+]] = icmp eq i32 [[IV2]], 1024
18 ; CHECK-UNROLL-A: br i1 [[CMP]], label [[END:%[a-z.]+]], label %for.body
19
20 ; CHECK-UNROLL-T1: [[IV0:%[a-z.0-9]+]] = phi i32 [ 0, %entry ], [ [[IV1:%[a-z.0-9]+]], %for.body ]
21 ; CHECK-UNROLL-T1: [[IV1]] = add nuw nsw i32 [[IV0]], 1
22 ; CHECK-UNROLL-T1: [[CMP:%[a-z.0-9]+]] = icmp eq i32 [[IV1]], 1024
23 ; CHECK-UNROLL-T1: br i1 [[CMP]], label [[END:%[a-z.]+]], label %for.body
24
25 ; CHECK-UNROLL-T2: [[IV0:%[a-z.0-9]+]] = phi i32 [ 0, %entry ], [ [[IV16:%[a-z.0-9]+]], %for.body ]
26 ; CHECK-UNROLL-T2: [[IV1:%[a-z.0-9]+]] = add nuw nsw i32 [[IV0]], 1
27 ; CHECK-UNROLL-T2: [[IV2:%[a-z.0-9]+]] = add nuw nsw i32 [[IV1]], 1
28 ; CHECK-UNROLL-T2: [[IV3:%[a-z.0-9]+]] = add nuw nsw i32 [[IV2]], 1
29 ; CHECK-UNROLL-T2: [[IV4:%[a-z.0-9]+]] = add nuw nsw i32 [[IV3]], 1
30 ; CHECK-UNROLL-T2: [[IV5:%[a-z.0-9]+]] = add nuw nsw i32 [[IV4]], 1
31 ; CHECK-UNROLL-T2: [[IV6:%[a-z.0-9]+]] = add nuw nsw i32 [[IV5]], 1
32 ; CHECK-UNROLL-T2: [[IV7:%[a-z.0-9]+]] = add nuw nsw i32 [[IV6]], 1
33 ; CHECK-UNROLL-T2: [[IV8:%[a-z.0-9]+]] = add nuw nsw i32 [[IV7]], 1
34 ; CHECK-UNROLL-T2: [[IV9:%[a-z.0-9]+]] = add nuw nsw i32 [[IV8]], 1
35 ; CHECK-UNROLL-T2: [[IV10:%[a-z.0-9]+]] = add nuw nsw i32 [[IV9]], 1
36 ; CHECK-UNROLL-T2: [[IV11:%[a-z.0-9]+]] = add nuw nsw i32 [[IV10]], 1
37 ; CHECK-UNROLL-T2: [[IV12:%[a-z.0-9]+]] = add nuw nsw i32 [[IV11]], 1
38 ; CHECK-UNROLL-T2: [[IV13:%[a-z.0-9]+]] = add nuw nsw i32 [[IV12]], 1
39 ; CHECK-UNROLL-T2: [[IV14:%[a-z.0-9]+]] = add nuw nsw i32 [[IV13]], 1
40 ; CHECK-UNROLL-T2: [[IV15:%[a-z.0-9]+]] = add nuw nsw i32 [[IV14]], 1
41 ; CHECK-UNROLL-T2: [[IV16]] = add nuw nsw i32 [[IV15]], 1
42 ; CHECK-UNROLL-T2: [[CMP:%[a-z.0-9]+]] = icmp eq i32 [[IV16]], 1024
43 ; CHECK-UNROLL-T2: br i1 [[CMP]], label [[END:%[a-z.]+]], label %for.body
5144
5245 %i.08 = phi i32 [ 0, %entry ], [ %inc, %for.body ]
5346 %arrayidx = getelementptr inbounds i32, i32* %A, i32 %i.08
7366
7467 ; CHECK-LABEL: for.body
7568 for.body:
76 ; CHECK-UNROLL-V7: [[IV0:%[a-z.0-9]+]] = phi i32 [ 0, [[PRE:%[a-z.0-9]+]] ], [ [[IV8:%[a-z.0-9]+]], %for.body ]
77 ; CHECK-UNROLL-V7: [[IV1:%[a-z.0-9]+]] = add nuw nsw i32 [[IV0]], 1
78 ; CHECK-UNROLL-V7: [[IV2]] = add nuw i32 [[IV1]], 1
79
80 ; CHECK-UNROLL-SMALL: [[IV0:%[a-z.0-9]+]] = phi i32 [ 0, [[PRE:%[a-z.0-9]+]] ], [ [[IV8:%[a-z.0-9]+]], %for.body ]
81 ; CHECK-UNROLL-SMALL: [[IV1:%[a-z.0-9]+]] = add nuw nsw i32 [[IV0]], 1
82 ; CHECK-UNROLL-SMALL: [[IV2:%[a-z.0-9]+]] = add nuw nsw i32 [[IV1]], 1
83 ; CHECK-UNROLL-SMALL: [[IV3:%[a-z.0-9]+]] = add nuw nsw i32 [[IV2]], 1
84 ; CHECK-UNROLL-SMALL: [[IV4:%[a-z.0-9]+]] = add nuw nsw i32 [[IV3]], 1
85 ; CHECK-UNROLL-SMALL: [[IV5:%[a-z.0-9]+]] = add nuw nsw i32 [[IV4]], 1
86 ; CHECK-UNROLL-SMALL: [[IV6:%[a-z.0-9]+]] = add nuw nsw i32 [[IV5]], 1
87 ; CHECK-UNROLL-SMALL: [[IV7:%[a-z.0-9]+]] = add nuw nsw i32 [[IV6]], 1
88 ; CHECK-UNROLL-SMALL: [[IV8]] = add nuw i32 [[IV7]], 1
89
90 ; CHECK-UNROLL: [[IV0:%[a-z.0-9]+]] = phi i32 [ 0, [[PRE:%[a-z.0-9]+]] ], [ [[IV8:%[a-z.0-9]+]], %for.body ]
91 ; CHECK-UNROLL: [[IV1:%[a-z.0-9]+]] = add nuw nsw i32 [[IV0]], 1
92 ; CHECK-UNROLL: [[IV2:%[a-z.0-9]+]] = add nuw nsw i32 [[IV1]], 1
93 ; CHECK-UNROLL: [[IV3:%[a-z.0-9]+]] = add nuw nsw i32 [[IV2]], 1
94 ; CHECK-UNROLL: [[IV4:%[a-z.0-9]+]] = add nuw nsw i32 [[IV3]], 1
95 ; CHECK-UNROLL: [[IV5:%[a-z.0-9]+]] = add nuw nsw i32 [[IV4]], 1
96 ; CHECK-UNROLL: [[IV6:%[a-z.0-9]+]] = add nuw nsw i32 [[IV5]], 1
97 ; CHECK-UNROLL: [[IV7:%[a-z.0-9]+]] = add nuw nsw i32 [[IV6]], 1
98 ; CHECK-UNROLL: [[IV8]] = add nuw i32 [[IV7]], 1
69 ; CHECK-UNROLL-A: [[IV0:%[a-z.0-9]+]] = phi i32 [ 0, [[PRE:%[a-z.0-9]+]] ], [ [[IV2:%[a-z.0-9]+]], %for.body ]
70 ; CHECK-UNROLL-A: [[IV1:%[a-z.0-9]+]] = add nuw nsw i32 [[IV0]], 1
71 ; CHECK-UNROLL-A: [[IV2]] = add nuw i32 [[IV1]], 1
72 ; CHECK-UNROLL-A: br
73
74 ; CHECK-UNROLL-T1: %i.09 = phi i32 [ %inc, %for.body ], [ 0
75 ; CHECK-UNROLL-T1: %inc = add nuw i32 %i.09, 1
76 ; CHECK-UNROLL-T1: %exitcond = icmp eq i32 %inc, %N
77 ; CHECK-UNROLL-T1: br
78
79 ; CHECK-UNROLL-T2: [[IV0:%[a-z.0-9]+]] = phi i32 [ 0, [[PRE:%[a-z.0-9]+]] ], [ [[IV4:%[a-z.0-9]+]], %for.body ]
80 ; CHECK-UNROLL-T2: [[IV1:%[a-z.0-9]+]] = add nuw nsw i32 [[IV0]], 1
81 ; CHECK-UNROLL-T2: [[IV2:%[a-z.0-9]+]] = add nuw nsw i32 [[IV1]], 1
82 ; CHECK-UNROLL-T2: [[IV3:%[a-z.0-9]+]] = add nuw nsw i32 [[IV2]], 1
83 ; CHECK-UNROLL-T2: [[IV4]] = add nuw i32 [[IV3]], 1
84 ; CHECK-UNROLL-T2: br
85
86 ; CHECK-UNROLL-T2: for.body.epil:
87 ; CHECK-UNROLL-T2: for.body.epil.1:
88 ; CHECK-UNROLL-T2: for.body.epil.2:
9989
10090 %i.09 = phi i32 [ %inc, %for.body ], [ 0, %entry ]
10191 %arrayidx = getelementptr inbounds i32, i32* %A, i32 %i.09
134124
135125 ; CHECK-LABEL: for.body4
136126 for.body4:
137 ; CHECK-UNROLL-V7: [[IV0:%[a-z.0-9]+]] = phi i32 [ 0, [[PRE:%[a-z0-9.]+]] ], [ [[IV1:%[a-z.0-9]+]], %for.body4 ]
138 ; CHECK-UNROLL-V7: [[IV1:%[a-z.0-9]+]] = add nuw i32 [[IV0]], 1
139
140 ; CHECK-UNROLL-SMALL: [[IV0:%[a-z.0-9]+]] = phi i32 [ 0, [[PRE:%[a-z0-9.]+]] ], [ [[IV4:%[a-z.0-9]+]], %for.body4 ]
141 ; CHECK-UNROLL-SMALL: [[IV1:%[a-z.0-9]+]] = add nuw nsw i32 [[IV0]], 1
142 ; CHECK-UNROLL-SMALL: [[IV2:%[a-z.0-9]+]] = add nuw nsw i32 [[IV1]], 1
143 ; CHECK-UNROLL-SMALL: [[IV3:%[a-z.0-9]+]] = add nuw nsw i32 [[IV2]], 1
144 ; CHECK-UNROLL-SMALL: [[IV4]] = add nuw i32 [[IV3]], 1
145
146 ; CHECK-UNROLL: [[IV0:%[a-z.0-9]+]] = phi i32 [ 0, [[PRE:%[a-z0-9.]+]] ], [ [[IV8:%[a-z.0-9]+]], %for.body4 ]
147 ; CHECK-UNROLL: [[IV1:%[a-z.0-9]+]] = add nuw nsw i32 [[IV0]], 1
148 ; CHECK-UNROLL: [[IV2:%[a-z.0-9]+]] = add nuw nsw i32 [[IV1]], 1
149 ; CHECK-UNROLL: [[IV3:%[a-z.0-9]+]] = add nuw nsw i32 [[IV2]], 1
150 ; CHECK-UNROLL: [[IV4:%[a-z.0-9]+]] = add nuw nsw i32 [[IV3]], 1
151 ; CHECK-UNROLL: [[IV5:%[a-z.0-9]+]] = add nuw nsw i32 [[IV4]], 1
152 ; CHECK-UNROLL: [[IV6:%[a-z.0-9]+]] = add nuw nsw i32 [[IV5]], 1
153 ; CHECK-UNROLL: [[IV7:%[a-z.0-9]+]] = add nuw nsw i32 [[IV6]], 1
154 ; CHECK-UNROLL: [[IV8:%[a-z.0-9]+]] = add nuw i32 [[IV7]], 1
127 ; CHECK-UNROLL-T1: [[IV0:%[a-z.0-9]+]] = phi i32 [ 0, [[PRE:%[a-z0-9.]+]] ], [ [[IV1:%[a-z.0-9]+]], %for.body4 ]
128 ; CHECK-UNROLL-T1: [[IV1]] = add nuw i32 [[IV0]], 1
129 ; CHECK-UNROLL-T1: br
130
131 ; CHECK-UNROLL-T2: for.body4.epil:
132 ; CHECK-UNROLL-T2: [[IV0:%[a-z.0-9]+]] = phi i32 [ 0, [[PRE:%[a-z0-9.]+]] ], [ [[IV4:%[a-z.0-9]+]], %for.body4 ]
133 ; CHECK-UNROLL-T2: [[IV1:%[a-z.0-9]+]] = add nuw nsw i32 [[IV0]], 1
134 ; CHECK-UNROLL-T2: [[IV2:%[a-z.0-9]+]] = add nuw nsw i32 [[IV1]], 1
135 ; CHECK-UNROLL-T2: [[IV3:%[a-z.0-9]+]] = add nuw nsw i32 [[IV2]], 1
136 ; CHECK-UNROLL-T2: [[IV4]] = add nuw i32 [[IV3]], 1
137 ; CHECK-UNROLL-T2: br
138 ; CHECK-UNROLL-T2: for.body4.epil.1:
139 ; CHECK-UNROLL-T2: for.body4.epil.2:
155140
156141 %w.024 = phi i32 [ 0, %for.body4.lr.ph ], [ %inc, %for.body4 ]
157142 %add = add i32 %w.024, %mul
181166
182167 ; CHECK-LABEL: for.body
183168 for.body:
184 ; CHECK-UNROLL-V7: [[IV0:%[a-z.0-9]+]] = phi i32 [ 0, %entry ], [ [[IV1:%[a-z.0-9]+]], %for.body ]
185 ; CHECK-UNROLL-V7: [[IV1]] = add nuw nsw i32 [[IV0]], 1
186 ; CHECK-UNROLL-V7: icmp eq i32 [[IV1]], 1024
187
188 ; CHECK-UNROLL-SMALL: [[IV0:%[a-z.0-9]+]] = phi i32 [ 0, %entry ], [ [[IV1:%[a-z.0-9]+]], %for.body ]
189 ; CHECK-UNROLL-SMALL: [[IV1]] = add nuw nsw i32 [[IV0]], 1
190 ; CHECK-UNROLL-SMALL: icmp eq i32 [[IV1]], 1024
191
192 ; CHECK-UNROLL: [[IV0:%[a-z.0-9]+]] = phi i32 [ 0, %entry ], [ [[IV1:%[a-z.0-9]+]], %for.body ]
193 ; CHECK-UNROLL: [[IV1]] = add nuw nsw i32 [[IV0]], 1
194 ; CHECK-UNROLL: icmp eq i32 [[IV1]], 1024
169 ; CHECK-UNROLL-A: [[IV0:%[a-z.0-9]+]] = phi i32 [ 0, %entry ], [ [[IV1:%[a-z.0-9]+]], %for.body ]
170 ; CHECK-UNROLL-A: [[IV1]] = add nuw nsw i32 [[IV0]], 1
171 ; CHECK-UNROLL-A: icmp eq i32 [[IV1]], 1024
172 ; CHECK-UNROLL-A: br
173
174 ; CHECK-UNROLL-T1: [[IV0:%[a-z.0-9]+]] = phi i32 [ 0, %entry ], [ [[IV1:%[a-z.0-9]+]], %for.body ]
175 ; CHECK-UNROLL-T1: [[IV1]] = add nuw nsw i32 [[IV0]], 1
176 ; CHECK-UNROLL-T1: icmp eq i32 [[IV1]], 1024
177 ; CHECK-UNROLL-T1: br
178
179 ; CHECK-UNROLL-T2: [[IV0:%[a-z.0-9]+]] = phi i32 [ 0, %entry ], [ [[IV1:%[a-z.0-9]+]], %for.body ]
180 ; CHECK-UNROLL-T2: [[IV1]] = add nuw nsw i32 [[IV0]], 1
181 ; CHECK-UNROLL-T2: icmp eq i32 [[IV1]], 1024
182 ; CHECK-UNROLL-T2: br
195183
196184 %i.08 = phi i32 [ 0, %entry ], [ %inc, %for.body ]
197185 %arrayidx = getelementptr inbounds i32, i32* %A, i32 %i.08
206194 br i1 %exitcond, label %for.cond.cleanup, label %for.body
207195 }
208196
197 ; CHECK-LABEL: iterate_inc
198 ; CHECK-UNROLL-A: %n.addr.04 = phi %struct.Node* [ %1, %while.body ], [ %n, %while.body.preheader ]
199 ; CHECK-UNROLL-A: %tobool = icmp eq %struct.Node* %1, null
200 ; CHECK-UNROLL-A: br i1 %tobool
201 ; CHECK-UNROLL-A-NOT: load
202
203 ; CHECK-UNROLL-T1: %n.addr.04 = phi %struct.Node* [ %1, %while.body ], [ %n, %while.body.preheader ]
204 ; CHECK-UNROLL-T1: %tobool = icmp eq %struct.Node* %1, null
205 ; CHECK-UNROLL-T1: br i1 %tobool
206 ; CHECK-UNROLL-T1-NOT: load
207
208 ; CHECK-UNROLL-T2: [[CMP0:%[a-z.0-9]+]] = icmp eq %struct.Node* [[VAR0:%[a-z.0-9]+]], null
209 ; CHECK-UNROLL-T2: br i1 [[CMP0]], label [[END:%[a-z.0-9]+]]
210 ; CHECK-UNROLL-T2: [[CMP1:%[a-z.0-9]+]] = icmp eq %struct.Node* [[VAR1:%[a-z.0-9]+]], null
211 ; CHECK-UNROLL-T2: br i1 [[CMP1]], label [[END]]
212 ; CHECK-UNROLL-T2: [[CMP2:%[a-z.0-9]+]] = icmp eq %struct.Node* [[VAR2:%[a-z.0-9]+]], null
213 ; CHECK-UNROLL-T2: br i1 [[CMP2]], label [[END]]
214 ; CHECK-UNROLL-T2: [[CMP3:%[a-z.0-9]+]] = icmp eq %struct.Node* [[VAR3:%[a-z.0-9]+]], null
215 ; CHECK-UNROLL-T2: br i1 [[CMP3]], label [[END]]
216 ; CHECK-UNROLL-T2: [[CMP4:%[a-z.0-9]+]] = icmp eq %struct.Node* [[VAR4:%[a-z.0-9]+]], null
217 ; CHECK-UNROLL-T2: br i1 [[CMP4]], label [[END]]
218 ; CHECK-UNROLL-T2-NOT: load
219
220 %struct.Node = type { %struct.Node*, i32 }
221
222 define arm_aapcscc void @iterate_inc(%struct.Node* %n) local_unnamed_addr #0 {
223 entry:
224 %tobool3 = icmp eq %struct.Node* %n, null
225 br i1 %tobool3, label %while.end, label %while.body.preheader
226
227 while.body.preheader:
228 br label %while.body
229
230 while.body:
231 %n.addr.04 = phi %struct.Node* [ %1, %while.body ], [ %n, %while.body.preheader ]
232 %val = getelementptr inbounds %struct.Node, %struct.Node* %n.addr.04, i32 0, i32 1
233 %0 = load i32, i32* %val, align 4
234 %add = add nsw i32 %0, 1
235 store i32 %add, i32* %val, align 4
236 %next = getelementptr inbounds %struct.Node, %struct.Node* %n.addr.04, i32 0, i32 0
237 %1 = load %struct.Node*, %struct.Node** %next, align 4
238 %tobool = icmp eq %struct.Node* %1, null
239 br i1 %tobool, label %while.end, label %while.body
240
241 while.end:
242 ret void
243 }
244
209245 declare arm_aapcs_vfpcc i32 @some_func(i32, i32) local_unnamed_addr #2