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[Hexagon] Avoid predicate copies to integer registers from store-locked git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@332260 91177308-0d34-0410-b5e6-96231b3b80d8 Krzysztof Parzyszek 1 year, 5 months ago
4 changed file(s) with 22 addition(s) and 7 deletion(s). Raw diff Collapse all Expand all
29092909 [SDNPHasChain]>;
29102910
29112911 def: Pat<(HexagonREADCYCLE), (A4_tfrcpp UPCYCLE)>;
2912
2913 // The declared return value of the store-locked intrinsics is i32, but
2914 // the instructions actually define i1. To avoid register copies from
2915 // IntRegs to PredRegs and back, fold the entire pattern checking the
2916 // result against true/false.
2917 let AddedComplexity = 100 in {
2918 def: Pat<(i1 (setne (int_hexagon_S2_storew_locked I32:$Rs, I32:$Rt), 0)),
2919 (S2_storew_locked I32:$Rs, I32:$Rt)>;
2920 def: Pat<(i1 (seteq (int_hexagon_S2_storew_locked I32:$Rs, I32:$Rt), 0)),
2921 (C2_not (S2_storew_locked I32:$Rs, I32:$Rt))>;
2922 def: Pat<(i1 (setne (int_hexagon_S4_stored_locked I32:$Rs, I64:$Rt), 0)),
2923 (S4_stored_locked I32:$Rs, I64:$Rt)>;
2924 def: Pat<(i1 (seteq (int_hexagon_S4_stored_locked I32:$Rs, I64:$Rt), 0)),
2925 (C2_not (S4_stored_locked I32:$Rs, I64:$Rt))>;
2926 }
3838 ; CHECK: [[RESULT_REG:r[0-9]+]] = [[BINARY_OP]]([[LOCKED_READ_REG]],[[FIRST_VALUE]])
3939 ; CHECK: memw_locked([[SECOND_ADDR]],[[LOCK_PRED_REG:p[0-9]+]]) = [[RESULT_REG]]
4040
41 ; CHECK: cmp.eq{{.*}}jump{{.*}}[[FAIL_LABEL]]
41 ; CHECK: if (![[LOCK_PRED_REG]]) jump{{.*}}[[FAIL_LABEL]]
4242 ; CHECK-DAG: memw(gp+#i32Result) = [[LOCKED_READ_REG]]
4343 ; CHECK-DAG: jumpr r31
4444
5959 ; CHECK: [[RESULT_REG:r[0-9]+:[0-9]+]] = [[BINARY_OP]]([[LOCKED_READ_REG]],[[FIRST_VALUE]])
6060 ; CHECK: memd_locked([[SECOND_ADDR]],[[LOCK_PRED_REG:p[0-9]+]]) = [[RESULT_REG]]
6161
62 ; CHECK: cmp.eq{{.*}}jump{{.*}}[[FAIL_LABEL]]
62 ; CHECK: if (![[LOCK_PRED_REG]]) jump{{.*}}[[FAIL_LABEL]]
6363 ; CHECK-DAG: memd(gp+#i64Result) = [[LOCKED_READ_REG]]
6464 ; CHECK-DAG: jumpr r31
6565
8080 ; CHECK: [[RESULT_REG:r[0-9]+]] = [[BINARY_OP]]([[LOCKED_READ_REG]],[[FIRST_VALUE]])
8181 ; CHECK: memw_locked([[SECOND_ADDR]],[[LOCK_PRED_REG:p[0-9]+]]) = [[RESULT_REG]]
8282
83 ; CHECK: cmp.eq{{.*}}jump{{.*}}[[FAIL_LABEL]]
83 ; CHECK: if (![[LOCK_PRED_REG]]) jump{{.*}}[[FAIL_LABEL]]
8484 ; CHECK-DAG: memw(gp+#ptrResult) = [[LOCKED_READ_REG]]
8585 ; CHECK-DAG: jumpr r31
8686
3131 ; CHECK: [[RESULT_REG:r[0-9]+]] = [[BINARY_OP]]([[LOCKED_READ_REG]],[[FIRST_VALUE]])
3232 ; CHECK: memw_locked([[SECOND_ADDR]],[[LOCK_PRED_REG:p[0-9]+]]) = [[RESULT_REG]]
3333
34 ; CHECK: cmp.eq{{.*}}jump{{.*}}[[FAIL_LABEL]]
34 ; CHECK: if (![[LOCK_PRED_REG]]) jump{{.*}}[[FAIL_LABEL]]
3535 ; CHECK-DAG: memw(gp+#g2) = [[LOCKED_READ_REG]]
3636 ; CHECK-DAG: jumpr r31
3737 define void @f0() {
5252 ; CHECK: [[RESULT_REG:r[:0-9]+]] = [[BINARY_OP]]([[LOCKED_READ_REG]],[[FIRST_VALUE]])
5353 ; CHECK: memd_locked([[SECOND_ADDR]],[[LOCK_PRED_REG:p[0-9]+]]) = [[RESULT_REG]]
5454
55 ; CHECK: cmp.eq{{.*}}jump{{.*}}[[FAIL_LABEL]]
55 ; CHECK: if (![[LOCK_PRED_REG]]) jump{{.*}}[[FAIL_LABEL]]
5656 ; CHECK-DAG: memd(gp+#g5) = [[LOCKED_READ_REG]]
5757 ; CHECK-DAG: jumpr r31
5858 define void @f1() {
2121 ; CHECK: [[RESULT_REG:r[0-9]+]] = sub(#-1,[[AND_RESULT_REG]])
2222 ; CHECK: memw_locked([[SECOND_ADDR]],[[LOCK_PRED_REG:p[0-9]+]]) = [[RESULT_REG]]
2323
24 ; CHECK: cmp.eq{{.*}}jump{{.*}}[[FAIL_LABEL]]
24 ; CHECK: if (![[LOCK_PRED_REG]]) jump{{.*}}[[FAIL_LABEL]]
2525 ; CHECK-DAG: memw(gp+#g2) = [[LOCKED_READ_REG]]
2626 ; CHECK-DAG: jumpr r31
2727 define void @f0() {
4343 ; CHECK: [[RESULT_REG:r[:0-9]+]] = not([[AND_RESULT_REG]])
4444 ; CHECK: memd_locked([[SECOND_ADDR]],[[LOCK_PRED_REG:p[0-9]+]]) = [[RESULT_REG]]
4545
46 ; CHECK: cmp.eq{{.*}}jump{{.*}}[[FAIL_LABEL]]
46 ; CHECK: if (![[LOCK_PRED_REG]]) jump{{.*}}[[FAIL_LABEL]]
4747 ; CHECK-DAG: memd(gp+#g5) = [[LOCKED_READ_REG]]
4848 ; CHECK-DAG: jumpr r31
4949 define void @f1() {