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[release_50] Merging r313916 [AArch64] Fix bug in store of vector 0 DAGCombine. Summary: Avoid using XZR/WZR directly as operands to split stores of zero vectors. Doing so can lead to the XZR/WZR being used by an instruction that doesn't allow it (e.g. add). Fixes bug 34674. Reviewers: t.p.northover, efriedma, MatzeB Subscribers: aemerson, rengolin, javed.absar, mcrosier, eraman, llvm-commits, kristof.beyls Differential Revision: https://reviews.llvm.org/D38146 PR34695. git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_50@314796 91177308-0d34-0410-b5e6-96231b3b80d8 Renato Golin 3 years ago
4 changed file(s) with 39 addition(s) and 11 deletion(s). Raw diff Collapse all Expand all
93469346 return SDValue();
93479347 }
93489348
9349 // Use WZR/XZR here to prevent DAGCombiner::MergeConsecutiveStores from
9350 // undoing this transformation.
9351 SDValue SplatVal = VT.getVectorElementType().getSizeInBits() == 32
9352 ? DAG.getRegister(AArch64::WZR, MVT::i32)
9353 : DAG.getRegister(AArch64::XZR, MVT::i64);
9349 // Use a CopyFromReg WZR/XZR here to prevent
9350 // DAGCombiner::MergeConsecutiveStores from undoing this transformation.
9351 SDLoc DL(&St);
9352 unsigned ZeroReg;
9353 EVT ZeroVT;
9354 if (VT.getVectorElementType().getSizeInBits() == 32) {
9355 ZeroReg = AArch64::WZR;
9356 ZeroVT = MVT::i32;
9357 } else {
9358 ZeroReg = AArch64::XZR;
9359 ZeroVT = MVT::i64;
9360 }
9361 SDValue SplatVal =
9362 DAG.getCopyFromReg(DAG.getEntryNode(), DL, ZeroReg, ZeroVT);
93549363 return splitStoreSplat(DAG, St, SplatVal, NumVecElts);
93559364 }
93569365
1111 define void @t2() nounwind ssp {
1212 entry:
1313 ; CHECK-LABEL: t2:
14 ; CHECK: stp xzr, xzr, [sp, #16]
1415 ; CHECK: strh wzr, [sp, #32]
15 ; CHECK: stp xzr, xzr, [sp, #8]
16 ; CHECK: str xzr, [sp, #24]
16 ; CHECK: str xzr, [sp, #8]
1717 %buf = alloca [26 x i8], align 1
1818 %0 = getelementptr inbounds [26 x i8], [26 x i8]* %buf, i32 0, i32 0
1919 call void @llvm.memset.p0i8.i32(i8* %0, i8 0, i32 26, i32 1, i1 false)
2020 call fastcc void @func_stack8([8 x i32] undef, i32 42)
2121 ; CHECK: bl func_stack8
2222 ; CHECK-NOT: sub sp, sp,
23 ; CHECK-NOT: [sp, #{{[-0-9]+}}]!
24 ; CHECK-NOT: [sp], #{{[-0-9]+}}
2325
2426 ; CHECK-TAIL: bl func_stack8
25 ; CHECK-TAIL: sub sp, sp, #16
27 ; CHECK-TAIL: stp xzr, xzr, [sp, #-16]!
2628
2729
2830 call fastcc void @func_stack32([8 x i32] undef, i128 0, i128 9)
7173 call fastcc void @func_stack8([8 x i32] undef, i32 42)
7274 ; CHECK: bl func_stack8
7375 ; CHECK-NOT: sub sp, sp,
76 ; CHECK-NOT: [sp, #{{[-0-9]+}}]!
77 ; CHECK-NOT: [sp], #{{[-0-9]+}}
7478
7579
7680 ; CHECK-TAIL: bl func_stack8
77 ; CHECK-TAIL: sub sp, sp, #16
81 ; CHECK-TAIL: stp xzr, xzr, [sp, #-16]!
7882
7983
8084 call fastcc void @func_stack32([8 x i32] undef, i128 0, i128 9)
115119 call fastcc void @func_stack8([8 x i32] undef, i32 42)
116120 ; CHECK: bl func_stack8
117121 ; CHECK-NOT: sub sp, sp,
122 ; CHECK-NOT: [sp, #{{[-0-9]+}}]!
123 ; CHECK-NOT: [sp], #{{[-0-9]+}}
118124
119125 ; CHECK-TAIL: bl func_stack8
120 ; CHECK-TAIL: sub sp, sp, #16
126 ; CHECK-TAIL: stp xzr, xzr, [sp, #-16]!
121127
122128
123129 call fastcc void @func_stack32([8 x i32] undef, i128 0, i128 9)
16661666 ret void
16671667 }
16681668
1669
1669 ; Check for bug 34674 where invalid add of xzr was being generated.
1670 ; CHECK-LABEL: bug34674:
1671 ; CHECK: // %entry
1672 ; CHECK-NEXT: mov [[ZREG:x[0-9]+]], xzr
1673 ; CHECK-DAG: stp [[ZREG]], [[ZREG]], [x0]
1674 ; CHECK-DAG: add x{{[0-9]+}}, [[ZREG]], #1
1675 define i64 @bug34674(<2 x i64>* %p) {
1676 entry:
1677 store <2 x i64> zeroinitializer, <2 x i64>* %p
1678 %p2 = bitcast <2 x i64>* %p to i64*
1679 %ld = load i64, i64* %p2
1680 %add = add i64 %ld, 1
1681 ret i64 %add
1682 }