llvm.org GIT mirror llvm / f1d93ca
Reenable DAG combining for vector shuffles. It looks like it was temporarily disabled and then never turned back on again. Adjust some tests, one because this change avoids an unnecessary instruction, and the other to make it continue testing what it was intended to test. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@107941 91177308-0d34-0410-b5e6-96231b3b80d8 Bob Wilson 9 years ago
3 changed file(s) with 12 addition(s) and 12 deletion(s). Raw diff Collapse all Expand all
63086308 }
63096309
63106310 SDValue DAGCombiner::visitVECTOR_SHUFFLE(SDNode *N) {
6311 return SDValue();
6312
63136311 EVT VT = N->getValueType(0);
63146312 unsigned NumElts = VT.getVectorNumElements();
63156313
33
44 ; This tests the fast register allocator's handling of partial redefines:
55 ;
6 ; %reg1026 = VMOVv16i8 0, pred:14, pred:%reg0
7 ; %reg1028:dsub_1 = EXTRACT_SUBREG %reg1026, 1
6 ; %reg1028:dsub_0, %reg1028:dsub_1 = VLD1q64 %reg1025...
7 ; %reg1030:dsub_1 = COPY %reg1028:dsub_0
88 ;
9 ; %reg1026 gets allocated %Q0, and if %reg1028 is reloaded for the partial redef,
10 ; it cannot also get %Q0.
9 ; %reg1028 gets allocated %Q0, and if %reg1030 is reloaded for the partial
10 ; redef, it cannot also get %Q0.
1111
12 ; CHECK: vmov.i8 q0, #0x0
13 ; CHECK-NOT: vld1.64 {d0,d1}
12 ; CHECK: vld1.64 {d0, d1}, [r0]
13 ; CHECK-NOT: vld1.64 {d0, d1}
1414 ; CHECK: vmov.f64 d3, d0
1515
16 define i32 @main(i32 %argc, i8** %argv) nounwind {
16 define i32 @test(i8* %arg) nounwind {
1717 entry:
18 %0 = shufflevector <2 x i64> undef, <2 x i64> zeroinitializer, <2 x i32> ; <<2 x i64>> [#uses=1]
19 store <2 x i64> %0, <2 x i64>* undef, align 16
18 %0 = call <2 x i64> @llvm.arm.neon.vld1.v2i64(i8* %arg)
19 %1 = shufflevector <2 x i64> undef, <2 x i64> %0, <2 x i32>
20 store <2 x i64> %1, <2 x i64>* undef, align 16
2021 ret i32 undef
2122 }
23
24 declare <2 x i64> @llvm.arm.neon.vld1.v2i64(i8*) nounwind readonly
269269 entry:
270270 ; CHECK: t10:
271271 ; CHECK: vmov.i32 q1, #0x3F000000
272 ; CHECK: vdup.32 q0, d0[0]
273272 ; CHECK: vmov d0, d1
274273 ; CHECK: vmla.f32 q0, q0, d0[0]
275274 %0 = shufflevector <4 x float> zeroinitializer, <4 x float> undef, <4 x i32> zeroinitializer ; <<4 x float>> [#uses=1]