llvm.org GIT mirror llvm / f1b37fe
Merging r329761: ------------------------------------------------------------------------ r329761 | gberry | 2018-04-10 14:43:03 -0700 (Tue, 10 Apr 2018) | 13 lines [AArch64][Falkor] Fix bug in Falkor HWPF collision avoidance pass. Summary: When inserting MOVs to avoid Falkor HWPF collisions, the non-base register operand of load instructions (e.g. a register offset) was not being considered live, so it could potentially have been used as a scratch register, clobbering the actual offset value. Reviewers: mcrosier Subscribers: rengolin, javed.absar, kristof.beyls, llvm-commits Differential Revision: https://reviews.llvm.org/D45502 ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_60@330209 91177308-0d34-0410-b5e6-96231b3b80d8 Tom Stellard 2 years ago
2 changed file(s) with 43 addition(s) and 0 deletion(s). Raw diff Collapse all Expand all
4545 #include "llvm/Pass.h"
4646 #include "llvm/Support/Casting.h"
4747 #include "llvm/Support/Debug.h"
48 #include "llvm/Support/DebugCounter.h"
4849 #include "llvm/Support/raw_ostream.h"
4950 #include
5051 #include
5960 "Number of HW prefetch tag collisions avoided");
6061 STATISTIC(NumCollisionsNotAvoided,
6162 "Number of HW prefetch tag collisions not avoided due to lack of regsiters");
63 DEBUG_COUNTER(FixCounter, "falkor-hwpf",
64 "Controls which tag collisions are avoided");
6265
6366 namespace {
6467
728731 bool Fixed = false;
729732 DEBUG(dbgs() << "Attempting to fix tag collision: " << MI);
730733
734 if (!DebugCounter::shouldExecute(FixCounter)) {
735 DEBUG(dbgs() << "Skipping fix due to debug counter:\n " << MI);
736 continue;
737 }
738
739 // Add the non-base registers of MI as live so we don't use them as
740 // scratch registers.
741 for (unsigned OpI = 0, OpE = MI.getNumOperands(); OpI < OpE; ++OpI) {
742 if (OpI == static_cast(LdI.BaseRegIdx))
743 continue;
744 MachineOperand &MO = MI.getOperand(OpI);
745 if (MO.isReg() && MO.readsReg())
746 LR.addReg(MO.getReg());
747 }
748
731749 for (unsigned ScratchReg : AArch64::GPR64RegClass) {
732750 if (!LR.available(ScratchReg) || MRI.isReserved(ScratchReg))
733751 continue;
352352 bb.1:
353353 RET_ReallyLR
354354 ...
355 ---
356 # Check that non-base registers are considered live when finding a
357 # scratch register by making sure we don't use %x2 for the scratch
358 # register for the inserted ORRXrs.
359 # CHECK-LABEL: name: hwpf_offreg
360 # CHECK: %x3 = ORRXrs %xzr, %x1, 0
361 # CHECK: %w10 = LDRWroX %x3, %x2, 0, 0
362 name: hwpf_offreg
363 tracksRegLiveness: true
364 body: |
365 bb.0:
366 liveins: %w0, %x1, %x2, %x17, %x18
367
368 %w10 = LDRWroX %x1, %x2, 0, 0 :: ("aarch64-strided-access" load 4)
369
370 %x2 = ORRXrs %xzr, %x10, 0
371 %w26 = LDRWroX %x1, %x2, 0, 0
372
373 %w0 = SUBWri %w0, 1, 0
374 %wzr = SUBSWri %w0, 0, 0, implicit-def %nzcv
375 Bcc 9, %bb.0, implicit %nzcv
376
377 bb.1:
378 RET_ReallyLR
379 ...