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Use TableGen to emit information for dwarf register numbers. This makes DwarfRegNum to accept list of numbers instead. Added three different "flavours", but only slightly tested on x86-32/linux. Please check another subtargets if possible, git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@43997 91177308-0d34-0410-b5e6-96231b3b80d8 Anton Korobeynikov 12 years ago
23 changed file(s) with 934 addition(s) and 878 deletion(s). Raw diff Collapse all Expand all
16561656 return 0;
16571657 }
16581658
1659 int ARMRegisterInfo::getDwarfRegNum(unsigned RegNum) const {
1660 assert(0 && "What is the dwarf register number");
1661 return -1;
1662 }
1663
16591664 #include "ARMGenRegisterInfo.inc"
16601665
116116 // Exception handling queries.
117117 unsigned getEHExceptionRegister() const;
118118 unsigned getEHHandlerRegister() const;
119
120 int getDwarfRegNum(unsigned RegNum) const;
119121 };
120122
121123 } // end namespace llvm
2424 }
2525
2626 // Integer registers
27 def R0 : ARMReg< 0, "r0">, DwarfRegNum<0>;
28 def R1 : ARMReg< 1, "r1">, DwarfRegNum<1>;
29 def R2 : ARMReg< 2, "r2">, DwarfRegNum<2>;
30 def R3 : ARMReg< 3, "r3">, DwarfRegNum<3>;
31 def R4 : ARMReg< 4, "r4">, DwarfRegNum<4>;
32 def R5 : ARMReg< 5, "r5">, DwarfRegNum<5>;
33 def R6 : ARMReg< 6, "r6">, DwarfRegNum<6>;
34 def R7 : ARMReg< 7, "r7">, DwarfRegNum<7>;
35 def R8 : ARMReg< 8, "r8">, DwarfRegNum<8>;
36 def R9 : ARMReg< 9, "r9">, DwarfRegNum<9>;
37 def R10 : ARMReg<10, "r10">, DwarfRegNum<10>;
38 def R11 : ARMReg<11, "r11">, DwarfRegNum<11>;
39 def R12 : ARMReg<12, "r12">, DwarfRegNum<12>;
40 def SP : ARMReg<13, "sp">, DwarfRegNum<13>;
41 def LR : ARMReg<14, "lr">, DwarfRegNum<14>;
42 def PC : ARMReg<15, "pc">, DwarfRegNum<15>;
27 def R0 : ARMReg< 0, "r0">, DwarfRegNum<[0]>;
28 def R1 : ARMReg< 1, "r1">, DwarfRegNum<[1]>;
29 def R2 : ARMReg< 2, "r2">, DwarfRegNum<[2]>;
30 def R3 : ARMReg< 3, "r3">, DwarfRegNum<[3]>;
31 def R4 : ARMReg< 4, "r4">, DwarfRegNum<[4]>;
32 def R5 : ARMReg< 5, "r5">, DwarfRegNum<[5]>;
33 def R6 : ARMReg< 6, "r6">, DwarfRegNum<[6]>;
34 def R7 : ARMReg< 7, "r7">, DwarfRegNum<[7]>;
35 def R8 : ARMReg< 8, "r8">, DwarfRegNum<[8]>;
36 def R9 : ARMReg< 9, "r9">, DwarfRegNum<[9]>;
37 def R10 : ARMReg<10, "r10">, DwarfRegNum<[10]>;
38 def R11 : ARMReg<11, "r11">, DwarfRegNum<[11]>;
39 def R12 : ARMReg<12, "r12">, DwarfRegNum<[12]>;
40 def SP : ARMReg<13, "sp">, DwarfRegNum<[13]>;
41 def LR : ARMReg<14, "lr">, DwarfRegNum<[14]>;
42 def PC : ARMReg<15, "pc">, DwarfRegNum<[15]>;
4343
4444 // Float registers
4545 def S0 : ARMFReg< 0, "s0">; def S1 : ARMFReg< 1, "s1">;
479479 return 0;
480480 }
481481
482 int AlphaRegisterInfo::getDwarfRegNum(unsigned RegNum) const {
483 assert(0 && "What is the dwarf register number");
484 return -1;
485 }
486
482487 #include "AlphaGenRegisterInfo.inc"
483488
484489 std::string AlphaRegisterInfo::getPrettyName(unsigned reg)
9292 unsigned getEHExceptionRegister() const;
9393 unsigned getEHHandlerRegister() const;
9494
95 int getDwarfRegNum(unsigned RegNum) const;
96
9597 static std::string getPrettyName(unsigned reg);
9698 };
9799
3434 //#define SP $30
3535
3636 // General-purpose registers
37 def R0 : GPR< 0, "$0">, DwarfRegNum<0>;
38 def R1 : GPR< 1, "$1">, DwarfRegNum<1>;
39 def R2 : GPR< 2, "$2">, DwarfRegNum<2>;
40 def R3 : GPR< 3, "$3">, DwarfRegNum<3>;
41 def R4 : GPR< 4, "$4">, DwarfRegNum<4>;
42 def R5 : GPR< 5, "$5">, DwarfRegNum<5>;
43 def R6 : GPR< 6, "$6">, DwarfRegNum<6>;
44 def R7 : GPR< 7, "$7">, DwarfRegNum<7>;
45 def R8 : GPR< 8, "$8">, DwarfRegNum<8>;
46 def R9 : GPR< 9, "$9">, DwarfRegNum<9>;
47 def R10 : GPR<10, "$10">, DwarfRegNum<10>;
48 def R11 : GPR<11, "$11">, DwarfRegNum<11>;
49 def R12 : GPR<12, "$12">, DwarfRegNum<12>;
50 def R13 : GPR<13, "$13">, DwarfRegNum<13>;
51 def R14 : GPR<14, "$14">, DwarfRegNum<14>;
52 def R15 : GPR<15, "$15">, DwarfRegNum<15>;
53 def R16 : GPR<16, "$16">, DwarfRegNum<16>;
54 def R17 : GPR<17, "$17">, DwarfRegNum<17>;
55 def R18 : GPR<18, "$18">, DwarfRegNum<18>;
56 def R19 : GPR<19, "$19">, DwarfRegNum<19>;
57 def R20 : GPR<20, "$20">, DwarfRegNum<20>;
58 def R21 : GPR<21, "$21">, DwarfRegNum<21>;
59 def R22 : GPR<22, "$22">, DwarfRegNum<22>;
60 def R23 : GPR<23, "$23">, DwarfRegNum<23>;
61 def R24 : GPR<24, "$24">, DwarfRegNum<24>;
62 def R25 : GPR<25, "$25">, DwarfRegNum<25>;
63 def R26 : GPR<26, "$26">, DwarfRegNum<26>;
64 def R27 : GPR<27, "$27">, DwarfRegNum<27>;
65 def R28 : GPR<28, "$28">, DwarfRegNum<28>;
66 def R29 : GPR<29, "$29">, DwarfRegNum<29>;
67 def R30 : GPR<30, "$30">, DwarfRegNum<30>;
68 def R31 : GPR<31, "$31">, DwarfRegNum<31>;
37 def R0 : GPR< 0, "$0">, DwarfRegNum<[0]>;
38 def R1 : GPR< 1, "$1">, DwarfRegNum<[1]>;
39 def R2 : GPR< 2, "$2">, DwarfRegNum<[2]>;
40 def R3 : GPR< 3, "$3">, DwarfRegNum<[3]>;
41 def R4 : GPR< 4, "$4">, DwarfRegNum<[4]>;
42 def R5 : GPR< 5, "$5">, DwarfRegNum<[5]>;
43 def R6 : GPR< 6, "$6">, DwarfRegNum<[6]>;
44 def R7 : GPR< 7, "$7">, DwarfRegNum<[7]>;
45 def R8 : GPR< 8, "$8">, DwarfRegNum<[8]>;
46 def R9 : GPR< 9, "$9">, DwarfRegNum<[9]>;
47 def R10 : GPR<10, "$10">, DwarfRegNum<[10]>;
48 def R11 : GPR<11, "$11">, DwarfRegNum<[11]>;
49 def R12 : GPR<12, "$12">, DwarfRegNum<[12]>;
50 def R13 : GPR<13, "$13">, DwarfRegNum<[13]>;
51 def R14 : GPR<14, "$14">, DwarfRegNum<[14]>;
52 def R15 : GPR<15, "$15">, DwarfRegNum<[15]>;
53 def R16 : GPR<16, "$16">, DwarfRegNum<[16]>;
54 def R17 : GPR<17, "$17">, DwarfRegNum<[17]>;
55 def R18 : GPR<18, "$18">, DwarfRegNum<[18]>;
56 def R19 : GPR<19, "$19">, DwarfRegNum<[19]>;
57 def R20 : GPR<20, "$20">, DwarfRegNum<[20]>;
58 def R21 : GPR<21, "$21">, DwarfRegNum<[21]>;
59 def R22 : GPR<22, "$22">, DwarfRegNum<[22]>;
60 def R23 : GPR<23, "$23">, DwarfRegNum<[23]>;
61 def R24 : GPR<24, "$24">, DwarfRegNum<[24]>;
62 def R25 : GPR<25, "$25">, DwarfRegNum<[25]>;
63 def R26 : GPR<26, "$26">, DwarfRegNum<[26]>;
64 def R27 : GPR<27, "$27">, DwarfRegNum<[27]>;
65 def R28 : GPR<28, "$28">, DwarfRegNum<[28]>;
66 def R29 : GPR<29, "$29">, DwarfRegNum<[29]>;
67 def R30 : GPR<30, "$30">, DwarfRegNum<[30]>;
68 def R31 : GPR<31, "$31">, DwarfRegNum<[31]>;
6969
7070 // Floating-point registers
71 def F0 : FPR< 0, "$f0">, DwarfRegNum<33>;
72 def F1 : FPR< 1, "$f1">, DwarfRegNum<34>;
73 def F2 : FPR< 2, "$f2">, DwarfRegNum<35>;
74 def F3 : FPR< 3, "$f3">, DwarfRegNum<36>;
75 def F4 : FPR< 4, "$f4">, DwarfRegNum<37>;
76 def F5 : FPR< 5, "$f5">, DwarfRegNum<38>;
77 def F6 : FPR< 6, "$f6">, DwarfRegNum<39>;
78 def F7 : FPR< 7, "$f7">, DwarfRegNum<40>;
79 def F8 : FPR< 8, "$f8">, DwarfRegNum<41>;
80 def F9 : FPR< 9, "$f9">, DwarfRegNum<42>;
81 def F10 : FPR<10, "$f10">, DwarfRegNum<43>;
82 def F11 : FPR<11, "$f11">, DwarfRegNum<44>;
83 def F12 : FPR<12, "$f12">, DwarfRegNum<45>;
84 def F13 : FPR<13, "$f13">, DwarfRegNum<46>;
85 def F14 : FPR<14, "$f14">, DwarfRegNum<47>;
86 def F15 : FPR<15, "$f15">, DwarfRegNum<48>;
87 def F16 : FPR<16, "$f16">, DwarfRegNum<49>;
88 def F17 : FPR<17, "$f17">, DwarfRegNum<50>;
89 def F18 : FPR<18, "$f18">, DwarfRegNum<51>;
90 def F19 : FPR<19, "$f19">, DwarfRegNum<52>;
91 def F20 : FPR<20, "$f20">, DwarfRegNum<53>;
92 def F21 : FPR<21, "$f21">, DwarfRegNum<54>;
93 def F22 : FPR<22, "$f22">, DwarfRegNum<55>;
94 def F23 : FPR<23, "$f23">, DwarfRegNum<56>;
95 def F24 : FPR<24, "$f24">, DwarfRegNum<57>;
96 def F25 : FPR<25, "$f25">, DwarfRegNum<58>;
97 def F26 : FPR<26, "$f26">, DwarfRegNum<59>;
98 def F27 : FPR<27, "$f27">, DwarfRegNum<60>;
99 def F28 : FPR<28, "$f28">, DwarfRegNum<61>;
100 def F29 : FPR<29, "$f29">, DwarfRegNum<62>;
101 def F30 : FPR<30, "$f30">, DwarfRegNum<63>;
102 def F31 : FPR<31, "$f31">, DwarfRegNum<64>;
71 def F0 : FPR< 0, "$f0">, DwarfRegNum<[33]>;
72 def F1 : FPR< 1, "$f1">, DwarfRegNum<[34]>;
73 def F2 : FPR< 2, "$f2">, DwarfRegNum<[35]>;
74 def F3 : FPR< 3, "$f3">, DwarfRegNum<[36]>;
75 def F4 : FPR< 4, "$f4">, DwarfRegNum<[37]>;
76 def F5 : FPR< 5, "$f5">, DwarfRegNum<[38]>;
77 def F6 : FPR< 6, "$f6">, DwarfRegNum<[39]>;
78 def F7 : FPR< 7, "$f7">, DwarfRegNum<[40]>;
79 def F8 : FPR< 8, "$f8">, DwarfRegNum<[41]>;
80 def F9 : FPR< 9, "$f9">, DwarfRegNum<[42]>;
81 def F10 : FPR<10, "$f10">, DwarfRegNum<[43]>;
82 def F11 : FPR<11, "$f11">, DwarfRegNum<[44]>;
83 def F12 : FPR<12, "$f12">, DwarfRegNum<[45]>;
84 def F13 : FPR<13, "$f13">, DwarfRegNum<[46]>;
85 def F14 : FPR<14, "$f14">, DwarfRegNum<[47]>;
86 def F15 : FPR<15, "$f15">, DwarfRegNum<[48]>;
87 def F16 : FPR<16, "$f16">, DwarfRegNum<[49]>;
88 def F17 : FPR<17, "$f17">, DwarfRegNum<[50]>;
89 def F18 : FPR<18, "$f18">, DwarfRegNum<[51]>;
90 def F19 : FPR<19, "$f19">, DwarfRegNum<[52]>;
91 def F20 : FPR<20, "$f20">, DwarfRegNum<[53]>;
92 def F21 : FPR<21, "$f21">, DwarfRegNum<[54]>;
93 def F22 : FPR<22, "$f22">, DwarfRegNum<[55]>;
94 def F23 : FPR<23, "$f23">, DwarfRegNum<[56]>;
95 def F24 : FPR<24, "$f24">, DwarfRegNum<[57]>;
96 def F25 : FPR<25, "$f25">, DwarfRegNum<[58]>;
97 def F26 : FPR<26, "$f26">, DwarfRegNum<[59]>;
98 def F27 : FPR<27, "$f27">, DwarfRegNum<[60]>;
99 def F28 : FPR<28, "$f28">, DwarfRegNum<[61]>;
100 def F29 : FPR<29, "$f29">, DwarfRegNum<[62]>;
101 def F30 : FPR<30, "$f30">, DwarfRegNum<[63]>;
102 def F31 : FPR<31, "$f31">, DwarfRegNum<[64]>;
103103
104104 // //#define FP $15
105105 // //#define RA $26
450450 return 0;
451451 }
452452
453 int IA64RegisterInfo::getDwarfRegNum(unsigned RegNum) const {
454 assert(0 && "What is the dwarf register number");
455 return -1;
456 }
457
453458 #include "IA64GenRegisterInfo.inc"
454459
8383 // Exception handling queries.
8484 unsigned getEHExceptionRegister() const;
8585 unsigned getEHHandlerRegister() const;
86
87 int getDwarfRegNum(unsigned RegNum) const;
8688 };
8789
8890 } // End llvm namespace
3636 }
3737
3838 /* general registers */
39 def r0 : GR< 0, "r0">, DwarfRegNum<0>;
40 def r1 : GR< 1, "r1">, DwarfRegNum<1>;
41 def r2 : GR< 2, "r2">, DwarfRegNum<2>;
42 def r3 : GR< 3, "r3">, DwarfRegNum<3>;
43 def r4 : GR< 4, "r4">, DwarfRegNum<4>;
44 def r5 : GR< 5, "r5">, DwarfRegNum<5>;
45 def r6 : GR< 6, "r6">, DwarfRegNum<6>;
46 def r7 : GR< 7, "r7">, DwarfRegNum<7>;
47 def r8 : GR< 8, "r8">, DwarfRegNum<8>;
48 def r9 : GR< 9, "r9">, DwarfRegNum<9>;
49 def r10 : GR< 10, "r10">, DwarfRegNum<10>;
50 def r11 : GR< 11, "r11">, DwarfRegNum<11>;
51 def r12 : GR< 12, "r12">, DwarfRegNum<12>;
52 def r13 : GR< 13, "r13">, DwarfRegNum<13>;
53 def r14 : GR< 14, "r14">, DwarfRegNum<14>;
54 def r15 : GR< 15, "r15">, DwarfRegNum<15>;
55 def r16 : GR< 16, "r16">, DwarfRegNum<16>;
56 def r17 : GR< 17, "r17">, DwarfRegNum<17>;
57 def r18 : GR< 18, "r18">, DwarfRegNum<18>;
58 def r19 : GR< 19, "r19">, DwarfRegNum<19>;
59 def r20 : GR< 20, "r20">, DwarfRegNum<20>;
60 def r21 : GR< 21, "r21">, DwarfRegNum<21>;
61 def r22 : GR< 22, "r22">, DwarfRegNum<22>;
62 def r23 : GR< 23, "r23">, DwarfRegNum<23>;
63 def r24 : GR< 24, "r24">, DwarfRegNum<24>;
64 def r25 : GR< 25, "r25">, DwarfRegNum<25>;
65 def r26 : GR< 26, "r26">, DwarfRegNum<26>;
66 def r27 : GR< 27, "r27">, DwarfRegNum<27>;
67 def r28 : GR< 28, "r28">, DwarfRegNum<28>;
68 def r29 : GR< 29, "r29">, DwarfRegNum<29>;
69 def r30 : GR< 30, "r30">, DwarfRegNum<30>;
70 def r31 : GR< 31, "r31">, DwarfRegNum<31>;
71 def r32 : GR< 32, "r32">, DwarfRegNum<32>;
72 def r33 : GR< 33, "r33">, DwarfRegNum<33>;
73 def r34 : GR< 34, "r34">, DwarfRegNum<34>;
74 def r35 : GR< 35, "r35">, DwarfRegNum<35>;
75 def r36 : GR< 36, "r36">, DwarfRegNum<36>;
76 def r37 : GR< 37, "r37">, DwarfRegNum<37>;
77 def r38 : GR< 38, "r38">, DwarfRegNum<38>;
78 def r39 : GR< 39, "r39">, DwarfRegNum<39>;
79 def r40 : GR< 40, "r40">, DwarfRegNum<40>;
80 def r41 : GR< 41, "r41">, DwarfRegNum<41>;
81 def r42 : GR< 42, "r42">, DwarfRegNum<42>;
82 def r43 : GR< 43, "r43">, DwarfRegNum<43>;
83 def r44 : GR< 44, "r44">, DwarfRegNum<44>;
84 def r45 : GR< 45, "r45">, DwarfRegNum<45>;
85 def r46 : GR< 46, "r46">, DwarfRegNum<46>;
86 def r47 : GR< 47, "r47">, DwarfRegNum<47>;
87 def r48 : GR< 48, "r48">, DwarfRegNum<48>;
88 def r49 : GR< 49, "r49">, DwarfRegNum<49>;
89 def r50 : GR< 50, "r50">, DwarfRegNum<50>;
90 def r51 : GR< 51, "r51">, DwarfRegNum<51>;
91 def r52 : GR< 52, "r52">, DwarfRegNum<52>;
92 def r53 : GR< 53, "r53">, DwarfRegNum<53>;
93 def r54 : GR< 54, "r54">, DwarfRegNum<54>;
94 def r55 : GR< 55, "r55">, DwarfRegNum<55>;
95 def r56 : GR< 56, "r56">, DwarfRegNum<56>;
96 def r57 : GR< 57, "r57">, DwarfRegNum<57>;
97 def r58 : GR< 58, "r58">, DwarfRegNum<58>;
98 def r59 : GR< 59, "r59">, DwarfRegNum<59>;
99 def r60 : GR< 60, "r60">, DwarfRegNum<60>;
100 def r61 : GR< 61, "r61">, DwarfRegNum<61>;
101 def r62 : GR< 62, "r62">, DwarfRegNum<62>;
102 def r63 : GR< 63, "r63">, DwarfRegNum<63>;
103 def r64 : GR< 64, "r64">, DwarfRegNum<64>;
104 def r65 : GR< 65, "r65">, DwarfRegNum<65>;
105 def r66 : GR< 66, "r66">, DwarfRegNum<66>;
106 def r67 : GR< 67, "r67">, DwarfRegNum<67>;
107 def r68 : GR< 68, "r68">, DwarfRegNum<68>;
108 def r69 : GR< 69, "r69">, DwarfRegNum<69>;
109 def r70 : GR< 70, "r70">, DwarfRegNum<70>;
110 def r71 : GR< 71, "r71">, DwarfRegNum<71>;
111 def r72 : GR< 72, "r72">, DwarfRegNum<72>;
112 def r73 : GR< 73, "r73">, DwarfRegNum<73>;
113 def r74 : GR< 74, "r74">, DwarfRegNum<74>;
114 def r75 : GR< 75, "r75">, DwarfRegNum<75>;
115 def r76 : GR< 76, "r76">, DwarfRegNum<76>;
116 def r77 : GR< 77, "r77">, DwarfRegNum<77>;
117 def r78 : GR< 78, "r78">, DwarfRegNum<78>;
118 def r79 : GR< 79, "r79">, DwarfRegNum<79>;
119 def r80 : GR< 80, "r80">, DwarfRegNum<80>;
120 def r81 : GR< 81, "r81">, DwarfRegNum<81>;
121 def r82 : GR< 82, "r82">, DwarfRegNum<82>;
122 def r83 : GR< 83, "r83">, DwarfRegNum<83>;
123 def r84 : GR< 84, "r84">, DwarfRegNum<84>;
124 def r85 : GR< 85, "r85">, DwarfRegNum<85>;
125 def r86 : GR< 86, "r86">, DwarfRegNum<86>;
126 def r87 : GR< 87, "r87">, DwarfRegNum<87>;
127 def r88 : GR< 88, "r88">, DwarfRegNum<88>;
128 def r89 : GR< 89, "r89">, DwarfRegNum<89>;
129 def r90 : GR< 90, "r90">, DwarfRegNum<90>;
130 def r91 : GR< 91, "r91">, DwarfRegNum<91>;
131 def r92 : GR< 92, "r92">, DwarfRegNum<92>;
132 def r93 : GR< 93, "r93">, DwarfRegNum<93>;
133 def r94 : GR< 94, "r94">, DwarfRegNum<94>;
134 def r95 : GR< 95, "r95">, DwarfRegNum<95>;
135 def r96 : GR< 96, "r96">, DwarfRegNum<96>;
136 def r97 : GR< 97, "r97">, DwarfRegNum<97>;
137 def r98 : GR< 98, "r98">, DwarfRegNum<98>;
138 def r99 : GR< 99, "r99">, DwarfRegNum<99>;
139 def r100 : GR< 100, "r100">, DwarfRegNum<100>;
140 def r101 : GR< 101, "r101">, DwarfRegNum<101>;
141 def r102 : GR< 102, "r102">, DwarfRegNum<102>;
142 def r103 : GR< 103, "r103">, DwarfRegNum<103>;
143 def r104 : GR< 104, "r104">, DwarfRegNum<104>;
144 def r105 : GR< 105, "r105">, DwarfRegNum<105>;
145 def r106 : GR< 106, "r106">, DwarfRegNum<106>;
146 def r107 : GR< 107, "r107">, DwarfRegNum<107>;
147 def r108 : GR< 108, "r108">, DwarfRegNum<108>;
148 def r109 : GR< 109, "r109">, DwarfRegNum<109>;
149 def r110 : GR< 110, "r110">, DwarfRegNum<110>;
150 def r111 : GR< 111, "r111">, DwarfRegNum<111>;
151 def r112 : GR< 112, "r112">, DwarfRegNum<112>;
152 def r113 : GR< 113, "r113">, DwarfRegNum<113>;
153 def r114 : GR< 114, "r114">, DwarfRegNum<114>;
154 def r115 : GR< 115, "r115">, DwarfRegNum<115>;
155 def r116 : GR< 116, "r116">, DwarfRegNum<116>;
156 def r117 : GR< 117, "r117">, DwarfRegNum<117>;
157 def r118 : GR< 118, "r118">, DwarfRegNum<118>;
158 def r119 : GR< 119, "r119">, DwarfRegNum<119>;
159 def r120 : GR< 120, "r120">, DwarfRegNum<120>;
160 def r121 : GR< 121, "r121">, DwarfRegNum<121>;
161 def r122 : GR< 122, "r122">, DwarfRegNum<122>;
162 def r123 : GR< 123, "r123">, DwarfRegNum<123>;
163 def r124 : GR< 124, "r124">, DwarfRegNum<124>;
164 def r125 : GR< 125, "r125">, DwarfRegNum<125>;
165 def r126 : GR< 126, "r126">, DwarfRegNum<126>;
166 def r127 : GR< 127, "r127">, DwarfRegNum<127>;
39 def r0 : GR< 0, "r0">, DwarfRegNum<[0]>;
40 def r1 : GR< 1, "r1">, DwarfRegNum<[1]>;
41 def r2 : GR< 2, "r2">, DwarfRegNum<[2]>;
42 def r3 : GR< 3, "r3">, DwarfRegNum<[3]>;
43 def r4 : GR< 4, "r4">, DwarfRegNum<[4]>;
44 def r5 : GR< 5, "r5">, DwarfRegNum<[5]>;
45 def r6 : GR< 6, "r6">, DwarfRegNum<[6]>;
46 def r7 : GR< 7, "r7">, DwarfRegNum<[7]>;
47 def r8 : GR< 8, "r8">, DwarfRegNum<[8]>;
48 def r9 : GR< 9, "r9">, DwarfRegNum<[9]>;
49 def r10 : GR< 10, "r10">, DwarfRegNum<[10]>;
50 def r11 : GR< 11, "r11">, DwarfRegNum<[11]>;
51 def r12 : GR< 12, "r12">, DwarfRegNum<[12]>;
52 def r13 : GR< 13, "r13">, DwarfRegNum<[13]>;
53 def r14 : GR< 14, "r14">, DwarfRegNum<[14]>;
54 def r15 : GR< 15, "r15">, DwarfRegNum<[15]>;
55 def r16 : GR< 16, "r16">, DwarfRegNum<[16]>;
56 def r17 : GR< 17, "r17">, DwarfRegNum<[17]>;
57 def r18 : GR< 18, "r18">, DwarfRegNum<[18]>;
58 def r19 : GR< 19, "r19">, DwarfRegNum<[19]>;
59 def r20 : GR< 20, "r20">, DwarfRegNum<[20]>;
60 def r21 : GR< 21, "r21">, DwarfRegNum<[21]>;
61 def r22 : GR< 22, "r22">, DwarfRegNum<[22]>;
62 def r23 : GR< 23, "r23">, DwarfRegNum<[23]>;
63 def r24 : GR< 24, "r24">, DwarfRegNum<[24]>;
64 def r25 : GR< 25, "r25">, DwarfRegNum<[25]>;
65 def r26 : GR< 26, "r26">, DwarfRegNum<[26]>;
66 def r27 : GR< 27, "r27">, DwarfRegNum<[27]>;
67 def r28 : GR< 28, "r28">, DwarfRegNum<[28]>;
68 def r29 : GR< 29, "r29">, DwarfRegNum<[29]>;
69 def r30 : GR< 30, "r30">, DwarfRegNum<[30]>;
70 def r31 : GR< 31, "r31">, DwarfRegNum<[31]>;
71 def r32 : GR< 32, "r32">, DwarfRegNum<[32]>;
72 def r33 : GR< 33, "r33">, DwarfRegNum<[33]>;
73 def r34 : GR< 34, "r34">, DwarfRegNum<[34]>;
74 def r35 : GR< 35, "r35">, DwarfRegNum<[35]>;
75 def r36 : GR< 36, "r36">, DwarfRegNum<[36]>;
76 def r37 : GR< 37, "r37">, DwarfRegNum<[37]>;
77 def r38 : GR< 38, "r38">, DwarfRegNum<[38]>;
78 def r39 : GR< 39, "r39">, DwarfRegNum<[39]>;
79 def r40 : GR< 40, "r40">, DwarfRegNum<[40]>;
80 def r41 : GR< 41, "r41">, DwarfRegNum<[41]>;
81 def r42 : GR< 42, "r42">, DwarfRegNum<[42]>;
82 def r43 : GR< 43, "r43">, DwarfRegNum<[43]>;
83 def r44 : GR< 44, "r44">, DwarfRegNum<[44]>;
84 def r45 : GR< 45, "r45">, DwarfRegNum<[45]>;
85 def r46 : GR< 46, "r46">, DwarfRegNum<[46]>;
86 def r47 : GR< 47, "r47">, DwarfRegNum<[47]>;
87 def r48 : GR< 48, "r48">, DwarfRegNum<[48]>;
88 def r49 : GR< 49, "r49">, DwarfRegNum<[49]>;
89 def r50 : GR< 50, "r50">, DwarfRegNum<[50]>;
90 def r51 : GR< 51, "r51">, DwarfRegNum<[51]>;
91 def r52 : GR< 52, "r52">, DwarfRegNum<[52]>;
92 def r53 : GR< 53, "r53">, DwarfRegNum<[53]>;
93 def r54 : GR< 54, "r54">, DwarfRegNum<[54]>;
94 def r55 : GR< 55, "r55">, DwarfRegNum<[55]>;
95 def r56 : GR< 56, "r56">, DwarfRegNum<[56]>;
96 def r57 : GR< 57, "r57">, DwarfRegNum<[57]>;
97 def r58 : GR< 58, "r58">, DwarfRegNum<[58]>;
98 def r59 : GR< 59, "r59">, DwarfRegNum<[59]>;
99 def r60 : GR< 60, "r60">, DwarfRegNum<[60]>;
100 def r61 : GR< 61, "r61">, DwarfRegNum<[61]>;
101 def r62 : GR< 62, "r62">, DwarfRegNum<[62]>;
102 def r63 : GR< 63, "r63">, DwarfRegNum<[63]>;
103 def r64 : GR< 64, "r64">, DwarfRegNum<[64]>;
104 def r65 : GR< 65, "r65">, DwarfRegNum<[65]>;
105 def r66 : GR< 66, "r66">, DwarfRegNum<[66]>;
106 def r67 : GR< 67, "r67">, DwarfRegNum<[67]>;
107 def r68 : GR< 68, "r68">, DwarfRegNum<[68]>;
108 def r69 : GR< 69, "r69">, DwarfRegNum<[69]>;
109 def r70 : GR< 70, "r70">, DwarfRegNum<[70]>;
110 def r71 : GR< 71, "r71">, DwarfRegNum<[71]>;
111 def r72 : GR< 72, "r72">, DwarfRegNum<[72]>;
112 def r73 : GR< 73, "r73">, DwarfRegNum<[73]>;
113 def r74 : GR< 74, "r74">, DwarfRegNum<[74]>;
114 def r75 : GR< 75, "r75">, DwarfRegNum<[75]>;
115 def r76 : GR< 76, "r76">, DwarfRegNum<[76]>;
116 def r77 : GR< 77, "r77">, DwarfRegNum<[77]>;
117 def r78 : GR< 78, "r78">, DwarfRegNum<[78]>;
118 def r79 : GR< 79, "r79">, DwarfRegNum<[79]>;
119 def r80 : GR< 80, "r80">, DwarfRegNum<[80]>;
120 def r81 : GR< 81, "r81">, DwarfRegNum<[81]>;
121 def r82 : GR< 82, "r82">, DwarfRegNum<[82]>;
122 def r83 : GR< 83, "r83">, DwarfRegNum<[83]>;
123 def r84 : GR< 84, "r84">, DwarfRegNum<[84]>;
124 def r85 : GR< 85, "r85">, DwarfRegNum<[85]>;
125 def r86 : GR< 86, "r86">, DwarfRegNum<[86]>;
126 def r87 : GR< 87, "r87">, DwarfRegNum<[87]>;
127 def r88 : GR< 88, "r88">, DwarfRegNum<[88]>;
128 def r89 : GR< 89, "r89">, DwarfRegNum<[89]>;
129 def r90 : GR< 90, "r90">, DwarfRegNum<[90]>;
130 def r91 : GR< 91, "r91">, DwarfRegNum<[91]>;
131 def r92 : GR< 92, "r92">, DwarfRegNum<[92]>;
132 def r93 : GR< 93, "r93">, DwarfRegNum<[93]>;
133 def r94 : GR< 94, "r94">, DwarfRegNum<[94]>;
134 def r95 : GR< 95, "r95">, DwarfRegNum<[95]>;
135 def r96 : GR< 96, "r96">, DwarfRegNum<[96]>;
136 def r97 : GR< 97, "r97">, DwarfRegNum<[97]>;
137 def r98 : GR< 98, "r98">, DwarfRegNum<[98]>;
138 def r99 : GR< 99, "r99">, DwarfRegNum<[99]>;
139 def r100 : GR< 100, "r100">, DwarfRegNum<[100]>;
140 def r101 : GR< 101, "r101">, DwarfRegNum<[101]>;
141 def r102 : GR< 102, "r102">, DwarfRegNum<[102]>;
142 def r103 : GR< 103, "r103">, DwarfRegNum<[103]>;
143 def r104 : GR< 104, "r104">, DwarfRegNum<[104]>;
144 def r105 : GR< 105, "r105">, DwarfRegNum<[105]>;
145 def r106 : GR< 106, "r106">, DwarfRegNum<[106]>;
146 def r107 : GR< 107, "r107">, DwarfRegNum<[107]>;
147 def r108 : GR< 108, "r108">, DwarfRegNum<[108]>;
148 def r109 : GR< 109, "r109">, DwarfRegNum<[109]>;
149 def r110 : GR< 110, "r110">, DwarfRegNum<[110]>;
150 def r111 : GR< 111, "r111">, DwarfRegNum<[111]>;
151 def r112 : GR< 112, "r112">, DwarfRegNum<[112]>;
152 def r113 : GR< 113, "r113">, DwarfRegNum<[113]>;
153 def r114 : GR< 114, "r114">, DwarfRegNum<[114]>;
154 def r115 : GR< 115, "r115">, DwarfRegNum<[115]>;
155 def r116 : GR< 116, "r116">, DwarfRegNum<[116]>;
156 def r117 : GR< 117, "r117">, DwarfRegNum<[117]>;
157 def r118 : GR< 118, "r118">, DwarfRegNum<[118]>;
158 def r119 : GR< 119, "r119">, DwarfRegNum<[119]>;
159 def r120 : GR< 120, "r120">, DwarfRegNum<[120]>;
160 def r121 : GR< 121, "r121">, DwarfRegNum<[121]>;
161 def r122 : GR< 122, "r122">, DwarfRegNum<[122]>;
162 def r123 : GR< 123, "r123">, DwarfRegNum<[123]>;
163 def r124 : GR< 124, "r124">, DwarfRegNum<[124]>;
164 def r125 : GR< 125, "r125">, DwarfRegNum<[125]>;
165 def r126 : GR< 126, "r126">, DwarfRegNum<[126]>;
166 def r127 : GR< 127, "r127">, DwarfRegNum<[127]>;
167167
168168 /* floating-point registers */
169 def F0 : FP< 0, "f0">, DwarfRegNum<128>;
170 def F1 : FP< 1, "f1">, DwarfRegNum<129>;
171 def F2 : FP< 2, "f2">, DwarfRegNum<130>;
172 def F3 : FP< 3, "f3">, DwarfRegNum<131>;
173 def F4 : FP< 4, "f4">, DwarfRegNum<132>;
174 def F5 : FP< 5, "f5">, DwarfRegNum<133>;
175 def F6 : FP< 6, "f6">, DwarfRegNum<134>;
176 def F7 : FP< 7, "f7">, DwarfRegNum<135>;
177 def F8 : FP< 8, "f8">, DwarfRegNum<136>;
178 def F9 : FP< 9, "f9">, DwarfRegNum<137>;
179 def F10 : FP< 10, "f10">, DwarfRegNum<138>;
180 def F11 : FP< 11, "f11">, DwarfRegNum<139>;
181 def F12 : FP< 12, "f12">, DwarfRegNum<140>;
182 def F13 : FP< 13, "f13">, DwarfRegNum<141>;
183 def F14 : FP< 14, "f14">, DwarfRegNum<142>;
184 def F15 : FP< 15, "f15">, DwarfRegNum<143>;
185 def F16 : FP< 16, "f16">, DwarfRegNum<144>;
186 def F17 : FP< 17, "f17">, DwarfRegNum<145>;
187 def F18 : FP< 18, "f18">, DwarfRegNum<146>;
188 def F19 : FP< 19, "f19">, DwarfRegNum<147>;
189 def F20 : FP< 20, "f20">, DwarfRegNum<148>;
190 def F21 : FP< 21, "f21">, DwarfRegNum<149>;
191 def F22 : FP< 22, "f22">, DwarfRegNum<150>;
192 def F23 : FP< 23, "f23">, DwarfRegNum<151>;
193 def F24 : FP< 24, "f24">, DwarfRegNum<152>;
194 def F25 : FP< 25, "f25">, DwarfRegNum<153>;
195 def F26 : FP< 26, "f26">, DwarfRegNum<154>;
196 def F27 : FP< 27, "f27">, DwarfRegNum<155>;
197 def F28 : FP< 28, "f28">, DwarfRegNum<156>;
198 def F29 : FP< 29, "f29">, DwarfRegNum<157>;
199 def F30 : FP< 30, "f30">, DwarfRegNum<158>;
200 def F31 : FP< 31, "f31">, DwarfRegNum<159>;
201 def F32 : FP< 32, "f32">, DwarfRegNum<160>;
202 def F33 : FP< 33, "f33">, DwarfRegNum<161>;
203 def F34 : FP< 34, "f34">, DwarfRegNum<162>;
204 def F35 : FP< 35, "f35">, DwarfRegNum<163>;
205 def F36 : FP< 36, "f36">, DwarfRegNum<164>;
206 def F37 : FP< 37, "f37">, DwarfRegNum<165>;
207 def F38 : FP< 38, "f38">, DwarfRegNum<166>;
208 def F39 : FP< 39, "f39">, DwarfRegNum<167>;
209 def F40 : FP< 40, "f40">, DwarfRegNum<168>;
210 def F41 : FP< 41, "f41">, DwarfRegNum<169>;
211 def F42 : FP< 42, "f42">, DwarfRegNum<170>;
212 def F43 : FP< 43, "f43">, DwarfRegNum<171>;
213 def F44 : FP< 44, "f44">, DwarfRegNum<172>;
214 def F45 : FP< 45, "f45">, DwarfRegNum<173>;
215 def F46 : FP< 46, "f46">, DwarfRegNum<174>;
216 def F47 : FP< 47, "f47">, DwarfRegNum<175>;
217 def F48 : FP< 48, "f48">, DwarfRegNum<176>;
218 def F49 : FP< 49, "f49">, DwarfRegNum<177>;
219 def F50 : FP< 50, "f50">, DwarfRegNum<178>;
220 def F51 : FP< 51, "f51">, DwarfRegNum<179>;
221 def F52 : FP< 52, "f52">, DwarfRegNum<180>;
222 def F53 : FP< 53, "f53">, DwarfRegNum<181>;
223 def F54 : FP< 54, "f54">, DwarfRegNum<182>;
224 def F55 : FP< 55, "f55">, DwarfRegNum<183>;
225 def F56 : FP< 56, "f56">, DwarfRegNum<184>;
226 def F57 : FP< 57, "f57">, DwarfRegNum<185>;
227 def F58 : FP< 58, "f58">, DwarfRegNum<186>;
228 def F59 : FP< 59, "f59">, DwarfRegNum<187>;
229 def F60 : FP< 60, "f60">, DwarfRegNum<188>;
230 def F61 : FP< 61, "f61">, DwarfRegNum<189>;
231 def F62 : FP< 62, "f62">, DwarfRegNum<190>;
232 def F63 : FP< 63, "f63">, DwarfRegNum<191>;
233 def F64 : FP< 64, "f64">, DwarfRegNum<192>;
234 def F65 : FP< 65, "f65">, DwarfRegNum<193>;
235 def F66 : FP< 66, "f66">, DwarfRegNum<194>;
236 def F67 : FP< 67, "f67">, DwarfRegNum<195>;
237 def F68 : FP< 68, "f68">, DwarfRegNum<196>;
238 def F69 : FP< 69, "f69">, DwarfRegNum<197>;
239 def F70 : FP< 70, "f70">, DwarfRegNum<198>;
240 def F71 : FP< 71, "f71">, DwarfRegNum<199>;
241 def F72 : FP< 72, "f72">, DwarfRegNum<200>;
242 def F73 : FP< 73, "f73">, DwarfRegNum<201>;
243 def F74 : FP< 74, "f74">, DwarfRegNum<202>;
244 def F75 : FP< 75, "f75">, DwarfRegNum<203>;
245 def F76 : FP< 76, "f76">, DwarfRegNum<204>;
246 def F77 : FP< 77, "f77">, DwarfRegNum<205>;
247 def F78 : FP< 78, "f78">, DwarfRegNum<206>;
248 def F79 : FP< 79, "f79">, DwarfRegNum<207>;
249 def F80 : FP< 80, "f80">, DwarfRegNum<208>;
250 def F81 : FP< 81, "f81">, DwarfRegNum<209>;
251 def F82 : FP< 82, "f82">, DwarfRegNum<210>;
252 def F83 : FP< 83, "f83">, DwarfRegNum<211>;
253 def F84 : FP< 84, "f84">, DwarfRegNum<212>;
254 def F85 : FP< 85, "f85">, DwarfRegNum<213>;
255 def F86 : FP< 86, "f86">, DwarfRegNum<214>;
256 def F87 : FP< 87, "f87">, DwarfRegNum<215>;
257 def F88 : FP< 88, "f88">, DwarfRegNum<216>;
258 def F89 : FP< 89, "f89">, DwarfRegNum<217>;
259 def F90 : FP< 90, "f90">, DwarfRegNum<218>;
260 def F91 : FP< 91, "f91">, DwarfRegNum<219>;
261 def F92 : FP< 92, "f92">, DwarfRegNum<220>;
262 def F93 : FP< 93, "f93">, DwarfRegNum<221>;
263 def F94 : FP< 94, "f94">, DwarfRegNum<222>;
264 def F95 : FP< 95, "f95">, DwarfRegNum<223>;
265 def F96 : FP< 96, "f96">, DwarfRegNum<224>;
266 def F97 : FP< 97, "f97">, DwarfRegNum<225>;
267 def F98 : FP< 98, "f98">, DwarfRegNum<226>;
268 def F99 : FP< 99, "f99">, DwarfRegNum<227>;
269 def F100 : FP< 100, "f100">, DwarfRegNum<228>;
270 def F101 : FP< 101, "f101">, DwarfRegNum<229>;
271 def F102 : FP< 102, "f102">, DwarfRegNum<230>;
272 def F103 : FP< 103, "f103">, DwarfRegNum<231>;
273 def F104 : FP< 104, "f104">, DwarfRegNum<232>;
274 def F105 : FP< 105, "f105">, DwarfRegNum<233>;
275 def F106 : FP< 106, "f106">, DwarfRegNum<234>;
276 def F107 : FP< 107, "f107">, DwarfRegNum<235>;
277 def F108 : FP< 108, "f108">, DwarfRegNum<236>;
278 def F109 : FP< 109, "f109">, DwarfRegNum<237>;
279 def F110 : FP< 110, "f110">, DwarfRegNum<238>;
280 def F111 : FP< 111, "f111">, DwarfRegNum<239>;
281 def F112 : FP< 112, "f112">, DwarfRegNum<240>;
282 def F113 : FP< 113, "f113">, DwarfRegNum<241>;
283 def F114 : FP< 114, "f114">, DwarfRegNum<242>;
284 def F115 : FP< 115, "f115">, DwarfRegNum<243>;
285 def F116 : FP< 116, "f116">, DwarfRegNum<244>;
286 def F117 : FP< 117, "f117">, DwarfRegNum<245>;
287 def F118 : FP< 118, "f118">, DwarfRegNum<246>;
288 def F119 : FP< 119, "f119">, DwarfRegNum<247>;
289 def F120 : FP< 120, "f120">, DwarfRegNum<248>;
290 def F121 : FP< 121, "f121">, DwarfRegNum<249>;
291 def F122 : FP< 122, "f122">, DwarfRegNum<250>;
292 def F123 : FP< 123, "f123">, DwarfRegNum<251>;
293 def F124 : FP< 124, "f124">, DwarfRegNum<252>;
294 def F125 : FP< 125, "f125">, DwarfRegNum<253>;
295 def F126 : FP< 126, "f126">, DwarfRegNum<254>;
296 def F127 : FP< 127, "f127">, DwarfRegNum<255>;
169 def F0 : FP< 0, "f0">, DwarfRegNum<[128]>;
170 def F1 : FP< 1, "f1">, DwarfRegNum<[129]>;
171 def F2 : FP< 2, "f2">, DwarfRegNum<[130]>;
172 def F3 : FP< 3, "f3">, DwarfRegNum<[131]>;
173 def F4 : FP< 4, "f4">, DwarfRegNum<[132]>;
174 def F5 : FP< 5, "f5">, DwarfRegNum<[133]>;
175 def F6 : FP< 6, "f6">, DwarfRegNum<[134]>;
176 def F7 : FP< 7, "f7">, DwarfRegNum<[135]>;
177 def F8 : FP< 8, "f8">, DwarfRegNum<[136]>;
178 def F9 : FP< 9, "f9">, DwarfRegNum<[137]>;
179 def F10 : FP< 10, "f10">, DwarfRegNum<[138]>;
180 def F11 : FP< 11, "f11">, DwarfRegNum<[139]>;
181 def F12 : FP< 12, "f12">, DwarfRegNum<[140]>;
182 def F13 : FP< 13, "f13">, DwarfRegNum<[141]>;
183 def F14 : FP< 14, "f14">, DwarfRegNum<[142]>;
184 def F15 : FP< 15, "f15">, DwarfRegNum<[143]>;
185 def F16 : FP< 16, "f16">, DwarfRegNum<[144]>;
186 def F17 : FP< 17, "f17">, DwarfRegNum<[145]>;
187 def F18 : FP< 18, "f18">, DwarfRegNum<[146]>;
188 def F19 : FP< 19, "f19">, DwarfRegNum<[147]>;
189 def F20 : FP< 20, "f20">, DwarfRegNum<[148]>;
190 def F21 : FP< 21, "f21">, DwarfRegNum<[149]>;
191 def F22 : FP< 22, "f22">, DwarfRegNum<[150]>;
192 def F23 : FP< 23, "f23">, DwarfRegNum<[151]>;
193 def F24 : FP< 24, "f24">, DwarfRegNum<[152]>;
194 def F25 : FP< 25, "f25">, DwarfRegNum<[153]>;
195 def F26 : FP< 26, "f26">, DwarfRegNum<[154]>;
196 def F27 : FP< 27, "f27">, DwarfRegNum<[155]>;
197 def F28 : FP< 28, "f28">, DwarfRegNum<[156]>;
198 def F29 : FP< 29, "f29">, DwarfRegNum<[157]>;
199 def F30 : FP< 30, "f30">, DwarfRegNum<[158]>;
200 def F31 : FP< 31, "f31">, DwarfRegNum<[159]>;
201 def F32 : FP< 32, "f32">, DwarfRegNum<[160]>;
202 def F33 : FP< 33, "f33">, DwarfRegNum<[161]>;
203 def F34 : FP< 34, "f34">, DwarfRegNum<[162]>;
204 def F35 : FP< 35, "f35">, DwarfRegNum<[163]>;
205 def F36 : FP< 36, "f36">, DwarfRegNum<[164]>;
206 def F37 : FP< 37, "f37">, DwarfRegNum<[165]>;
207 def F38 : FP< 38, "f38">, DwarfRegNum<[166]>;
208 def F39 : FP< 39, "f39">, DwarfRegNum<[167]>;
209 def F40 : FP< 40, "f40">, DwarfRegNum<[168]>;
210 def F41 : FP< 41, "f41">, DwarfRegNum<[169]>;
211 def F42 : FP< 42, "f42">, DwarfRegNum<[170]>;
212 def F43 : FP< 43, "f43">, DwarfRegNum<[171]>;
213 def F44 : FP< 44, "f44">, DwarfRegNum<[172]>;
214 def F45 : FP< 45, "f45">, DwarfRegNum<[173]>;
215 def F46 : FP< 46, "f46">, DwarfRegNum<[174]>;
216 def F47 : FP< 47, "f47">, DwarfRegNum<[175]>;
217 def F48 : FP< 48, "f48">, DwarfRegNum<[176]>;
218 def F49 : FP< 49, "f49">, DwarfRegNum<[177]>;
219 def F50 : FP< 50, "f50">, DwarfRegNum<[178]>;
220 def F51 : FP< 51, "f51">, DwarfRegNum<[179]>;
221 def F52 : FP< 52, "f52">, DwarfRegNum<[180]>;
222 def F53 : FP< 53, "f53">, DwarfRegNum<[181]>;
223 def F54 : FP< 54, "f54">, DwarfRegNum<[182]>;
224 def F55 : FP< 55, "f55">, DwarfRegNum<[183]>;
225 def F56 : FP< 56, "f56">, DwarfRegNum<[184]>;
226 def F57 : FP< 57, "f57">, DwarfRegNum<[185]>;
227 def F58 : FP< 58, "f58">, DwarfRegNum<[186]>;
228 def F59 : FP< 59, "f59">, DwarfRegNum<[187]>;
229 def F60 : FP< 60, "f60">, DwarfRegNum<[188]>;
230 def F61 : FP< 61, "f61">, DwarfRegNum<[189]>;
231 def F62 : FP< 62, "f62">, DwarfRegNum<[190]>;
232 def F63 : FP< 63, "f63">, DwarfRegNum<[191]>;
233 def F64 : FP< 64, "f64">, DwarfRegNum<[192]>;
234 def F65 : FP< 65, "f65">, DwarfRegNum<[193]>;
235 def F66 : FP< 66, "f66">, DwarfRegNum<[194]>;
236 def F67 : FP< 67, "f67">, DwarfRegNum<[195]>;
237 def F68 : FP< 68, "f68">, DwarfRegNum<[196]>;
238 def F69 : FP< 69, "f69">, DwarfRegNum<[197]>;
239 def F70 : FP< 70, "f70">, DwarfRegNum<[198]>;
240 def F71 : FP< 71, "f71">, DwarfRegNum<[199]>;
241 def F72 : FP< 72, "f72">, DwarfRegNum<[200]>;
242 def F73 : FP< 73, "f73">, DwarfRegNum<[201]>;
243 def F74 : FP< 74, "f74">, DwarfRegNum<[202]>;
244 def F75 : FP< 75, "f75">, DwarfRegNum<[203]>;
245 def F76 : FP< 76, "f76">, DwarfRegNum<[204]>;
246 def F77 : FP< 77, "f77">, DwarfRegNum<[205]>;
247 def F78 : FP< 78, "f78">, DwarfRegNum<[206]>;
248 def F79 : FP< 79, "f79">, DwarfRegNum<[207]>;
249 def F80 : FP< 80, "f80">, DwarfRegNum<[208]>;
250 def F81 : FP< 81, "f81">, DwarfRegNum<[209]>;
251 def F82 : FP< 82, "f82">, DwarfRegNum<[210]>;
252 def F83 : FP< 83, "f83">, DwarfRegNum<[211]>;
253 def F84 : FP< 84, "f84">, DwarfRegNum<[212]>;
254 def F85 : FP< 85, "f85">, DwarfRegNum<[213]>;
255 def F86 : FP< 86, "f86">, DwarfRegNum<[214]>;
256 def F87 : FP< 87, "f87">, DwarfRegNum<[215]>;
257 def F88 : FP< 88, "f88">, DwarfRegNum<[216]>;
258 def F89 : FP< 89, "f89">, DwarfRegNum<[217]>;
259 def F90 : FP< 90, "f90">, DwarfRegNum<[218]>;
260 def F91 : FP< 91, "f91">, DwarfRegNum<[219]>;
261 def F92 : FP< 92, "f92">, DwarfRegNum<[220]>;
262 def F93 : FP< 93, "f93">, DwarfRegNum<[221]>;
263 def F94 : FP< 94, "f94">, DwarfRegNum<[222]>;
264 def F95 : FP< 95, "f95">, DwarfRegNum<[223]>;
265 def F96 : FP< 96, "f96">, DwarfRegNum<[224]>;
266 def F97 : FP< 97, "f97">, DwarfRegNum<[225]>;
267 def F98 : FP< 98, "f98">, DwarfRegNum<[226]>;
268 def F99 : FP< 99, "f99">, DwarfRegNum<[227]>;
269 def F100 : FP< 100, "f100">, DwarfRegNum<[228]>;
270 def F101 : FP< 101, "f101">, DwarfRegNum<[229]>;
271 def F102 : FP< 102, "f102">, DwarfRegNum<[230]>;
272 def F103 : FP< 103, "f103">, DwarfRegNum<[231]>;
273 def F104 : FP< 104, "f104">, DwarfRegNum<[232]>;
274 def F105 : FP< 105, "f105">, DwarfRegNum<[233]>;
275 def F106 : FP< 106, "f106">, DwarfRegNum<[234]>;
276 def F107 : FP< 107, "f107">, DwarfRegNum<[235]>;
277 def F108 : FP< 108, "f108">, DwarfRegNum<[236]>;
278 def F109 : FP< 109, "f109">, DwarfRegNum<[237]>;
279 def F110 : FP< 110, "f110">, DwarfRegNum<[238]>;
280 def F111 : FP< 111, "f111">, DwarfRegNum<[239]>;
281 def F112 : FP< 112, "f112">, DwarfRegNum<[240]>;
282 def F113 : FP< 113, "f113">, DwarfRegNum<[241]>;
283 def F114 : FP< 114, "f114">, DwarfRegNum<[242]>;
284 def F115 : FP< 115, "f115">, DwarfRegNum<[243]>;
285 def F116 : FP< 116, "f116">, DwarfRegNum<[244]>;
286 def F117 : FP< 117, "f117">, DwarfRegNum<[245]>;
287 def F118 : FP< 118, "f118">, DwarfRegNum<[246]>;
288 def F119 : FP< 119, "f119">, DwarfRegNum<[247]>;
289 def F120 : FP< 120, "f120">, DwarfRegNum<[248]>;
290 def F121 : FP< 121, "f121">, DwarfRegNum<[249]>;
291 def F122 : FP< 122, "f122">, DwarfRegNum<[250]>;
292 def F123 : FP< 123, "f123">, DwarfRegNum<[251]>;
293 def F124 : FP< 124, "f124">, DwarfRegNum<[252]>;
294 def F125 : FP< 125, "f125">, DwarfRegNum<[253]>;
295 def F126 : FP< 126, "f126">, DwarfRegNum<[254]>;
296 def F127 : FP< 127, "f127">, DwarfRegNum<[255]>;
297297
298298 /* predicate registers */
299 def p0 : PR< 0, "p0">, DwarfRegNum<256>;
300 def p1 : PR< 1, "p1">, DwarfRegNum<257>;
301 def p2 : PR< 2, "p2">, DwarfRegNum<258>;
302 def p3 : PR< 3, "p3">, DwarfRegNum<259>;
303 def p4 : PR< 4, "p4">, DwarfRegNum<260>;
304 def p5 : PR< 5, "p5">, DwarfRegNum<261>;
305 def p6 : PR< 6, "p6">, DwarfRegNum<262>;
306 def p7 : PR< 7, "p7">, DwarfRegNum<263>;
307 def p8 : PR< 8, "p8">, DwarfRegNum<264>;
308 def p9 : PR< 9, "p9">, DwarfRegNum<265>;
309 def p10 : PR< 10, "p10">, DwarfRegNum<266>;
310 def p11 : PR< 11, "p11">, DwarfRegNum<267>;
311 def p12 : PR< 12, "p12">, DwarfRegNum<268>;
312 def p13 : PR< 13, "p13">, DwarfRegNum<269>;
313 def p14 : PR< 14, "p14">, DwarfRegNum<270>;
314 def p15 : PR< 15, "p15">, DwarfRegNum<271>;
315 def p16 : PR< 16, "p16">, DwarfRegNum<272>;
316 def p17 : PR< 17, "p17">, DwarfRegNum<273>;
317 def p18 : PR< 18, "p18">, DwarfRegNum<274>;
318 def p19 : PR< 19, "p19">, DwarfRegNum<275>;
319 def p20 : PR< 20, "p20">, DwarfRegNum<276>;
320 def p21 : PR< 21, "p21">, DwarfRegNum<277>;
321 def p22 : PR< 22, "p22">, DwarfRegNum<278>;
322 def p23 : PR< 23, "p23">, DwarfRegNum<279>;
323 def p24 : PR< 24, "p24">, DwarfRegNum<280>;
324 def p25 : PR< 25, "p25">, DwarfRegNum<281>;
325 def p26 : PR< 26, "p26">, DwarfRegNum<282>;
326 def p27 : PR< 27, "p27">, DwarfRegNum<283>;
327 def p28 : PR< 28, "p28">, DwarfRegNum<284>;
328 def p29 : PR< 29, "p29">, DwarfRegNum<285>;
329 def p30 : PR< 30, "p30">, DwarfRegNum<286>;
330 def p31 : PR< 31, "p31">, DwarfRegNum<287>;
331 def p32 : PR< 32, "p32">, DwarfRegNum<288>;
332 def p33 : PR< 33, "p33">, DwarfRegNum<289>;
333 def p34 : PR< 34, "p34">, DwarfRegNum<290>;
334 def p35 : PR< 35, "p35">, DwarfRegNum<291>;
335 def p36 : PR< 36, "p36">, DwarfRegNum<292>;
336 def p37 : PR< 37, "p37">, DwarfRegNum<293>;
337 def p38 : PR< 38, "p38">, DwarfRegNum<294>;
338 def p39 : PR< 39, "p39">, DwarfRegNum<295>;
339 def p40 : PR< 40, "p40">, DwarfRegNum<296>;
340 def p41 : PR< 41, "p41">, DwarfRegNum<297>;
341 def p42 : PR< 42, "p42">, DwarfRegNum<298>;
342 def p43 : PR< 43, "p43">, DwarfRegNum<299>;
343 def p44 : PR< 44, "p44">, DwarfRegNum<300>;
344 def p45 : PR< 45, "p45">, DwarfRegNum<301>;
345 def p46 : PR< 46, "p46">, DwarfRegNum<302>;
346 def p47 : PR< 47, "p47">, DwarfRegNum<303>;
347 def p48 : PR< 48, "p48">, DwarfRegNum<304>;
348 def p49 : PR< 49, "p49">, DwarfRegNum<305>;
349 def p50 : PR< 50, "p50">, DwarfRegNum<306>;
350 def p51 : PR< 51, "p51">, DwarfRegNum<307>;
351 def p52 : PR< 52, "p52">, DwarfRegNum<308>;
352 def p53 : PR< 53, "p53">, DwarfRegNum<309>;
353 def p54 : PR< 54, "p54">, DwarfRegNum<310>;
354 def p55 : PR< 55, "p55">, DwarfRegNum<311>;
355 def p56 : PR< 56, "p56">, DwarfRegNum<312>;
356 def p57 : PR< 57, "p57">, DwarfRegNum<313>;
357 def p58 : PR< 58, "p58">, DwarfRegNum<314>;
358 def p59 : PR< 59, "p59">, DwarfRegNum<315>;
359 def p60 : PR< 60, "p60">, DwarfRegNum<316>;
360 def p61 : PR< 61, "p61">, DwarfRegNum<317>;
361 def p62 : PR< 62, "p62">, DwarfRegNum<318>;
362 def p63 : PR< 63, "p63">, DwarfRegNum<319>;
299 def p0 : PR< 0, "p0">, DwarfRegNum<[256]>;
300 def p1 : PR< 1, "p1">, DwarfRegNum<[257]>;
301 def p2 : PR< 2, "p2">, DwarfRegNum<[258]>;
302 def p3 : PR< 3, "p3">, DwarfRegNum<[259]>;
303 def p4 : PR< 4, "p4">, DwarfRegNum<[260]>;
304 def p5 : PR< 5, "p5">, DwarfRegNum<[261]>;
305 def p6 : PR< 6, "p6">, DwarfRegNum<[262]>;
306 def p7 : PR< 7, "p7">, DwarfRegNum<[263]>;
307 def p8 : PR< 8, "p8">, DwarfRegNum<[264]>;
308 def p9 : PR< 9, "p9">, DwarfRegNum<[265]>;
309 def p10 : PR< 10, "p10">, DwarfRegNum<[266]>;
310 def p11 : PR< 11, "p11">, DwarfRegNum<[267]>;
311 def p12 : PR< 12, "p12">, DwarfRegNum<[268]>;
312 def p13 : PR< 13, "p13">, DwarfRegNum<[269]>;
313 def p14 : PR< 14, "p14">, DwarfRegNum<[270]>;
314 def p15 : PR< 15, "p15">, DwarfRegNum<[271]>;
315 def p16 : PR< 16, "p16">, DwarfRegNum<[272]>;
316 def p17 : PR< 17, "p17">, DwarfRegNum<[273]>;
317 def p18 : PR< 18, "p18">, DwarfRegNum<[274]>;
318 def p19 : PR< 19, "p19">, DwarfRegNum<[275]>;
319 def p20 : PR< 20, "p20">, DwarfRegNum<[276]>;
320 def p21 : PR< 21, "p21">, DwarfRegNum<[277]>;
321 def p22 : PR< 22, "p22">, DwarfRegNum<[278]>;
322 def p23 : PR< 23, "p23">, DwarfRegNum<[279]>;
323 def p24 : PR< 24, "p24">, DwarfRegNum<[280]>;
324 def p25 : PR< 25, "p25">, DwarfRegNum<[281]>;
325 def p26 : PR< 26, "p26">, DwarfRegNum<[282]>;
326 def p27 : PR< 27, "p27">, DwarfRegNum<[283]>;
327 def p28 : PR< 28, "p28">, DwarfRegNum<[284]>;
328 def p29 : PR< 29, "p29">, DwarfRegNum<[285]>;
329 def p30 : PR< 30, "p30">, DwarfRegNum<[286]>;
330 def p31 : PR< 31, "p31">, DwarfRegNum<[287]>;
331 def p32 : PR< 32, "p32">, DwarfRegNum<[288]>;
332 def p33 : PR< 33, "p33">, DwarfRegNum<[289]>;
333 def p34 : PR< 34, "p34">, DwarfRegNum<[290]>;
334 def p35 : PR< 35, "p35">, DwarfRegNum<[291]>;
335 def p36 : PR< 36, "p36">, DwarfRegNum<[292]>;
336 def p37 : PR< 37, "p37">, DwarfRegNum<[293]>;
337 def p38 : PR< 38, "p38">, DwarfRegNum<[294]>;
338 def p39 : PR< 39, "p39">, DwarfRegNum<[295]>;
339 def p40 : PR< 40, "p40">, DwarfRegNum<[296]>;
340 def p41 : PR< 41, "p41">, DwarfRegNum<[297]>;
341 def p42 : PR< 42, "p42">, DwarfRegNum<[298]>;
342 def p43 : PR< 43, "p43">, DwarfRegNum<[299]>;
343 def p44 : PR< 44, "p44">, DwarfRegNum<[300]>;
344 def p45 : PR< 45, "p45">, DwarfRegNum<[301]>;
345 def p46 : PR< 46, "p46">, DwarfRegNum<[302]>;
346 def p47 : PR< 47, "p47">, DwarfRegNum<[303]>;
347 def p48 : PR< 48, "p48">, DwarfRegNum<[304]>;
348 def p49 : PR< 49, "p49">, DwarfRegNum<[305]>;
349 def p50 : PR< 50, "p50">, DwarfRegNum<[306]>;
350 def p51 : PR< 51, "p51">, DwarfRegNum<[307]>;
351 def p52 : PR< 52, "p52">, DwarfRegNum<[308]>;
352 def p53 : PR< 53, "p53">, DwarfRegNum<[309]>;
353 def p54 : PR< 54, "p54">, DwarfRegNum<[310]>;
354 def p55 : PR< 55, "p55">, DwarfRegNum<[311]>;
355 def p56 : PR< 56, "p56">, DwarfRegNum<[312]>;
356 def p57 : PR< 57, "p57">, DwarfRegNum<[313]>;
357 def p58 : PR< 58, "p58">, DwarfRegNum<[314]>;
358 def p59 : PR< 59, "p59">, DwarfRegNum<[315]>;
359 def p60 : PR< 60, "p60">, DwarfRegNum<[316]>;
360 def p61 : PR< 61, "p61">, DwarfRegNum<[317]>;
361 def p62 : PR< 62, "p62">, DwarfRegNum<[318]>;
362 def p63 : PR< 63, "p63">, DwarfRegNum<[319]>;
363363
364364 // XXX : this is temporary, we'll eventually have the output registers
365365 // in the general purpose register class too?
366 def out0 : GR<0, "out0">, DwarfRegNum<120>;
367 def out1 : GR<1, "out1">, DwarfRegNum<121>;
368 def out2 : GR<2, "out2">, DwarfRegNum<122>;
369 def out3 : GR<3, "out3">, DwarfRegNum<123>;
370 def out4 : GR<4, "out4">, DwarfRegNum<124>;
371 def out5 : GR<5, "out5">, DwarfRegNum<125>;
372 def out6 : GR<6, "out6">, DwarfRegNum<126>;
373 def out7 : GR<7, "out7">, DwarfRegNum<127>;
366 def out0 : GR<0, "out0">, DwarfRegNum<[120]>;
367 def out1 : GR<1, "out1">, DwarfRegNum<[121]>;
368 def out2 : GR<2, "out2">, DwarfRegNum<[122]>;
369 def out3 : GR<3, "out3">, DwarfRegNum<[123]>;
370 def out4 : GR<4, "out4">, DwarfRegNum<[124]>;
371 def out5 : GR<5, "out5">, DwarfRegNum<[125]>;
372 def out6 : GR<6, "out6">, DwarfRegNum<[126]>;
373 def out7 : GR<7, "out7">, DwarfRegNum<[127]>;
374374
375375 // application (special) registers:
376376
377377 // "previous function state" application register
378 def AR_PFS : GR<0, "ar.pfs">, DwarfRegNum<331>;
378 def AR_PFS : GR<0, "ar.pfs">, DwarfRegNum<[331]>;
379379
380380 // "return pointer" (this is really branch register b0)
381 def rp : GR<0, "rp">, DwarfRegNum<-1>;
381 def rp : GR<0, "rp">, DwarfRegNum<[-1]>;
382382
383383 // branch reg 6
384 def B6 : GR<0, "b6">, DwarfRegNum<326>;
384 def B6 : GR<0, "b6">, DwarfRegNum<[326]>;
385385
386386 //===----------------------------------------------------------------------===//
387387 // Register Class Definitions... now that we have all of the pieces, define the
537537 return 0;
538538 }
539539
540 int MipsRegisterInfo::
541 getDwarfRegNum(unsigned RegNum) const {
542 assert(0 && "What is the dwarf register number");
543 return -1;
544 }
545
540546 #include "MipsGenRegisterInfo.inc"
541547
9595 /// Exception handling queries.
9696 unsigned getEHExceptionRegister() const;
9797 unsigned getEHHandlerRegister() const;
98
99 int getDwarfRegNum(unsigned RegNum) const;
98100 };
99101
100102 } // end namespace llvm
2222 }
2323
2424 // CPU GPR Registers
25 def ZERO : MipsGPRReg< 0, "ZERO">, DwarfRegNum<0>;
26 def AT : MipsGPRReg< 1, "AT">, DwarfRegNum<1>;
27 def V0 : MipsGPRReg< 2, "2">, DwarfRegNum<2>;
28 def V1 : MipsGPRReg< 3, "3">, DwarfRegNum<3>;
29 def A0 : MipsGPRReg< 4, "4">, DwarfRegNum<5>;
30 def A1 : MipsGPRReg< 5, "5">, DwarfRegNum<5>;
31 def A2 : MipsGPRReg< 6, "6">, DwarfRegNum<6>;
32 def A3 : MipsGPRReg< 7, "7">, DwarfRegNum<7>;
33 def T0 : MipsGPRReg< 8, "8">, DwarfRegNum<8>;
34 def T1 : MipsGPRReg< 9, "9">, DwarfRegNum<9>;
35 def T2 : MipsGPRReg< 10, "10">, DwarfRegNum<10>;
36 def T3 : MipsGPRReg< 11, "11">, DwarfRegNum<11>;
37 def T4 : MipsGPRReg< 12, "12">, DwarfRegNum<12>;
38 def T5 : MipsGPRReg< 13, "13">, DwarfRegNum<13>;
39 def T6 : MipsGPRReg< 14, "14">, DwarfRegNum<14>;
40 def T7 : MipsGPRReg< 15, "15">, DwarfRegNum<15>;
41 def S0 : MipsGPRReg< 16, "16">, DwarfRegNum<16>;
42 def S1 : MipsGPRReg< 17, "17">, DwarfRegNum<17>;
43 def S2 : MipsGPRReg< 18, "18">, DwarfRegNum<18>;
44 def S3 : MipsGPRReg< 19, "19">, DwarfRegNum<19>;
45 def S4 : MipsGPRReg< 20, "20">, DwarfRegNum<20>;
46 def S5 : MipsGPRReg< 21, "21">, DwarfRegNum<21>;
47 def S6 : MipsGPRReg< 22, "22">, DwarfRegNum<22>;
48 def S7 : MipsGPRReg< 23, "23">, DwarfRegNum<23>;
49 def T8 : MipsGPRReg< 24, "24">, DwarfRegNum<24>;
50 def T9 : MipsGPRReg< 25, "25">, DwarfRegNum<25>;
51 def K0 : MipsGPRReg< 26, "26">, DwarfRegNum<26>;
52 def K1 : MipsGPRReg< 27, "27">, DwarfRegNum<27>;
53 def GP : MipsGPRReg< 28, "GP">, DwarfRegNum<28>;
54 def SP : MipsGPRReg< 29, "SP">, DwarfRegNum<29>;
55 def FP : MipsGPRReg< 30, "FP">, DwarfRegNum<30>;
56 def RA : MipsGPRReg< 31, "RA">, DwarfRegNum<31>;
25 def ZERO : MipsGPRReg< 0, "ZERO">, DwarfRegNum<[0]>;
26 def AT : MipsGPRReg< 1, "AT">, DwarfRegNum<[1]>;
27 def V0 : MipsGPRReg< 2, "2">, DwarfRegNum<[2]>;
28 def V1 : MipsGPRReg< 3, "3">, DwarfRegNum<[3]>;
29 def A0 : MipsGPRReg< 4, "4">, DwarfRegNum<[5]>;
30 def A1 : MipsGPRReg< 5, "5">, DwarfRegNum<[5]>;
31 def A2 : MipsGPRReg< 6, "6">, DwarfRegNum<[6]>;
32 def A3 : MipsGPRReg< 7, "7">, DwarfRegNum<[7]>;
33 def T0 : MipsGPRReg< 8, "8">, DwarfRegNum<[8]>;
34 def T1 : MipsGPRReg< 9, "9">, DwarfRegNum<[9]>;
35 def T2 : MipsGPRReg< 10, "10">, DwarfRegNum<[10]>;
36 def T3 : MipsGPRReg< 11, "11">, DwarfRegNum<[11]>;
37 def T4 : MipsGPRReg< 12, "12">, DwarfRegNum<[12]>;
38 def T5 : MipsGPRReg< 13, "13">, DwarfRegNum<[13]>;
39 def T6 : MipsGPRReg< 14, "14">, DwarfRegNum<[14]>;
40 def T7 : MipsGPRReg< 15, "15">, DwarfRegNum<[15]>;
41 def S0 : MipsGPRReg< 16, "16">, DwarfRegNum<[16]>;
42 def S1 : MipsGPRReg< 17, "17">, DwarfRegNum<[17]>;
43 def S2 : MipsGPRReg< 18, "18">, DwarfRegNum<[18]>;
44 def S3 : MipsGPRReg< 19, "19">, DwarfRegNum<[19]>;
45 def S4 : MipsGPRReg< 20, "20">, DwarfRegNum<[20]>;
46 def S5 : MipsGPRReg< 21, "21">, DwarfRegNum<[21]>;
47 def S6 : MipsGPRReg< 22, "22">, DwarfRegNum<[22]>;
48 def S7 : MipsGPRReg< 23, "23">, DwarfRegNum<[23]>;
49 def T8 : MipsGPRReg< 24, "24">, DwarfRegNum<[24]>;
50 def T9 : MipsGPRReg< 25, "25">, DwarfRegNum<[25]>;
51 def K0 : MipsGPRReg< 26, "26">, DwarfRegNum<[26]>;
52 def K1 : MipsGPRReg< 27, "27">, DwarfRegNum<[27]>;
53 def GP : MipsGPRReg< 28, "GP">, DwarfRegNum<[28]>;
54 def SP : MipsGPRReg< 29, "SP">, DwarfRegNum<[29]>;
55 def FP : MipsGPRReg< 30, "FP">, DwarfRegNum<[30]>;
56 def RA : MipsGPRReg< 31, "RA">, DwarfRegNum<[31]>;
5757
5858 // CPU Registers Class
5959 def CPURegs : RegisterClass<"Mips", [i32], 32,
12761276 return !Subtarget.isPPC64() ? PPC::R4 : PPC::X4;
12771277 }
12781278
1279 int PPCRegisterInfo::getDwarfRegNum(unsigned RegNum) const {
1280 assert(0 && "What is the dwarf register number");
1281 return -1;
1282 }
1283
12791284 #include "PPCGenRegisterInfo.inc"
12801285
115115 // Exception handling queries.
116116 unsigned getEHExceptionRegister() const;
117117 unsigned getEHHandlerRegister() const;
118
119 int getDwarfRegNum(unsigned RegNum) const;
118120 };
119121
120122 } // end namespace llvm
5353
5454
5555 // General-purpose registers
56 def R0 : GPR< 0, "r0">, DwarfRegNum<0>;
57 def R1 : GPR< 1, "r1">, DwarfRegNum<1>;
58 def R2 : GPR< 2, "r2">, DwarfRegNum<2>;
59 def R3 : GPR< 3, "r3">, DwarfRegNum<3>;
60 def R4 : GPR< 4, "r4">, DwarfRegNum<4>;
61 def R5 : GPR< 5, "r5">, DwarfRegNum<5>;
62 def R6 : GPR< 6, "r6">, DwarfRegNum<6>;
63 def R7 : GPR< 7, "r7">, DwarfRegNum<7>;
64 def R8 : GPR< 8, "r8">, DwarfRegNum<8>;
65 def R9 : GPR< 9, "r9">, DwarfRegNum<9>;
66 def R10 : GPR<10, "r10">, DwarfRegNum<10>;
67 def R11 : GPR<11, "r11">, DwarfRegNum<11>;
68 def R12 : GPR<12, "r12">, DwarfRegNum<12>;
69 def R13 : GPR<13, "r13">, DwarfRegNum<13>;
70 def R14 : GPR<14, "r14">, DwarfRegNum<14>;
71 def R15 : GPR<15, "r15">, DwarfRegNum<15>;
72 def R16 : GPR<16, "r16">, DwarfRegNum<16>;
73 def R17 : GPR<17, "r17">, DwarfRegNum<17>;
74 def R18 : GPR<18, "r18">, DwarfRegNum<18>;
75 def R19 : GPR<19, "r19">, DwarfRegNum<19>;
76 def R20 : GPR<20, "r20">, DwarfRegNum<20>;
77 def R21 : GPR<21, "r21">, DwarfRegNum<21>;
78 def R22 : GPR<22, "r22">, DwarfRegNum<22>;
79 def R23 : GPR<23, "r23">, DwarfRegNum<23>;
80 def R24 : GPR<24, "r24">, DwarfRegNum<24>;
81 def R25 : GPR<25, "r25">, DwarfRegNum<25>;
82 def R26 : GPR<26, "r26">, DwarfRegNum<26>;
83 def R27 : GPR<27, "r27">, DwarfRegNum<27>;
84 def R28 : GPR<28, "r28">, DwarfRegNum<28>;
85 def R29 : GPR<29, "r29">, DwarfRegNum<29>;
86 def R30 : GPR<30, "r30">, DwarfRegNum<30>;
87 def R31 : GPR<31, "r31">, DwarfRegNum<31>;
56 def R0 : GPR< 0, "r0">, DwarfRegNum<[0]>;
57 def R1 : GPR< 1, "r1">, DwarfRegNum<[1]>;
58 def R2 : GPR< 2, "r2">, DwarfRegNum<[2]>;
59 def R3 : GPR< 3, "r3">, DwarfRegNum<[3]>;
60 def R4 : GPR< 4, "r4">, DwarfRegNum<[4]>;
61 def R5 : GPR< 5, "r5">, DwarfRegNum<[5]>;
62 def R6 : GPR< 6, "r6">, DwarfRegNum<[6]>;
63 def R7 : GPR< 7, "r7">, DwarfRegNum<[7]>;
64 def R8 : GPR< 8, "r8">, DwarfRegNum<[8]>;
65 def R9 : GPR< 9, "r9">, DwarfRegNum<[9]>;
66 def R10 : GPR<10, "r10">, DwarfRegNum<[10]>;
67 def R11 : GPR<11, "r11">, DwarfRegNum<[11]>;
68 def R12 : GPR<12, "r12">, DwarfRegNum<[12]>;
69 def R13 : GPR<13, "r13">, DwarfRegNum<[13]>;
70 def R14 : GPR<14, "r14">, DwarfRegNum<[14]>;
71 def R15 : GPR<15, "r15">, DwarfRegNum<[15]>;
72 def R16 : GPR<16, "r16">, DwarfRegNum<[16]>;
73 def R17 : GPR<17, "r17">, DwarfRegNum<[17]>;
74 def R18 : GPR<18, "r18">, DwarfRegNum<[18]>;
75 def R19 : GPR<19, "r19">, DwarfRegNum<[19]>;
76 def R20 : GPR<20, "r20">, DwarfRegNum<[20]>;
77 def R21 : GPR<21, "r21">, DwarfRegNum<[21]>;
78 def R22 : GPR<22, "r22">, DwarfRegNum<[22]>;
79 def R23 : GPR<23, "r23">, DwarfRegNum<[23]>;
80 def R24 : GPR<24, "r24">, DwarfRegNum<[24]>;
81 def R25 : GPR<25, "r25">, DwarfRegNum<[25]>;
82 def R26 : GPR<26, "r26">, DwarfRegNum<[26]>;
83 def R27 : GPR<27, "r27">, DwarfRegNum<[27]>;
84 def R28 : GPR<28, "r28">, DwarfRegNum<[28]>;
85 def R29 : GPR<29, "r29">, DwarfRegNum<[29]>;
86 def R30 : GPR<30, "r30">, DwarfRegNum<[30]>;
87 def R31 : GPR<31, "r31">, DwarfRegNum<[31]>;
8888
8989 // 64-bit General-purpose registers
90 def X0 : GP8< R0>, DwarfRegNum<0>;
91 def X1 : GP8< R1>, DwarfRegNum<1>;
92 def X2 : GP8< R2>, DwarfRegNum<2>;
93 def X3 : GP8< R3>, DwarfRegNum<3>;
94 def X4 : GP8< R4>, DwarfRegNum<4>;
95 def X5 : GP8< R5>, DwarfRegNum<5>;
96 def X6 : GP8< R6>, DwarfRegNum<6>;
97 def X7 : GP8< R7>, DwarfRegNum<7>;
98 def X8 : GP8< R8>, DwarfRegNum<8>;
99 def X9 : GP8< R9>, DwarfRegNum<9>;
100 def X10 : GP8, DwarfRegNum<10>;
101 def X11 : GP8, DwarfRegNum<11>;
102 def X12 : GP8, DwarfRegNum<12>;
103 def X13 : GP8, DwarfRegNum<13>;
104 def X14 : GP8, DwarfRegNum<14>;
105 def X15 : GP8, DwarfRegNum<15>;
106 def X16 : GP8, DwarfRegNum<16>;
107 def X17 : GP8, DwarfRegNum<17>;
108 def X18 : GP8, DwarfRegNum<18>;
109 def X19 : GP8, DwarfRegNum<19>;
110 def X20 : GP8, DwarfRegNum<20>;
111 def X21 : GP8, DwarfRegNum<21>;
112 def X22 : GP8, DwarfRegNum<22>;
113 def X23 : GP8, DwarfRegNum<23>;
114 def X24 : GP8, DwarfRegNum<24>;
115 def X25 : GP8, DwarfRegNum<25>;
116 def X26 : GP8, DwarfRegNum<26>;
117 def X27 : GP8, DwarfRegNum<27>;
118 def X28 : GP8, DwarfRegNum<28>;
119 def X29 : GP8, DwarfRegNum<29>;
120 def X30 : GP8, DwarfRegNum<30>;
121 def X31 : GP8, DwarfRegNum<31>;
90 def X0 : GP8< R0>, DwarfRegNum<[0]>;
91 def X1 : GP8< R1>, DwarfRegNum<[1]>;
92 def X2 : GP8< R2>, DwarfRegNum<[2]>;
93 def X3 : GP8< R3>, DwarfRegNum<[3]>;
94 def X4 : GP8< R4>, DwarfRegNum<[4]>;
95 def X5 : GP8< R5>, DwarfRegNum<[5]>;
96 def X6 : GP8< R6>, DwarfRegNum<[6]>;
97 def X7 : GP8< R7>, DwarfRegNum<[7]>;
98 def X8 : GP8< R8>, DwarfRegNum<[8]>;
99 def X9 : GP8< R9>, DwarfRegNum<[9]>;
100 def X10 : GP8, DwarfRegNum<[10]>;
101 def X11 : GP8, DwarfRegNum<[11]>;
102 def X12 : GP8, DwarfRegNum<[12]>;
103 def X13 : GP8, DwarfRegNum<[13]>;
104 def X14 : GP8, DwarfRegNum<[14]>;
105 def X15 : GP8, DwarfRegNum<[15]>;
106 def X16 : GP8, DwarfRegNum<[16]>;
107 def X17 : GP8, DwarfRegNum<[17]>;
108 def X18 : GP8, DwarfRegNum<[18]>;
109 def X19 : GP8, DwarfRegNum<[19]>;
110 def X20 : GP8, DwarfRegNum<[20]>;
111 def X21 : GP8, DwarfRegNum<[21]>;
112 def X22 : GP8, DwarfRegNum<[22]>;
113 def X23 : GP8, DwarfRegNum<[23]>;
114 def X24 : GP8, DwarfRegNum<[24]>;
115 def X25 : GP8, DwarfRegNum<[25]>;
116 def X26 : GP8, DwarfRegNum<[26]>;
117 def X27 : GP8, DwarfRegNum<[27]>;
118 def X28 : GP8, DwarfRegNum<[28]>;
119 def X29 : GP8, DwarfRegNum<[29]>;
120 def X30 : GP8, DwarfRegNum<[30]>;
121 def X31 : GP8, DwarfRegNum<[31]>;
122122
123123 // Floating-point registers
124 def F0 : FPR< 0, "f0">, DwarfRegNum<32>;
125 def F1 : FPR< 1, "f1">, DwarfRegNum<33>;
126 def F2 : FPR< 2, "f2">, DwarfRegNum<34>;
127 def F3 : FPR< 3, "f3">, DwarfRegNum<35>;
128 def F4 : FPR< 4, "f4">, DwarfRegNum<36>;
129 def F5 : FPR< 5, "f5">, DwarfRegNum<37>;
130 def F6 : FPR< 6, "f6">, DwarfRegNum<38>;
131 def F7 : FPR< 7, "f7">, DwarfRegNum<39>;
132 def F8 : FPR< 8, "f8">, DwarfRegNum<40>;
133 def F9 : FPR< 9, "f9">, DwarfRegNum<41>;
134 def F10 : FPR<10, "f10">, DwarfRegNum<42>;
135 def F11 : FPR<11, "f11">, DwarfRegNum<43>;
136 def F12 : FPR<12, "f12">, DwarfRegNum<44>;
137 def F13 : FPR<13, "f13">, DwarfRegNum<45>;
138 def F14 : FPR<14, "f14">, DwarfRegNum<46>;
139 def F15 : FPR<15, "f15">, DwarfRegNum<47>;
140 def F16 : FPR<16, "f16">, DwarfRegNum<48>;
141 def F17 : FPR<17, "f17">, DwarfRegNum<49>;
142 def F18 : FPR<18, "f18">, DwarfRegNum<50>;
143 def F19 : FPR<19, "f19">, DwarfRegNum<51>;
144 def F20 : FPR<20, "f20">, DwarfRegNum<52>;
145 def F21 : FPR<21, "f21">, DwarfRegNum<53>;
146 def F22 : FPR<22, "f22">, DwarfRegNum<54>;
147 def F23 : FPR<23, "f23">, DwarfRegNum<55>;
148 def F24 : FPR<24, "f24">, DwarfRegNum<56>;
149 def F25 : FPR<25, "f25">, DwarfRegNum<57>;
150 def F26 : FPR<26, "f26">, DwarfRegNum<58>;
151 def F27 : FPR<27, "f27">, DwarfRegNum<59>;
152 def F28 : FPR<28, "f28">, DwarfRegNum<60>;
153 def F29 : FPR<29, "f29">, DwarfRegNum<61>;
154 def F30 : FPR<30, "f30">, DwarfRegNum<62>;
155 def F31 : FPR<31, "f31">, DwarfRegNum<63>;
124 def F0 : FPR< 0, "f0">, DwarfRegNum<[32]>;
125 def F1 : FPR< 1, "f1">, DwarfRegNum<[33]>;
126 def F2 : FPR< 2, "f2">, DwarfRegNum<[34]>;
127 def F3 : FPR< 3, "f3">, DwarfRegNum<[35]>;
128 def F4 : FPR< 4, "f4">, DwarfRegNum<[36]>;
129 def F5 : FPR< 5, "f5">, DwarfRegNum<[37]>;
130 def F6 : FPR< 6, "f6">, DwarfRegNum<[38]>;
131 def F7 : FPR< 7, "f7">, DwarfRegNum<[39]>;
132 def F8 : FPR< 8, "f8">, DwarfRegNum<[40]>;
133 def F9 : FPR< 9, "f9">, DwarfRegNum<[41]>;
134 def F10 : FPR<10, "f10">, DwarfRegNum<[42]>;
135 def F11 : FPR<11, "f11">, DwarfRegNum<[43]>;
136 def F12 : FPR<12, "f12">, DwarfRegNum<[44]>;
137 def F13 : FPR<13, "f13">, DwarfRegNum<[45]>;
138 def F14 : FPR<14, "f14">, DwarfRegNum<[46]>;
139 def F15 : FPR<15, "f15">, DwarfRegNum<[47]>;
140 def F16 : FPR<16, "f16">, DwarfRegNum<[48]>;
141 def F17 : FPR<17, "f17">, DwarfRegNum<[49]>;
142 def F18 : FPR<18, "f18">, DwarfRegNum<[50]>;
143 def F19 : FPR<19, "f19">, DwarfRegNum<[51]>;
144 def F20 : FPR<20, "f20">, DwarfRegNum<[52]>;
145 def F21 : FPR<21, "f21">, DwarfRegNum<[53]>;
146 def F22 : FPR<22, "f22">, DwarfRegNum<[54]>;
147 def F23 : FPR<23, "f23">, DwarfRegNum<[55]>;
148 def F24 : FPR<24, "f24">, DwarfRegNum<[56]>;
149 def F25 : FPR<25, "f25">, DwarfRegNum<[57]>;
150 def F26 : FPR<26, "f26">, DwarfRegNum<[58]>;
151 def F27 : FPR<27, "f27">, DwarfRegNum<[59]>;
152 def F28 : FPR<28, "f28">, DwarfRegNum<[60]>;
153 def F29 : FPR<29, "f29">, DwarfRegNum<[61]>;
154 def F30 : FPR<30, "f30">, DwarfRegNum<[62]>;
155 def F31 : FPR<31, "f31">, DwarfRegNum<[63]>;
156156
157157 // Vector registers
158 def V0 : VR< 0, "v0">, DwarfRegNum<77>;
159 def V1 : VR< 1, "v1">, DwarfRegNum<78>;
160 def V2 : VR< 2, "v2">, DwarfRegNum<79>;
161 def V3 : VR< 3, "v3">, DwarfRegNum<80>;
162 def V4 : VR< 4, "v4">, DwarfRegNum<81>;
163 def V5 : VR< 5, "v5">, DwarfRegNum<82>;
164 def V6 : VR< 6, "v6">, DwarfRegNum<83>;
165 def V7 : VR< 7, "v7">, DwarfRegNum<84>;
166 def V8 : VR< 8, "v8">, DwarfRegNum<85>;
167 def V9 : VR< 9, "v9">, DwarfRegNum<86>;
168 def V10 : VR<10, "v10">, DwarfRegNum<87>;
169 def V11 : VR<11, "v11">, DwarfRegNum<88>;
170 def V12 : VR<12, "v12">, DwarfRegNum<89>;
171 def V13 : VR<13, "v13">, DwarfRegNum<90>;
172 def V14 : VR<14, "v14">, DwarfRegNum<91>;
173 def V15 : VR<15, "v15">, DwarfRegNum<92>;
174 def V16 : VR<16, "v16">, DwarfRegNum<93>;
175 def V17 : VR<17, "v17">, DwarfRegNum<94>;
176 def V18 : VR<18, "v18">, DwarfRegNum<95>;
177 def V19 : VR<19, "v19">, DwarfRegNum<96>;
178 def V20 : VR<20, "v20">, DwarfRegNum<97>;
179 def V21 : VR<21, "v21">, DwarfRegNum<98>;
180 def V22 : VR<22, "v22">, DwarfRegNum<99>;
181 def V23 : VR<23, "v23">, DwarfRegNum<100>;
182 def V24 : VR<24, "v24">, DwarfRegNum<101>;
183 def V25 : VR<25, "v25">, DwarfRegNum<102>;
184 def V26 : VR<26, "v26">, DwarfRegNum<103>;
185 def V27 : VR<27, "v27">, DwarfRegNum<104>;
186 def V28 : VR<28, "v28">, DwarfRegNum<105>;
187 def V29 : VR<29, "v29">, DwarfRegNum<106>;
188 def V30 : VR<30, "v30">, DwarfRegNum<107>;
189 def V31 : VR<31, "v31">, DwarfRegNum<108>;
158 def V0 : VR< 0, "v0">, DwarfRegNum<[77]>;
159 def V1 : VR< 1, "v1">, DwarfRegNum<[78]>;
160 def V2 : VR< 2, "v2">, DwarfRegNum<[79]>;
161 def V3 : VR< 3, "v3">, DwarfRegNum<[80]>;
162 def V4 : VR< 4, "v4">, DwarfRegNum<[81]>;
163 def V5 : VR< 5, "v5">, DwarfRegNum<[82]>;
164 def V6 : VR< 6, "v6">, DwarfRegNum<[83]>;
165 def V7 : VR< 7, "v7">, DwarfRegNum<[84]>;
166 def V8 : VR< 8, "v8">, DwarfRegNum<[85]>;
167 def V9 : VR< 9, "v9">, DwarfRegNum<[86]>;
168 def V10 : VR<10, "v10">, DwarfRegNum<[87]>;
169 def V11 : VR<11, "v11">, DwarfRegNum<[88]>;
170 def V12 : VR<12, "v12">, DwarfRegNum<[89]>;
171 def V13 : VR<13, "v13">, DwarfRegNum<[90]>;
172 def V14 : VR<14, "v14">, DwarfRegNum<[91]>;
173 def V15 : VR<15, "v15">, DwarfRegNum<[92]>;
174 def V16 : VR<16, "v16">, DwarfRegNum<[93]>;
175 def V17 : VR<17, "v17">, DwarfRegNum<[94]>;
176 def V18 : VR<18, "v18">, DwarfRegNum<[95]>;
177 def V19 : VR<19, "v19">, DwarfRegNum<[96]>;
178 def V20 : VR<20, "v20">, DwarfRegNum<[97]>;
179 def V21 : VR<21, "v21">, DwarfRegNum<[98]>;
180 def V22 : VR<22, "v22">, DwarfRegNum<[99]>;
181 def V23 : VR<23, "v23">, DwarfRegNum<[100]>;
182 def V24 : VR<24, "v24">, DwarfRegNum<[101]>;
183 def V25 : VR<25, "v25">, DwarfRegNum<[102]>;
184 def V26 : VR<26, "v26">, DwarfRegNum<[103]>;
185 def V27 : VR<27, "v27">, DwarfRegNum<[104]>;
186 def V28 : VR<28, "v28">, DwarfRegNum<[105]>;
187 def V29 : VR<29, "v29">, DwarfRegNum<[106]>;
188 def V30 : VR<30, "v30">, DwarfRegNum<[107]>;
189 def V31 : VR<31, "v31">, DwarfRegNum<[108]>;
190190
191191 // Condition registers
192 def CR0 : CR<0, "cr0">, DwarfRegNum<68>;
193 def CR1 : CR<1, "cr1">, DwarfRegNum<69>;
194 def CR2 : CR<2, "cr2">, DwarfRegNum<70>;
195 def CR3 : CR<3, "cr3">, DwarfRegNum<71>;
196 def CR4 : CR<4, "cr4">, DwarfRegNum<72>;
197 def CR5 : CR<5, "cr5">, DwarfRegNum<73>;
198 def CR6 : CR<6, "cr6">, DwarfRegNum<74>;
199 def CR7 : CR<7, "cr7">, DwarfRegNum<75>;
192 def CR0 : CR<0, "cr0">, DwarfRegNum<[68]>;
193 def CR1 : CR<1, "cr1">, DwarfRegNum<[69]>;
194 def CR2 : CR<2, "cr2">, DwarfRegNum<[70]>;
195 def CR3 : CR<3, "cr3">, DwarfRegNum<[71]>;
196 def CR4 : CR<4, "cr4">, DwarfRegNum<[72]>;
197 def CR5 : CR<5, "cr5">, DwarfRegNum<[73]>;
198 def CR6 : CR<6, "cr6">, DwarfRegNum<[74]>;
199 def CR7 : CR<7, "cr7">, DwarfRegNum<[75]>;
200200
201201 // Condition register bits
202 def CR0LT : CRBIT< 0, "0">, DwarfRegNum<0>;
203 def CR0GT : CRBIT< 1, "1">, DwarfRegNum<0>;
204 def CR0EQ : CRBIT< 2, "2">, DwarfRegNum<0>;
205 def CR0UN : CRBIT< 3, "3">, DwarfRegNum<0>;
206 def CR1LT : CRBIT< 4, "4">, DwarfRegNum<0>;
207 def CR1GT : CRBIT< 5, "5">, DwarfRegNum<0>;
208 def CR1EQ : CRBIT< 6, "6">, DwarfRegNum<0>;
209 def CR1UN : CRBIT< 7, "7">, DwarfRegNum<0>;
210 def CR2LT : CRBIT< 8, "8">, DwarfRegNum<0>;
211 def CR2GT : CRBIT< 9, "9">, DwarfRegNum<0>;
212 def CR2EQ : CRBIT<10, "10">, DwarfRegNum<0>;
213 def CR2UN : CRBIT<11, "11">, DwarfRegNum<0>;
214 def CR3LT : CRBIT<12, "12">, DwarfRegNum<0>;
215 def CR3GT : CRBIT<13, "13">, DwarfRegNum<0>;
216 def CR3EQ : CRBIT<14, "14">, DwarfRegNum<0>;
217 def CR3UN : CRBIT<15, "15">, DwarfRegNum<0>;
218 def CR4LT : CRBIT<16, "16">, DwarfRegNum<0>;
219 def CR4GT : CRBIT<17, "17">, DwarfRegNum<0>;
220 def CR4EQ : CRBIT<18, "18">, DwarfRegNum<0>;
221 def CR4UN : CRBIT<19, "19">, DwarfRegNum<0>;
222 def CR5LT : CRBIT<20, "20">, DwarfRegNum<0>;
223 def CR5GT : CRBIT<21, "21">, DwarfRegNum<0>;
224 def CR5EQ : CRBIT<22, "22">, DwarfRegNum<0>;
225 def CR5UN : CRBIT<23, "23">, DwarfRegNum<0>;
226 def CR6LT : CRBIT<24, "24">, DwarfRegNum<0>;
227 def CR6GT : CRBIT<25, "25">, DwarfRegNum<0>;
228 def CR6EQ : CRBIT<26, "26">, DwarfRegNum<0>;
229 def CR6UN : CRBIT<27, "27">, DwarfRegNum<0>;
230 def CR7LT : CRBIT<28, "28">, DwarfRegNum<0>;
231 def CR7GT : CRBIT<29, "29">, DwarfRegNum<0>;
232 def CR7EQ : CRBIT<30, "30">, DwarfRegNum<0>;
233 def CR7UN : CRBIT<31, "31">, DwarfRegNum<0>;
202 def CR0LT : CRBIT< 0, "0">, DwarfRegNum<[0]>;
203 def CR0GT : CRBIT< 1, "1">, DwarfRegNum<[0]>;
204 def CR0EQ : CRBIT< 2, "2">, DwarfRegNum<[0]>;
205 def CR0UN : CRBIT< 3, "3">, DwarfRegNum<[0]>;
206 def CR1LT : CRBIT< 4, "4">, DwarfRegNum<[0]>;
207 def CR1GT : CRBIT< 5, "5">, DwarfRegNum<[0]>;
208 def CR1EQ : CRBIT< 6, "6">, DwarfRegNum<[0]>;
209 def CR1UN : CRBIT< 7, "7">, DwarfRegNum<[0]>;
210 def CR2LT : CRBIT< 8, "8">, DwarfRegNum<[0]>;
211 def CR2GT : CRBIT< 9, "9">, DwarfRegNum<[0]>;
212 def CR2EQ : CRBIT<10, "10">, DwarfRegNum<[0]>;
213 def CR2UN : CRBIT<11, "11">, DwarfRegNum<[0]>;
214 def CR3LT : CRBIT<12, "12">, DwarfRegNum<[0]>;
215 def CR3GT : CRBIT<13, "13">, DwarfRegNum<[0]>;
216 def CR3EQ : CRBIT<14, "14">, DwarfRegNum<[0]>;
217 def CR3UN : CRBIT<15, "15">, DwarfRegNum<[0]>;
218 def CR4LT : CRBIT<16, "16">, DwarfRegNum<[0]>;
219 def CR4GT : CRBIT<17, "17">, DwarfRegNum<[0]>;
220 def CR4EQ : CRBIT<18, "18">, DwarfRegNum<[0]>;
221 def CR4UN : CRBIT<19, "19">, DwarfRegNum<[0]>;
222 def CR5LT : CRBIT<20, "20">, DwarfRegNum<[0]>;
223 def CR5GT : CRBIT<21, "21">, DwarfRegNum<[0]>;
224 def CR5EQ : CRBIT<22, "22">, DwarfRegNum<[0]>;
225 def CR5UN : CRBIT<23, "23">, DwarfRegNum<[0]>;
226 def CR6LT : CRBIT<24, "24">, DwarfRegNum<[0]>;
227 def CR6GT : CRBIT<25, "25">, DwarfRegNum<[0]>;
228 def CR6EQ : CRBIT<26, "26">, DwarfRegNum<[0]>;
229 def CR6UN : CRBIT<27, "27">, DwarfRegNum<[0]>;
230 def CR7LT : CRBIT<28, "28">, DwarfRegNum<[0]>;
231 def CR7GT : CRBIT<29, "29">, DwarfRegNum<[0]>;
232 def CR7EQ : CRBIT<30, "30">, DwarfRegNum<[0]>;
233 def CR7UN : CRBIT<31, "31">, DwarfRegNum<[0]>;
234234
235235 def : SubRegSet<1, [CR0, CR1, CR2, CR3, CR4, CR5, CR6, CR7],
236236 [CR0LT, CR1LT, CR2LT, CR3LT, CR4LT, CR5LT, CR6LT, CR7LT]>;
242242 [CR0UN, CR1UN, CR2UN, CR3UN, CR4UN, CR5UN, CR6UN, CR7UN]>;
243243
244244 // Link register
245 def LR : SPR<8, "lr">, DwarfRegNum<65>;
245 def LR : SPR<8, "lr">, DwarfRegNum<[65]>;
246246 //let Aliases = [LR] in
247 def LR8 : SPR<8, "lr">, DwarfRegNum<65>;
247 def LR8 : SPR<8, "lr">, DwarfRegNum<[65]>;
248248
249249 // Count register
250 def CTR : SPR<9, "ctr">, DwarfRegNum<66>;
251 def CTR8 : SPR<9, "ctr">, DwarfRegNum<66>;
250 def CTR : SPR<9, "ctr">, DwarfRegNum<[66]>;
251 def CTR8 : SPR<9, "ctr">, DwarfRegNum<[66]>;
252252
253253 // VRsave register
254 def VRSAVE: SPR<256, "VRsave">, DwarfRegNum<107>;
254 def VRSAVE: SPR<256, "VRsave">, DwarfRegNum<[107]>;
255255
256256 /// Register classes
257257 // Allocate volatiles first
332332 return 0;
333333 }
334334
335 int SparcRegisterInfo::getDwarfRegNum(unsigned RegNum) const {
336 assert(0 && "What is the dwarf register number");
337 return -1;
338 }
339
335340 #include "SparcGenRegisterInfo.inc"
336341
9595 // Exception handling queries.
9696 unsigned getEHExceptionRegister() const;
9797 unsigned getEHHandlerRegister() const;
98
99 int getDwarfRegNum(unsigned RegNum) const;
98100 };
99101
100102 } // end namespace llvm
3131 }
3232
3333 // Integer registers
34 def G0 : Ri< 0, "G0">, DwarfRegNum<0>;
35 def G1 : Ri< 1, "G1">, DwarfRegNum<1>;
36 def G2 : Ri< 2, "G2">, DwarfRegNum<2>;
37 def G3 : Ri< 3, "G3">, DwarfRegNum<3>;
38 def G4 : Ri< 4, "G4">, DwarfRegNum<4>;
39 def G5 : Ri< 5, "G5">, DwarfRegNum<5>;
40 def G6 : Ri< 6, "G6">, DwarfRegNum<6>;
41 def G7 : Ri< 7, "G7">, DwarfRegNum<7>;
42 def O0 : Ri< 8, "O0">, DwarfRegNum<8>;
43 def O1 : Ri< 9, "O1">, DwarfRegNum<9>;
44 def O2 : Ri<10, "O2">, DwarfRegNum<10>;
45 def O3 : Ri<11, "O3">, DwarfRegNum<11>;
46 def O4 : Ri<12, "O4">, DwarfRegNum<12>;
47 def O5 : Ri<13, "O5">, DwarfRegNum<13>;
48 def O6 : Ri<14, "O6">, DwarfRegNum<14>;
49 def O7 : Ri<15, "O7">, DwarfRegNum<15>;
50 def L0 : Ri<16, "L0">, DwarfRegNum<16>;
51 def L1 : Ri<17, "L1">, DwarfRegNum<17>;
52 def L2 : Ri<18, "L2">, DwarfRegNum<18>;
53 def L3 : Ri<19, "L3">, DwarfRegNum<19>;
54 def L4 : Ri<20, "L4">, DwarfRegNum<20>;
55 def L5 : Ri<21, "L5">, DwarfRegNum<21>;
56 def L6 : Ri<22, "L6">, DwarfRegNum<22>;
57 def L7 : Ri<23, "L7">, DwarfRegNum<23>;
58 def I0 : Ri<24, "I0">, DwarfRegNum<24>;
59 def I1 : Ri<25, "I1">, DwarfRegNum<25>;
60 def I2 : Ri<26, "I2">, DwarfRegNum<26>;
61 def I3 : Ri<27, "I3">, DwarfRegNum<27>;
62 def I4 : Ri<28, "I4">, DwarfRegNum<28>;
63 def I5 : Ri<29, "I5">, DwarfRegNum<29>;
64 def I6 : Ri<30, "I6">, DwarfRegNum<30>;
65 def I7 : Ri<31, "I7">, DwarfRegNum<31>;
34 def G0 : Ri< 0, "G0">, DwarfRegNum<[0]>;
35 def G1 : Ri< 1, "G1">, DwarfRegNum<[1]>;
36 def G2 : Ri< 2, "G2">, DwarfRegNum<[2]>;
37 def G3 : Ri< 3, "G3">, DwarfRegNum<[3]>;
38 def G4 : Ri< 4, "G4">, DwarfRegNum<[4]>;
39 def G5 : Ri< 5, "G5">, DwarfRegNum<[5]>;
40 def G6 : Ri< 6, "G6">, DwarfRegNum<[6]>;
41 def G7 : Ri< 7, "G7">, DwarfRegNum<[7]>;
42 def O0 : Ri< 8, "O0">, DwarfRegNum<[8]>;
43 def O1 : Ri< 9, "O1">, DwarfRegNum<[9]>;
44 def O2 : Ri<10, "O2">, DwarfRegNum<[10]>;
45 def O3 : Ri<11, "O3">, DwarfRegNum<[11]>;
46 def O4 : Ri<12, "O4">, DwarfRegNum<[12]>;
47 def O5 : Ri<13, "O5">, DwarfRegNum<[13]>;
48 def O6 : Ri<14, "O6">, DwarfRegNum<[14]>;
49 def O7 : Ri<15, "O7">, DwarfRegNum<[15]>;
50 def L0 : Ri<16, "L0">, DwarfRegNum<[16]>;
51 def L1 : Ri<17, "L1">, DwarfRegNum<[17]>;
52 def L2 : Ri<18, "L2">, DwarfRegNum<[18]>;
53 def L3 : Ri<19, "L3">, DwarfRegNum<[19]>;
54 def L4 : Ri<20, "L4">, DwarfRegNum<[20]>;
55 def L5 : Ri<21, "L5">, DwarfRegNum<[21]>;
56 def L6 : Ri<22, "L6">, DwarfRegNum<[22]>;
57 def L7 : Ri<23, "L7">, DwarfRegNum<[23]>;
58 def I0 : Ri<24, "I0">, DwarfRegNum<[24]>;
59 def I1 : Ri<25, "I1">, DwarfRegNum<[25]>;
60 def I2 : Ri<26, "I2">, DwarfRegNum<[26]>;
61 def I3 : Ri<27, "I3">, DwarfRegNum<[27]>;
62 def I4 : Ri<28, "I4">, DwarfRegNum<[28]>;
63 def I5 : Ri<29, "I5">, DwarfRegNum<[29]>;
64 def I6 : Ri<30, "I6">, DwarfRegNum<[30]>;
65 def I7 : Ri<31, "I7">, DwarfRegNum<[31]>;
6666
6767 // Floating-point registers
68 def F0 : Rf< 0, "F0">, DwarfRegNum<32>;
69 def F1 : Rf< 1, "F1">, DwarfRegNum<33>;
70 def F2 : Rf< 2, "F2">, DwarfRegNum<34>;
71 def F3 : Rf< 3, "F3">, DwarfRegNum<35>;
72 def F4 : Rf< 4, "F4">, DwarfRegNum<36>;
73 def F5 : Rf< 5, "F5">, DwarfRegNum<37>;
74 def F6 : Rf< 6, "F6">, DwarfRegNum<38>;
75 def F7 : Rf< 7, "F7">, DwarfRegNum<39>;
76 def F8 : Rf< 8, "F8">, DwarfRegNum<40>;
77 def F9 : Rf< 9, "F9">, DwarfRegNum<41>;
78 def F10 : Rf<10, "F10">, DwarfRegNum<42>;
79 def F11 : Rf<11, "F11">, DwarfRegNum<43>;
80 def F12 : Rf<12, "F12">, DwarfRegNum<44>;
81 def F13 : Rf<13, "F13">, DwarfRegNum<45>;
82 def F14 : Rf<14, "F14">, DwarfRegNum<46>;
83 def F15 : Rf<15, "F15">, DwarfRegNum<47>;
84 def F16 : Rf<16, "F16">, DwarfRegNum<48>;
85 def F17 : Rf<17, "F17">, DwarfRegNum<49>;
86 def F18 : Rf<18, "F18">, DwarfRegNum<50>;
87 def F19 : Rf<19, "F19">, DwarfRegNum<51>;
88 def F20 : Rf<20, "F20">, DwarfRegNum<52>;
89 def F21 : Rf<21, "F21">, DwarfRegNum<53>;
90 def F22 : Rf<22, "F22">, DwarfRegNum<54>;
91 def F23 : Rf<23, "F23">, DwarfRegNum<55>;
92 def F24 : Rf<24, "F24">, DwarfRegNum<56>;
93 def F25 : Rf<25, "F25">, DwarfRegNum<57>;
94 def F26 : Rf<26, "F26">, DwarfRegNum<58>;
95 def F27 : Rf<27, "F27">, DwarfRegNum<59>;
96 def F28 : Rf<28, "F28">, DwarfRegNum<60>;
97 def F29 : Rf<29, "F29">, DwarfRegNum<61>;
98 def F30 : Rf<30, "F30">, DwarfRegNum<62>;
99 def F31 : Rf<31, "F31">, DwarfRegNum<63>;
68 def F0 : Rf< 0, "F0">, DwarfRegNum<[32]>;
69 def F1 : Rf< 1, "F1">, DwarfRegNum<[33]>;
70 def F2 : Rf< 2, "F2">, DwarfRegNum<[34]>;
71 def F3 : Rf< 3, "F3">, DwarfRegNum<[35]>;
72 def F4 : Rf< 4, "F4">, DwarfRegNum<[36]>;
73 def F5 : Rf< 5, "F5">, DwarfRegNum<[37]>;
74 def F6 : Rf< 6, "F6">, DwarfRegNum<[38]>;
75 def F7 : Rf< 7, "F7">, DwarfRegNum<[39]>;
76 def F8 : Rf< 8, "F8">, DwarfRegNum<[40]>;
77 def F9 : Rf< 9, "F9">, DwarfRegNum<[41]>;
78 def F10 : Rf<10, "F10">, DwarfRegNum<[42]>;
79 def F11 : Rf<11, "F11">, DwarfRegNum<[43]>;
80 def F12 : Rf<12, "F12">, DwarfRegNum<[44]>;
81 def F13 : Rf<13, "F13">, DwarfRegNum<[45]>;
82 def F14 : Rf<14, "F14">, DwarfRegNum<[46]>;
83 def F15 : Rf<15, "F15">, DwarfRegNum<[47]>;
84 def F16 : Rf<16, "F16">, DwarfRegNum<[48]>;
85 def F17 : Rf<17, "F17">, DwarfRegNum<[49]>;
86 def F18 : Rf<18, "F18">, DwarfRegNum<[50]>;
87 def F19 : Rf<19, "F19">, DwarfRegNum<[51]>;
88 def F20 : Rf<20, "F20">, DwarfRegNum<[52]>;
89 def F21 : Rf<21, "F21">, DwarfRegNum<[53]>;
90 def F22 : Rf<22, "F22">, DwarfRegNum<[54]>;
91 def F23 : Rf<23, "F23">, DwarfRegNum<[55]>;
92 def F24 : Rf<24, "F24">, DwarfRegNum<[56]>;
93 def F25 : Rf<25, "F25">, DwarfRegNum<[57]>;
94 def F26 : Rf<26, "F26">, DwarfRegNum<[58]>;
95 def F27 : Rf<27, "F27">, DwarfRegNum<[59]>;
96 def F28 : Rf<28, "F28">, DwarfRegNum<[60]>;
97 def F29 : Rf<29, "F29">, DwarfRegNum<[61]>;
98 def F30 : Rf<30, "F30">, DwarfRegNum<[62]>;
99 def F31 : Rf<31, "F31">, DwarfRegNum<[63]>;
100100
101101 // Aliases of the F* registers used to hold 64-bit fp values (doubles)
102 def D0 : Rd< 0, "F0", [F0, F1]>, DwarfRegNum<32>;
103 def D1 : Rd< 2, "F2", [F2, F3]>, DwarfRegNum<34>;
104 def D2 : Rd< 4, "F4", [F4, F5]>, DwarfRegNum<36>;
105 def D3 : Rd< 6, "F6", [F6, F7]>, DwarfRegNum<38>;
106 def D4 : Rd< 8, "F8", [F8, F9]>, DwarfRegNum<40>;
107 def D5 : Rd<10, "F10", [F10, F11]>, DwarfRegNum<42>;
108 def D6 : Rd<12, "F12", [F12, F13]>, DwarfRegNum<44>;
109 def D7 : Rd<14, "F14", [F14, F15]>, DwarfRegNum<46>;
110 def D8 : Rd<16, "F16", [F16, F17]>, DwarfRegNum<48>;
111 def D9 : Rd<18, "F18", [F18, F19]>, DwarfRegNum<50>;
112 def D10 : Rd<20, "F20", [F20, F21]>, DwarfRegNum<52>;
113 def D11 : Rd<22, "F22", [F22, F23]>, DwarfRegNum<54>;
114 def D12 : Rd<24, "F24", [F24, F25]>, DwarfRegNum<56>;
115 def D13 : Rd<26, "F26", [F26, F27]>, DwarfRegNum<58>;
116 def D14 : Rd<28, "F28", [F28, F29]>, DwarfRegNum<60>;
117 def D15 : Rd<30, "F30", [F30, F31]>, DwarfRegNum<62>;
102 def D0 : Rd< 0, "F0", [F0, F1]>, DwarfRegNum<[32]>;
103 def D1 : Rd< 2, "F2", [F2, F3]>, DwarfRegNum<[34]>;
104 def D2 : Rd< 4, "F4", [F4, F5]>, DwarfRegNum<[36]>;
105 def D3 : Rd< 6, "F6", [F6, F7]>, DwarfRegNum<[38]>;
106 def D4 : Rd< 8, "F8", [F8, F9]>, DwarfRegNum<[40]>;
107 def D5 : Rd<10, "F10", [F10, F11]>, DwarfRegNum<[42]>;
108 def D6 : Rd<12, "F12", [F12, F13]>, DwarfRegNum<[44]>;
109 def D7 : Rd<14, "F14", [F14, F15]>, DwarfRegNum<[46]>;
110 def D8 : Rd<16, "F16", [F16, F17]>, DwarfRegNum<[48]>;
111 def D9 : Rd<18, "F18", [F18, F19]>, DwarfRegNum<[50]>;
112 def D10 : Rd<20, "F20", [F20, F21]>, DwarfRegNum<[52]>;
113 def D11 : Rd<22, "F22", [F22, F23]>, DwarfRegNum<[54]>;
114 def D12 : Rd<24, "F24", [F24, F25]>, DwarfRegNum<[56]>;
115 def D13 : Rd<26, "F26", [F26, F27]>, DwarfRegNum<[58]>;
116 def D14 : Rd<28, "F28", [F28, F29]>, DwarfRegNum<[60]>;
117 def D15 : Rd<30, "F30", [F30, F31]>, DwarfRegNum<[62]>;
118118
119119 // Register classes.
120120 //
4848 // not [AX, AH, AL].
4949 list SubRegs = [];
5050
51 // DwarfNumber - Number used internally by gcc/gdb to identify the register.
51 // DwarfNumbers - Numbers used internally by gcc/gdb to identify the register.
5252 // These values can be determined by locating the .h file in the
5353 // directory llvmgcc/gcc/config// and looking for REGISTER_NAMES. The
5454 // order of these names correspond to the enumeration used by gcc. A value of
5555 // -1 indicates that the gcc number is undefined.
56 int DwarfNumber = -1;
56 list DwarfNumbers = [];
5757 }
5858
5959 // RegisterWithSubRegs - This can be used to define instances of Register which
132132 // to the register numbering used by gcc and gdb. These values are used by a
133133 // debug information writer (ex. DwarfWriter) to describe where values may be
134134 // located during execution.
135 class DwarfRegNum {
136 // DwarfNumber - Number used internally by gcc/gdb to identify the register.
135 class DwarfRegNum Numbers> {
136 // DwarfNumbers - Numbers used internally by gcc/gdb to identify the register.
137137 // These values can be determined by locating the .h file in the
138138 // directory llvmgcc/gcc/config// and looking for REGISTER_NAMES. The
139139 // order of these names correspond to the enumeration used by gcc. A value of
140140 // -1 indicates that the gcc number is undefined.
141 int DwarfNumber = N;
141 list DwarfNumbers = Numbers;
142142 }
143143
144144 //===----------------------------------------------------------------------===//
655655
656656 // getDwarfRegNum - This function maps LLVM register identifiers to the
657657 // Dwarf specific numbering, used in debug info and exception tables.
658 // The registers are given "basic" dwarf numbers in the .td files,
659 // which are for the 64-bit target. These are collected by TableGen
660 // into X86GenRegisterInfo::getDwarfRegNum and overridden here for
661 // other targets.
662 // FIXME: Comments in gcc indicate that Darwin uses different numbering
663 // for debug info and exception handling info:( The numbering here is
664 // for exception handling.
665658
666659 int X86RegisterInfo::getDwarfRegNum(unsigned RegNo) const {
667 int n = X86GenRegisterInfo::getDwarfRegNum(RegNo);
668660 const X86Subtarget *Subtarget = &TM.getSubtarget();
661 unsigned Flavour = DWARFFlavour::X86_64;
669662 if (!Subtarget->is64Bit()) {
670 // Numbers are all different for 32-bit. Further, some of them
671 // differ between Darwin and other targets.
672 switch (n) {
673 default: assert(0 && "Invalid argument to getDwarfRegNum");
674 return n;
675 case 0: return 0; // ax
676 case 1: return 2; // dx
677 case 2: return 1; // cx
678 case 3: return 3; // bx
679 case 4: return 6; // si
680 case 5: return 7; // di
681 case 6: return (Subtarget->isDarwin) ? 4 : 5; // bp
682 case 7: return (Subtarget->isDarwin) ? 5 : 4; // sp
683
684 case 8: case 9: case 10: case 11: // r8..r15
685 case 12: case 13: case 14: case 15:
686 assert(0 && "Invalid register in 32-bit mode");
687 return n;
688
689 case 16: return 8; // ip
690
691 case 17: case 18: case 19: case 20: // xmm0..xmm7
692 case 21: case 22: case 23: case 24:
693 return n+4;
694
695 case 25: case 26: case 27: case 28: // xmm8..xmm15
696 case 29: case 30: case 31: case 32:
697 assert(0 && "Invalid register in 32-bit mode");
698 return n;
699
700 case 33: case 34: case 35: case 36: // st0..st7
701 case 37: case 38: case 39: case 40:
702 return (Subtarget->isDarwin) ? n-21 : n-22;
703
704 case 41: case 42: case 43: case 44: // mm0..mm7
705 case 45: case 46: case 47: case 48:
706 return n-12;
663 if (Subtarget->isTargetDarwin()) {
664 Flavour = DWARFFlavour::X86_32_Darwin;
665 } else if (Subtarget->isTargetCygMing()) {
666 // Unsupported by now, just quick fallback
667 Flavour = DWARFFlavour::X86_32_ELF;
668 } else {
669 Flavour = DWARFFlavour::X86_32_ELF;
707670 }
708671 }
709 return n;
672
673 return X86GenRegisterInfo::getDwarfRegNumFull(RegNo, Flavour);
710674 }
711675
712676 // getX86RegNum - This function maps LLVM register identifiers to their X86
3131 };
3232 }
3333
34 /// DWARFFlavour - Flavour of dwarf regnumbers
35 ///
36 namespace DWARFFlavour {
37 enum {
38 X86_64 = 0, X86_32_Darwin = 1, X86_32_ELF = 2
39 };
40 }
41
3442 class X86RegisterInfo : public X86GenRegisterInfo {
3543 public:
3644 X86TargetMachine &TM;
2222 // because the register file generator is smart enough to figure out that
2323 // AL aliases AX if we tell it that AX aliased AL (for example).
2424
25 // Dwarf numbering is different for 32-bit and 64-bit, and there are
26 // variations by target as well. The numbers here are for 64-bit.
27 // They are altered by X86RegisterInfo::getDwarfRegNum at runtime. Note
28 // that we can't assign the same number here to different registers, as
29 // getDwarfRegNum has only the number here to work with.
25 // Dwarf numbering is different for 32-bit and 64-bit, and there are
26 // variations by target as well. Currently the first entry is for X86-64,
27 // second - for X86-32/Darwin and third for X86-32/Linux
28
29 // FIXME: Comments in gcc indicate that Darwin uses different numbering
30 // for debug info and exception handling info:( The numbering here is
31 // for exception handling.
3032
3133 // 8-bit registers
3234 // Low registers
33 def AL : Register<"AL">, DwarfRegNum<0>;
34 def DL : Register<"DL">, DwarfRegNum<1>;
35 def CL : Register<"CL">, DwarfRegNum<2>;
36 def BL : Register<"BL">, DwarfRegNum<3>;
35 def AL : Register<"AL">, DwarfRegNum<[0, 0, 0]>;
36 def DL : Register<"DL">, DwarfRegNum<[1, 2, 2]>;
37 def CL : Register<"CL">, DwarfRegNum<[2, 1, 1]>;
38 def BL : Register<"BL">, DwarfRegNum<[3, 3, 3]>;
3739
3840 // X86-64 only
39 def SIL : Register<"SIL">, DwarfRegNum<4>;
40 def DIL : Register<"DIL">, DwarfRegNum<5>;
41 def BPL : Register<"BPL">, DwarfRegNum<6>;
42 def SPL : Register<"SPL">, DwarfRegNum<7>;
43 def R8B : Register<"R8B">, DwarfRegNum<8>;
44 def R9B : Register<"R9B">, DwarfRegNum<9>;
45 def R10B : Register<"R10B">, DwarfRegNum<10>;
46 def R11B : Register<"R11B">, DwarfRegNum<11>;
47 def R12B : Register<"R12B">, DwarfRegNum<12>;
48 def R13B : Register<"R13B">, DwarfRegNum<13>;
49 def R14B : Register<"R14B">, DwarfRegNum<14>;
50 def R15B : Register<"R15B">, DwarfRegNum<15>;
41 def SIL : Register<"SIL">, DwarfRegNum<[4, 6, 6]>;
42 def DIL : Register<"DIL">, DwarfRegNum<[5, 7, 7]>;
43 def BPL : Register<"BPL">, DwarfRegNum<[6, 4, 5]>;
44 def SPL : Register<"SPL">, DwarfRegNum<[7, 5, 4]>;
45 def R8B : Register<"R8B">, DwarfRegNum<[8, -2, -2]>;
46 def R9B : Register<"R9B">, DwarfRegNum<[9, -2, -2]>;
47 def R10B : Register<"R10B">, DwarfRegNum<[10, -2, -2]>;
48 def R11B : Register<"R11B">, DwarfRegNum<[11, -2, -2]>;
49 def R12B : Register<"R12B">, DwarfRegNum<[12, -2, -2]>;
50 def R13B : Register<"R13B">, DwarfRegNum<[13, -2, -2]>;
51 def R14B : Register<"R14B">, DwarfRegNum<[14, -2, -2]>;
52 def R15B : Register<"R15B">, DwarfRegNum<[15, -2, -2]>;
5153
5254 // High registers X86-32 only
53 def AH : Register<"AH">, DwarfRegNum<0>;
54 def DH : Register<"DH">, DwarfRegNum<1>;
55 def CH : Register<"CH">, DwarfRegNum<2>;
56 def BH : Register<"BH">, DwarfRegNum<3>;
55 def AH : Register<"AH">, DwarfRegNum<[0, 0, 0]>;
56 def DH : Register<"DH">, DwarfRegNum<[1, 2, 2]>;
57 def CH : Register<"CH">, DwarfRegNum<[2, 1, 1]>;
58 def BH : Register<"BH">, DwarfRegNum<[3, 3, 3]>;
5759
5860 // 16-bit registers
59 def AX : RegisterWithSubRegs<"AX", [AH,AL]>, DwarfRegNum<0>;
60 def DX : RegisterWithSubRegs<"DX", [DH,DL]>, DwarfRegNum<1>;
61 def CX : RegisterWithSubRegs<"CX", [CH,CL]>, DwarfRegNum<2>;
62 def BX : RegisterWithSubRegs<"BX", [BH,BL]>, DwarfRegNum<3>;
63 def SI : RegisterWithSubRegs<"SI", [SIL]>, DwarfRegNum<4>;
64 def DI : RegisterWithSubRegs<"DI", [DIL]>, DwarfRegNum<5>;
65 def BP : RegisterWithSubRegs<"BP", [BPL]>, DwarfRegNum<6>;
66 def SP : RegisterWithSubRegs<"SP", [SPL]>, DwarfRegNum<7>;
67 def IP : Register<"IP">, DwarfRegNum<16>;
61 def AX : RegisterWithSubRegs<"AX", [AH,AL]>, DwarfRegNum<[0, 0, 0]>;
62 def DX : RegisterWithSubRegs<"DX", [DH,DL]>, DwarfRegNum<[1, 2, 2]>;
63 def CX : RegisterWithSubRegs<"CX", [CH,CL]>, DwarfRegNum<[2, 1, 1]>;
64 def BX : RegisterWithSubRegs<"BX", [BH,BL]>, DwarfRegNum<[3, 3, 3]>;
65 def SI : RegisterWithSubRegs<"SI", [SIL]>, DwarfRegNum<[4, 6, 6]>;
66 def DI : RegisterWithSubRegs<"DI", [DIL]>, DwarfRegNum<[5, 7, 7]>;
67 def BP : RegisterWithSubRegs<"BP", [BPL]>, DwarfRegNum<[6, 4, 5]>;
68 def SP : RegisterWithSubRegs<"SP", [SPL]>, DwarfRegNum<[7, 5, 4]>;
69 def IP : Register<"IP">, DwarfRegNum<[16]>;
6870
6971 // X86-64 only
70 def R8W : RegisterWithSubRegs<"R8W", [R8B]>, DwarfRegNum<8>;
71 def R9W : RegisterWithSubRegs<"R9W", [R9B]>, DwarfRegNum<9>;
72 def R10W : RegisterWithSubRegs<"R10W", [R10B]>, DwarfRegNum<10>;
73 def R11W : RegisterWithSubRegs<"R11W", [R11B]>, DwarfRegNum<11>;
74 def R12W : RegisterWithSubRegs<"R12W", [R12B]>, DwarfRegNum<12>;
75 def R13W : RegisterWithSubRegs<"R13W", [R13B]>, DwarfRegNum<13>;
76 def R14W : RegisterWithSubRegs<"R14W", [R14B]>, DwarfRegNum<14>;
77 def R15W : RegisterWithSubRegs<"R15W", [R15B]>, DwarfRegNum<15>;
72 def R8W : RegisterWithSubRegs<"R8W", [R8B]>, DwarfRegNum<[8, -2, -2]>;
73 def R9W : RegisterWithSubRegs<"R9W", [R9B]>, DwarfRegNum<[9, -2, -2]>;
74 def R10W : RegisterWithSubRegs<"R10W", [R10B]>, DwarfRegNum<[10, -2, -2]>;
75 def R11W : RegisterWithSubRegs<"R11W", [R11B]>, DwarfRegNum<[11, -2, -2]>;
76 def R12W : RegisterWithSubRegs<"R12W", [R12B]>, DwarfRegNum<[12, -2, -2]>;
77 def R13W : RegisterWithSubRegs<"R13W", [R13B]>, DwarfRegNum<[13, -2, -2]>;
78 def R14W : RegisterWithSubRegs<"R14W", [R14B]>, DwarfRegNum<[14, -2, -2]>;
79 def R15W : RegisterWithSubRegs<"R15W", [R15B]>, DwarfRegNum<[15, -2, -2]>;
7880
7981 // 32-bit registers
80 def EAX : RegisterWithSubRegs<"EAX", [AX]>, DwarfRegNum<0>;
81 def EDX : RegisterWithSubRegs<"EDX", [DX]>, DwarfRegNum<1>;
82 def ECX : RegisterWithSubRegs<"ECX", [CX]>, DwarfRegNum<2>;
83 def EBX : RegisterWithSubRegs<"EBX", [BX]>, DwarfRegNum<3>;
84 def ESI : RegisterWithSubRegs<"ESI", [SI]>, DwarfRegNum<4>;
85 def EDI : RegisterWithSubRegs<"EDI", [DI]>, DwarfRegNum<5>;
86 def EBP : RegisterWithSubRegs<"EBP", [BP]>, DwarfRegNum<6>;
87 def ESP : RegisterWithSubRegs<"ESP", [SP]>, DwarfRegNum<7>;
88 def EIP : RegisterWithSubRegs<"EIP", [IP]>, DwarfRegNum<16>;
82 def EAX : RegisterWithSubRegs<"EAX", [AX]>, DwarfRegNum<[0, 0, 0]>;
83 def EDX : RegisterWithSubRegs<"EDX", [DX]>, DwarfRegNum<[1, 2, 2]>;
84 def ECX : RegisterWithSubRegs<"ECX", [CX]>, DwarfRegNum<[2, 1, 1]>;
85 def EBX : RegisterWithSubRegs<"EBX", [BX]>, DwarfRegNum<[3, 3, 3]>;
86 def ESI : RegisterWithSubRegs<"ESI", [SI]>, DwarfRegNum<[4, 6, 6]>;
87 def EDI : RegisterWithSubRegs<"EDI", [DI]>, DwarfRegNum<[5, 7, 7]>;
88 def EBP : RegisterWithSubRegs<"EBP", [BP]>, DwarfRegNum<[6, 4, 5]>;
89 def ESP : RegisterWithSubRegs<"ESP", [SP]>, DwarfRegNum<[7, 5, 4]>;
90 def EIP : RegisterWithSubRegs<"EIP", [IP]>, DwarfRegNum<[16, 8, 8]>;
8991
9092 // X86-64 only
91 def R8D : RegisterWithSubRegs<"R8D", [R8W]>, DwarfRegNum<8>;
92 def R9D : RegisterWithSubRegs<"R9D", [R9W]>, DwarfRegNum<9>;
93 def R10D : RegisterWithSubRegs<"R10D", [R10W]>, DwarfRegNum<10>;
94 def R11D : RegisterWithSubRegs<"R11D", [R11W]>, DwarfRegNum<11>;
95 def R12D : RegisterWithSubRegs<"R12D", [R12W]>, DwarfRegNum<12>;
96 def R13D : RegisterWithSubRegs<"R13D", [R13W]>, DwarfRegNum<13>;
97 def R14D : RegisterWithSubRegs<"R14D", [R14W]>, DwarfRegNum<14>;
98 def R15D : RegisterWithSubRegs<"R15D", [R15W]>, DwarfRegNum<15>;
93 def R8D : RegisterWithSubRegs<"R8D", [R8W]>, DwarfRegNum<[8, -2, -2]>;
94 def R9D : RegisterWithSubRegs<"R9D", [R9W]>, DwarfRegNum<[9, -2, -2]>;
95 def R10D : RegisterWithSubRegs<"R10D", [R10W]>, DwarfRegNum<[10, -2, -2]>;
96 def R11D : RegisterWithSubRegs<"R11D", [R11W]>, DwarfRegNum<[11, -2, -2]>;
97 def R12D : RegisterWithSubRegs<"R12D", [R12W]>, DwarfRegNum<[12, -2, -2]>;
98 def R13D : RegisterWithSubRegs<"R13D", [R13W]>, DwarfRegNum<[13, -2, -2]>;
99 def R14D : RegisterWithSubRegs<"R14D", [R14W]>, DwarfRegNum<[14, -2, -2]>;
100 def R15D : RegisterWithSubRegs<"R15D", [R15W]>, DwarfRegNum<[15, -2, -2]>;
99101
100102 // 64-bit registers, X86-64 only
101 def RAX : RegisterWithSubRegs<"RAX", [EAX]>, DwarfRegNum<0>;
102 def RDX : RegisterWithSubRegs<"RDX", [EDX]>, DwarfRegNum<1>;
103 def RCX : RegisterWithSubRegs<"RCX", [ECX]>, DwarfRegNum<2>;
104 def RBX : RegisterWithSubRegs<"RBX", [EBX]>, DwarfRegNum<3>;
105 def RSI : RegisterWithSubRegs<"RSI", [ESI]>, DwarfRegNum<4>;
106 def RDI : RegisterWithSubRegs<"RDI", [EDI]>, DwarfRegNum<5>;
107 def RBP : RegisterWithSubRegs<"RBP", [EBP]>, DwarfRegNum<6>;
108 def RSP : RegisterWithSubRegs<"RSP", [ESP]>, DwarfRegNum<7>;
109
110 def R8 : RegisterWithSubRegs<"R8", [R8D]>, DwarfRegNum<8>;
111 def R9 : RegisterWithSubRegs<"R9", [R9D]>, DwarfRegNum<9>;
112 def R10 : RegisterWithSubRegs<"R10", [R10D]>, DwarfRegNum<10>;
113 def R11 : RegisterWithSubRegs<"R11", [R11D]>, DwarfRegNum<11>;
114 def R12 : RegisterWithSubRegs<"R12", [R12D]>, DwarfRegNum<12>;
115 def R13 : RegisterWithSubRegs<"R13", [R13D]>, DwarfRegNum<13>;
116 def R14 : RegisterWithSubRegs<"R14", [R14D]>, DwarfRegNum<14>;
117 def R15 : RegisterWithSubRegs<"R15", [R15D]>, DwarfRegNum<15>;
118 def RIP : RegisterWithSubRegs<"RIP", [EIP]>, DwarfRegNum<16>;
103 def RAX : RegisterWithSubRegs<"RAX", [EAX]>, DwarfRegNum<[0, -2, -2]>;
104 def RDX : RegisterWithSubRegs<"RDX", [EDX]>, DwarfRegNum<[1, -2, -2]>;
105 def RCX : RegisterWithSubRegs<"RCX", [ECX]>, DwarfRegNum<[2, -2, -2]>;
106 def RBX : RegisterWithSubRegs<"RBX", [EBX]>, DwarfRegNum<[3, -2, -2]>;
107 def RSI : RegisterWithSubRegs<"RSI", [ESI]>, DwarfRegNum<[4, -2, -2]>;
108 def RDI : RegisterWithSubRegs<"RDI", [EDI]>, DwarfRegNum<[5, -2, -2]>;
109 def RBP : RegisterWithSubRegs<"RBP", [EBP]>, DwarfRegNum<[6, -2, -2]>;
110 def RSP : RegisterWithSubRegs<"RSP", [ESP]>, DwarfRegNum<[7, -2, -2]>;
111
112 def R8 : RegisterWithSubRegs<"R8", [R8D]>, DwarfRegNum<[8, -2, -2]>;
113 def R9 : RegisterWithSubRegs<"R9", [R9D]>, DwarfRegNum<[9, -2, -2]>;
114 def R10 : RegisterWithSubRegs<"R10", [R10D]>, DwarfRegNum<[10, -2, -2]>;
115 def R11 : RegisterWithSubRegs<"R11", [R11D]>, DwarfRegNum<[11, -2, -2]>;
116 def R12 : RegisterWithSubRegs<"R12", [R12D]>, DwarfRegNum<[12, -2, -2]>;
117 def R13 : RegisterWithSubRegs<"R13", [R13D]>, DwarfRegNum<[13, -2, -2]>;
118 def R14 : RegisterWithSubRegs<"R14", [R14D]>, DwarfRegNum<[14, -2, -2]>;
119 def R15 : RegisterWithSubRegs<"R15", [R15D]>, DwarfRegNum<[15, -2, -2]>;
120 def RIP : RegisterWithSubRegs<"RIP", [EIP]>, DwarfRegNum<[16, -2, -2]>;
119121
120122 // MMX Registers. These are actually aliased to ST0 .. ST7
121 def MM0 : Register<"MM0">, DwarfRegNum<41>;
122 def MM1 : Register<"MM1">, DwarfRegNum<42>;
123 def MM2 : Register<"MM2">, DwarfRegNum<43>;
124 def MM3 : Register<"MM3">, DwarfRegNum<44>;
125 def MM4 : Register<"MM4">, DwarfRegNum<45>;
126 def MM5 : Register<"MM5">, DwarfRegNum<46>;
127 def MM6 : Register<"MM6">, DwarfRegNum<47>;
128 def MM7 : Register<"MM7">, DwarfRegNum<48>;
123 def MM0 : Register<"MM0">, DwarfRegNum<[41, 29, 29]>;
124 def MM1 : Register<"MM1">, DwarfRegNum<[42, 30, 30]>;
125 def MM2 : Register<"MM2">, DwarfRegNum<[43, 31, 31]>;
126 def MM3 : Register<"MM3">, DwarfRegNum<[44, 32, 32]>;
127 def MM4 : Register<"MM4">, DwarfRegNum<[45, 33, 33]>;
128 def MM5 : Register<"MM5">, DwarfRegNum<[46, 34, 34]>;
129 def MM6 : Register<"MM6">, DwarfRegNum<[47, 35, 35]>;
130 def MM7 : Register<"MM7">, DwarfRegNum<[48, 36, 36]>;
129131
130132 // Pseudo Floating Point registers
131 def FP0 : Register<"FP0">, DwarfRegNum<-1>;
132 def FP1 : Register<"FP1">, DwarfRegNum<-1>;
133 def FP2 : Register<"FP2">, DwarfRegNum<-1>;
134 def FP3 : Register<"FP3">, DwarfRegNum<-1>;
135 def FP4 : Register<"FP4">, DwarfRegNum<-1>;
136 def FP5 : Register<"FP5">, DwarfRegNum<-1>;
137 def FP6 : Register<"FP6">, DwarfRegNum<-1>;
133 def FP0 : Register<"FP0">;
134 def FP1 : Register<"FP1">;
135 def FP2 : Register<"FP2">;
136 def FP3 : Register<"FP3">;
137 def FP4 : Register<"FP4">;
138 def FP5 : Register<"FP5">;
139 def FP6 : Register<"FP6">;
138140
139141 // XMM Registers, used by the various SSE instruction set extensions
140 def XMM0: Register<"XMM0">, DwarfRegNum<17>;
141 def XMM1: Register<"XMM1">, DwarfRegNum<18>;
142 def XMM2: Register<"XMM2">, DwarfRegNum<19>;
143 def XMM3: Register<"XMM3">, DwarfRegNum<20>;
144 def XMM4: Register<"XMM4">, DwarfRegNum<21>;
145 def XMM5: Register<"XMM5">, DwarfRegNum<22>;
146 def XMM6: Register<"XMM6">, DwarfRegNum<23>;
147 def XMM7: Register<"XMM7">, DwarfRegNum<24>;
142 def XMM0: Register<"XMM0">, DwarfRegNum<[17, 21, 21]>;
143 def XMM1: Register<"XMM1">, DwarfRegNum<[18, 22, 22]>;
144 def XMM2: Register<"XMM2">, DwarfRegNum<[19, 23, 23]>;
145 def XMM3: Register<"XMM3">, DwarfRegNum<[20, 24, 24]>;
146 def XMM4: Register<"XMM4">, DwarfRegNum<[21, 25, 25]>;
147 def XMM5: Register<"XMM5">, DwarfRegNum<[22, 26, 26]>;
148 def XMM6: Register<"XMM6">, DwarfRegNum<[23, 27, 27]>;
149 def XMM7: Register<"XMM7">, DwarfRegNum<[24, 28, 28]>;
148150
149151 // X86-64 only
150 def XMM8: Register<"XMM8">, DwarfRegNum<25>;
151 def XMM9: Register<"XMM9">, DwarfRegNum<26>;
152 def XMM10: Register<"XMM10">, DwarfRegNum<27>;
153 def XMM11: Register<"XMM11">, DwarfRegNum<28>;
154 def XMM12: Register<"XMM12">, DwarfRegNum<29>;
155 def XMM13: Register<"XMM13">, DwarfRegNum<30>;
156 def XMM14: Register<"XMM14">, DwarfRegNum<31>;
157 def XMM15: Register<"XMM15">, DwarfRegNum<32>;
152 def XMM8: Register<"XMM8">, DwarfRegNum<[25, -2, -2]>;
153 def XMM9: Register<"XMM9">, DwarfRegNum<[26, -2, -2]>;
154 def XMM10: Register<"XMM10">, DwarfRegNum<[27, -2, -2]>;
155 def XMM11: Register<"XMM11">, DwarfRegNum<[28, -2, -2]>;
156 def XMM12: Register<"XMM12">, DwarfRegNum<[29, -2, -2]>;
157 def XMM13: Register<"XMM13">, DwarfRegNum<[30, -2, -2]>;
158 def XMM14: Register<"XMM14">, DwarfRegNum<[31, -2, -2]>;
159 def XMM15: Register<"XMM15">, DwarfRegNum<[32, -2, -2]>;
158160
159161 // Floating point stack registers
160 def ST0 : Register<"ST(0)">, DwarfRegNum<33>;
161 def ST1 : Register<"ST(1)">, DwarfRegNum<34>;
162 def ST2 : Register<"ST(2)">, DwarfRegNum<35>;
163 def ST3 : Register<"ST(3)">, DwarfRegNum<36>;
164 def ST4 : Register<"ST(4)">, DwarfRegNum<37>;
165 def ST5 : Register<"ST(5)">, DwarfRegNum<38>;
166 def ST6 : Register<"ST(6)">, DwarfRegNum<39>;
167 def ST7 : Register<"ST(7)">, DwarfRegNum<40>;
162 def ST0 : Register<"ST(0)">, DwarfRegNum<[33, 12, 11]>;
163 def ST1 : Register<"ST(1)">, DwarfRegNum<[34, 13, 12]>;
164 def ST2 : Register<"ST(2)">, DwarfRegNum<[35, 14, 13]>;
165 def ST3 : Register<"ST(3)">, DwarfRegNum<[36, 15, 14]>;
166 def ST4 : Register<"ST(4)">, DwarfRegNum<[37, 16, 15]>;
167 def ST5 : Register<"ST(5)">, DwarfRegNum<[38, 17, 16]>;
168 def ST6 : Register<"ST(6)">, DwarfRegNum<[39, 18, 17]>;
169 def ST7 : Register<"ST(7)">, DwarfRegNum<[40, 19, 18]>;
168170
169171 // Status flags register
170172 def EFLAGS : Register<"EFLAGS">;
5959 OS << "struct " << ClassName << " : public MRegisterInfo {\n"
6060 << " " << ClassName
6161 << "(int CallFrameSetupOpcode = -1, int CallFrameDestroyOpcode = -1);\n"
62 << " virtual int getDwarfRegNum(unsigned RegNum) const;\n"
62 << " virtual int getDwarfRegNumFull(unsigned RegNum, "
63 << "unsigned Flavour) const;\n"
64 << " virtual int getDwarfRegNum(unsigned RegNum) const = 0;\n"
6365 << " unsigned getSubReg(unsigned RegNo, unsigned Index) const;\n"
6466 << "};\n\n";
6567
405407 std::map > RegisterSuperRegs;
406408 std::map > RegisterAliases;
407409 std::map > > SubRegVectors;
410 std::map > DwarfRegNums;
411
408412 const std::vector &Regs = Target.getRegisters();
409413
410414 for (unsigned i = 0, e = Regs.size(); i != e; ++i) {
589593 << ", RegisterClasses, RegisterClasses+" << RegisterClasses.size() <<",\n "
590594 << " CallFrameSetupOpcode, CallFrameDestroyOpcode) {}\n\n";
591595
596 // Collect all information about dwarf register numbers
597
598 // First, just pull all provided information to the map
599 unsigned maxLength = 0;
600 for (unsigned i = 0, e = Registers.size(); i != e; ++i) {
601 Record *Reg = Registers[i].TheDef;
602 std::vector RegNums = Reg->getValueAsListOfInts("DwarfNumbers");
603 maxLength = std::max(maxLength, RegNums.size());
604 if (DwarfRegNums.count(Reg))
605 cerr << "Warning: DWARF numbers for register " << getQualifiedName(Reg)
606 << "specified multiple times\n";
607 DwarfRegNums[Reg] = RegNums;
608 }
609
610 // Now we know maximal length of number list. Append -1's, where needed
611 for (std::map >::iterator
612 I = DwarfRegNums.begin(), E = DwarfRegNums.end(); I != E; ++I)
613 for (unsigned i = I->second.size(), e = maxLength; i != e; ++i)
614 I->second.push_back(-1);
615
592616 // Emit information about the dwarf register numbers.
593 OS << "int " << ClassName << "::getDwarfRegNum(unsigned RegNum) const {\n";
594 OS << " static const int DwarfRegNums[] = { -1, // NoRegister";
595 for (unsigned i = 0, e = Registers.size(); i != e; ++i) {
596 if (!(i % 16)) OS << "\n ";
597 const CodeGenRegister &Reg = Registers[i];
598 int DwarfRegNum = Reg.TheDef->getValueAsInt("DwarfNumber");
599 OS << DwarfRegNum;
600 if ((i + 1) != e) OS << ", ";
601 }
602 OS << "\n };\n";
603 OS << " assert(RegNum < (sizeof(DwarfRegNums)/sizeof(int)) &&\n";
604 OS << " \"RegNum exceeds number of registers\");\n";
605 OS << " return DwarfRegNums[RegNum];\n";
606 OS << "}\n\n";
617 OS << "int " << ClassName << "::getDwarfRegNumFull(unsigned RegNum, "
618 << "unsigned Flavour) const {\n"
619 << " switch (Flavour) {\n"
620 << " default:\n"
621 << " assert(0 && \"Unknown DWARF flavour\");\n"
622 << " return -1;\n";
623
624 for (unsigned i = 0, e = maxLength; i != e; ++i) {
625 OS << " case " << i << ":\n"
626 << " switch (RegNum) {\n"
627 << " default:\n"
628 << " assert(0 && \"Invalid RegNum\");\n"
629 << " return -1;\n";
630
631 for (std::map >::iterator
632 I = DwarfRegNums.begin(), E = DwarfRegNums.end(); I != E; ++I) {
633 int RegNo = I->second[i];
634 if (RegNo != -2)
635 OS << " case " << getQualifiedName(I->first) << ":\n"
636 << " return " << RegNo << ";\n";
637 else
638 OS << " case " << getQualifiedName(I->first) << ":\n"
639 << " assert(0 && \"Invalid register for this mode\");\n"
640 << " return -1;\n";
641 }
642 OS << " };\n";
643 }
644
645 OS << " };\n}\n\n";
607646
608647 OS << "} // End llvm namespace \n";
609648 }