llvm.org GIT mirror llvm / f179b3f
Get the cached subtarget off the MachineFunction rather than inquiring for a new one from the TargetMachine. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@229999 91177308-0d34-0410-b5e6-96231b3b80d8 Eric Christopher 5 years ago
8 changed file(s) with 17 addition(s) and 16 deletion(s). Raw diff Collapse all Expand all
18631863 void ARMFrameLowering::adjustForSegmentedStacks(MachineFunction &MF) const {
18641864 unsigned Opcode;
18651865 unsigned CFIIndex;
1866 const ARMSubtarget *ST = &MF.getTarget().getSubtarget();
1866 const ARMSubtarget *ST = &MF.getSubtarget();
18671867 bool Thumb = ST->isThumb();
18681868
18691869 // Sadly, this currently doesn't support varargs, platforms other than
6969
7070 bool runOnMachineFunction(MachineFunction &MF) override {
7171 // Reset the subtarget each time through.
72 Subtarget = &MF.getTarget().getSubtarget();
72 Subtarget = &MF.getSubtarget();
7373 SelectionDAGISel::runOnMachineFunction(MF);
7474 return true;
7575 }
9292 void ARMInstrInfo::expandLoadStackGuard(MachineBasicBlock::iterator MI,
9393 Reloc::Model RM) const {
9494 MachineFunction &MF = *MI->getParent()->getParent();
95 const ARMSubtarget &Subtarget = MF.getTarget().getSubtarget();
95 const ARMSubtarget &Subtarget = MF.getSubtarget();
9696
9797 if (!Subtarget.useMovt(MF)) {
9898 if (RM == Reloc::PIC_)
1313 void ARMFunctionInfo::anchor() { }
1414
1515 ARMFunctionInfo::ARMFunctionInfo(MachineFunction &MF)
16 : isThumb(MF.getTarget().getSubtarget().isThumb()),
17 hasThumb2(MF.getTarget().getSubtarget().hasThumb2()),
16 : isThumb(MF.getSubtarget().isThumb()),
17 hasThumb2(MF.getSubtarget().hasThumb2()),
1818 StByValParamsPadding(0), ArgRegsSaveSize(0), HasStackFrame(false),
1919 RestoreSPFromFP(false), LRSpilledForFarJump(false),
2020 FramePtrSpillOffset(0), GPRCS1Offset(0), GPRCS2Offset(0), DPRCSOffset(0),
198198 // Thumb1 instructions that know how to use hi regs.
199199 let AltOrders = [(add LR, GPR), (trunc GPR, 8)];
200200 let AltOrderSelect = [{
201 return 1 + MF.getTarget().getSubtarget().isThumb1Only();
201 return 1 + MF.getSubtarget().isThumb1Only();
202202 }];
203203 }
204204
208208 def GPRnopc : RegisterClass<"ARM", [i32], 32, (sub GPR, PC)> {
209209 let AltOrders = [(add LR, GPRnopc), (trunc GPRnopc, 8)];
210210 let AltOrderSelect = [{
211 return 1 + MF.getTarget().getSubtarget().isThumb1Only();
211 return 1 + MF.getSubtarget().isThumb1Only();
212212 }];
213213 }
214214
218218 def GPRwithAPSR : RegisterClass<"ARM", [i32], 32, (add (sub GPR, PC), APSR_NZCV)> {
219219 let AltOrders = [(add LR, GPRnopc), (trunc GPRnopc, 8)];
220220 let AltOrderSelect = [{
221 return 1 + MF.getTarget().getSubtarget().isThumb1Only();
221 return 1 + MF.getSubtarget().isThumb1Only();
222222 }];
223223 }
224224
236236 def rGPR : RegisterClass<"ARM", [i32], 32, (sub GPR, SP, PC)> {
237237 let AltOrders = [(add LR, rGPR), (trunc rGPR, 8)];
238238 let AltOrderSelect = [{
239 return 1 + MF.getTarget().getSubtarget().isThumb1Only();
239 return 1 + MF.getSubtarget().isThumb1Only();
240240 }];
241241 }
242242
254254 def tcGPR : RegisterClass<"ARM", [i32], 32, (add R0, R1, R2, R3, R12)> {
255255 let AltOrders = [(and tcGPR, tGPR)];
256256 let AltOrderSelect = [{
257 return MF.getTarget().getSubtarget().isThumb1Only();
257 return MF.getSubtarget().isThumb1Only();
258258 }];
259259 }
260260
3131 bool isVolatile, bool AlwaysInline,
3232 MachinePointerInfo DstPtrInfo,
3333 MachinePointerInfo SrcPtrInfo) const {
34 const ARMSubtarget &Subtarget = DAG.getTarget().getSubtarget();
34 const ARMSubtarget &Subtarget =
35 DAG.getMachineFunction().getSubtarget();
3536 // Do repeated 4-byte loads and stores. To be improved.
3637 // This requires 4-byte alignment.
3738 if ((Align & 3) != 0)
149150 SDValue Src, SDValue Size,
150151 unsigned Align, bool isVolatile,
151152 MachinePointerInfo DstPtrInfo) const {
152 const ARMSubtarget &Subtarget = DAG.getTarget().getSubtarget();
153 const ARMSubtarget &Subtarget =
154 DAG.getMachineFunction().getSubtarget();
153155 // Use default for non-AAPCS (or MachO) subtargets
154156 if (!Subtarget.isAAPCS_ABI() || Subtarget.isTargetMachO() ||
155157 Subtarget.isTargetWindows())
156158 return SDValue();
157159
158 const ARMTargetLowering &TLI =
159 *DAG.getTarget().getSubtarget().getTargetLowering();
160 const ARMTargetLowering &TLI = *Subtarget.getTargetLowering();
160161 TargetLowering::ArgListTy Args;
161162 TargetLowering::ArgListEntry Entry;
162163
380380 TII = static_cast(Fn.getSubtarget().getInstrInfo());
381381 TRI = Fn.getSubtarget().getRegisterInfo();
382382 MRI = &Fn.getRegInfo();
383 const ARMSubtarget *STI = &Fn.getTarget().getSubtarget();
383 const ARMSubtarget *STI = &Fn.getSubtarget();
384384 isLikeA9 = STI->isLikeA9() || STI->isSwift();
385385 isSwift = STI->isSwift();
386386
4343 bool KillSrc) const {
4444 // Need to check the arch.
4545 MachineFunction &MF = *MBB.getParent();
46 const ARMSubtarget &st = MF.getTarget().getSubtarget();
46 const ARMSubtarget &st = MF.getSubtarget();
4747
4848 assert(ARM::GPRRegClass.contains(DestReg, SrcReg) &&
4949 "Thumb1 can only copy GPR registers");