llvm.org GIT mirror llvm / f160ecc
[X86][AVX512] Fix PR31515 - Do not flip vselect condition if it's not a vXi1 mask r289653 added a case where `vselect <cond> <vector1> <all-zeros>` is transformed to: `vselect xor(cond, DAG.getConstant(1, DL, CondVT) <all-zeros> <vector1>` This was not aimed to catch cases where Cond is not a vXi1 mask but it does. Moreover, when Cond type is VxiN (N > 1) then xor(cond, DAG.getConstant(1, DL, CondVT) != NOT(cond). This patch changes the above to xor with allones, and avoids entering the case for non-mask Conds. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@291745 91177308-0d34-0410-b5e6-96231b3b80d8 Elad Cohen 3 years ago
2 changed file(s) with 27 addition(s) and 5 deletion(s). Raw diff Collapse all Expand all
2875328753 if (N->getOpcode() != ISD::VSELECT)
2875428754 return SDValue();
2875528755
28756 assert(CondVT.isVector() && "Vector select expects a vector selector!");
28757
2875628758 bool FValIsAllZeros = ISD::isBuildVectorAllZeros(LHS.getNode());
28757 // Check if the first operand is all zeros.This situation only
28758 // applies to avx512.
28759 if (FValIsAllZeros && Subtarget.hasAVX512() && Cond.hasOneUse()) {
28759 // Check if the first operand is all zeros and Cond type is vXi1.
28760 // This situation only applies to avx512.
28761 if (FValIsAllZeros && Subtarget.hasAVX512() && Cond.hasOneUse() &&
28762 CondVT.getVectorElementType() == MVT::i1) {
2876028763 //Invert the cond to not(cond) : xor(op,allones)=not(op)
2876128764 SDValue CondNew = DAG.getNode(ISD::XOR, DL, Cond.getValueType(), Cond,
28762 DAG.getConstant(1, DL, Cond.getValueType()));
28765 DAG.getConstant(APInt::getAllOnesValue(CondVT.getScalarSizeInBits()),
28766 DL, CondVT));
2876328767 //Vselect cond, op1, op2 = Vselect not(cond), op2, op1
2876428768 return DAG.getNode(ISD::VSELECT, DL, VT, CondNew, RHS, LHS);
2876528769 }
28766 assert(CondVT.isVector() && "Vector select expects a vector selector!");
2876728770
2876828771 // To use the condition operand as a bitwise mask, it must have elements that
2876928772 // are the same size as the select elements. Ie, the condition operand must
178178 %cond = select i1 %c, float %a, float %b
179179 ret float %cond
180180 }
181
182 define <16 x i16> @pr31515(<16 x i1> %a, <16 x i1> %b, <16 x i16> %c) nounwind {
183 ; CHECK-LABEL: pr31515:
184 ; CHECK: ## BB#0:
185 ; CHECK-NEXT: vpmovsxbd %xmm1, %zmm1
186 ; CHECK-NEXT: vpslld $31, %zmm1, %zmm1
187 ; CHECK-NEXT: vpmovsxbd %xmm0, %zmm0
188 ; CHECK-NEXT: vpslld $31, %zmm0, %zmm0
189 ; CHECK-NEXT: vptestmd %zmm0, %zmm0, %k1
190 ; CHECK-NEXT: vptestmd %zmm1, %zmm1, %k1 {%k1}
191 ; CHECK-NEXT: vpternlogd $255, %zmm0, %zmm0, %zmm0 {%k1} {z}
192 ; CHECK-NEXT: vpmovdw %zmm0, %ymm0
193 ; CHECK-NEXT: vpandn %ymm2, %ymm0, %ymm0
194 ; CHECK-NEXT: retq
195 %mask = and <16 x i1> %a, %b
196 %res = select <16 x i1> %mask, <16 x i16> zeroinitializer, <16 x i16> %c
197 ret <16 x i16> %res
198 }
199