llvm.org GIT mirror llvm / f0a0cdd
- Added getOpcodeAfterMemoryUnfold(). It doesn't unfold an instruction, but only returns the opcode of the instruction post unfolding. - Fix some copy+paste bugs. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@43153 91177308-0d34-0410-b5e6-96231b3b80d8 Evan Cheng 12 years ago
15 changed file(s) with 58 addition(s) and 30 deletion(s). Raw diff Collapse all Expand all
507507 const TargetRegisterClass *RC) const = 0;
508508
509509 virtual void storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
510 SmallVectorImpl Addr,
510 SmallVectorImpl &Addr,
511511 const TargetRegisterClass *RC,
512512 SmallVectorImpl &NewMIs) const = 0;
513513
517517 const TargetRegisterClass *RC) const = 0;
518518
519519 virtual void loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
520 SmallVectorImpl Addr,
520 SmallVectorImpl &Addr,
521521 const TargetRegisterClass *RC,
522522 SmallVectorImpl &NewMIs) const =0;
523523
574574 virtual bool unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N,
575575 SmallVectorImpl &NewNodes) const {
576576 return false;
577 }
578
579 /// getOpcodeAfterMemoryUnfold - Returns the opcode of the would be new
580 /// instruction after load / store are unfolded from the specified opcode.
581 /// It returns zero if the specified unfolding is impossible.
582 virtual unsigned getOpcodeAfterMemoryUnfold(unsigned Opc,
583 bool UnfoldLoad, bool UnfoldStore) const {
584 return 0;
577585 }
578586
579587 /// targetHandlesStackFrameRounding - Returns true if the target is
182182 }
183183
184184 void ARMRegisterInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
185 SmallVectorImpl Addr,
185 SmallVectorImpl &Addr,
186186 const TargetRegisterClass *RC,
187187 SmallVectorImpl &NewMIs) const {
188188 unsigned Opc = 0;
238238 }
239239
240240 void ARMRegisterInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
241 SmallVectorImpl Addr,
241 SmallVectorImpl &Addr,
242242 const TargetRegisterClass *RC,
243243 SmallVectorImpl &NewMIs) const {
244244 unsigned Opc = 0;
5151 const TargetRegisterClass *RC) const;
5252
5353 void storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
54 SmallVectorImpl Addr,
54 SmallVectorImpl &Addr,
5555 const TargetRegisterClass *RC,
5656 SmallVectorImpl &NewMIs) const;
5757
6161 const TargetRegisterClass *RC) const;
6262
6363 void loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
64 SmallVectorImpl Addr,
64 SmallVectorImpl &Addr,
6565 const TargetRegisterClass *RC,
6666 SmallVectorImpl &NewMIs) const;
6767
8282 }
8383
8484 void AlphaRegisterInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
85 SmallVectorImpl Addr,
85 SmallVectorImpl &Addr,
8686 const TargetRegisterClass *RC,
8787 SmallVectorImpl &NewMIs) const {
8888 unsigned Opc = 0;
127127 }
128128
129129 void AlphaRegisterInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
130 SmallVectorImpl Addr,
130 SmallVectorImpl &Addr,
131131 const TargetRegisterClass *RC,
132132 SmallVectorImpl &NewMIs) const {
133133 unsigned Opc = 0;
3333 const TargetRegisterClass *RC) const;
3434
3535 void storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
36 SmallVectorImpl Addr,
36 SmallVectorImpl &Addr,
3737 const TargetRegisterClass *RC,
3838 SmallVectorImpl &NewMIs) const;
3939
4343 const TargetRegisterClass *RC) const;
4444
4545 void loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
46 SmallVectorImpl Addr,
46 SmallVectorImpl &Addr,
4747 const TargetRegisterClass *RC,
4848 SmallVectorImpl &NewMIs) const;
4949
6060 }
6161
6262 void IA64RegisterInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
63 SmallVectorImpl Addr,
63 SmallVectorImpl &Addr,
6464 const TargetRegisterClass *RC,
6565 SmallVectorImpl &NewMIs) const {
6666 unsigned Opc = 0;
112112 }
113113
114114 void IA64RegisterInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
115 SmallVectorImpl Addr,
115 SmallVectorImpl &Addr,
116116 const TargetRegisterClass *RC,
117117 SmallVectorImpl &NewMIs) const {
118118 unsigned Opc = 0;
3434 const TargetRegisterClass *RC) const;
3535
3636 void storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
37 SmallVectorImpl Addr,
37 SmallVectorImpl &Addr,
3838 const TargetRegisterClass *RC,
3939 SmallVectorImpl &NewMIs) const;
4040
4444 const TargetRegisterClass *RC) const;
4545
4646 void loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
47 SmallVectorImpl Addr,
47 SmallVectorImpl &Addr,
4848 const TargetRegisterClass *RC,
4949 SmallVectorImpl &NewMIs) const;
5050
9595 }
9696
9797 void MipsRegisterInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
98 SmallVectorImpl Addr,
98 SmallVectorImpl &Addr,
9999 const TargetRegisterClass *RC,
100100 SmallVectorImpl &NewMIs) const {
101101 if (RC != Mips::CPURegsRegisterClass)
127127 }
128128
129129 void MipsRegisterInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
130 SmallVectorImpl Addr,
130 SmallVectorImpl &Addr,
131131 const TargetRegisterClass *RC,
132132 SmallVectorImpl &NewMIs) const {
133133 if (RC != Mips::CPURegsRegisterClass)
3737 const TargetRegisterClass *RC) const;
3838
3939 void storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
40 SmallVectorImpl Addr,
40 SmallVectorImpl &Addr,
4141 const TargetRegisterClass *RC,
4242 SmallVectorImpl &NewMIs) const;
4343
4747 const TargetRegisterClass *RC) const;
4848
4949 void loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
50 SmallVectorImpl Addr,
50 SmallVectorImpl &Addr,
5151 const TargetRegisterClass *RC,
5252 SmallVectorImpl &NewMIs) const;
5353
181181 }
182182
183183 void PPCRegisterInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
184 SmallVectorImpl Addr,
184 SmallVectorImpl &Addr,
185185 const TargetRegisterClass *RC,
186186 SmallVectorImpl &NewMIs) const {
187187 if (Addr[0].isFrameIndex()) {
290290 }
291291
292292 void PPCRegisterInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
293 SmallVectorImpl Addr,
293 SmallVectorImpl &Addr,
294294 const TargetRegisterClass *RC,
295295 SmallVectorImpl &NewMIs) const {
296296 if (Addr[0].isFrameIndex()) {
4040 const TargetRegisterClass *RC) const;
4141
4242 void storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
43 SmallVectorImpl Addr,
43 SmallVectorImpl &Addr,
4444 const TargetRegisterClass *RC,
4545 SmallVectorImpl &NewMIs) const;
4646
5050 const TargetRegisterClass *RC) const;
5151
5252 void loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
53 SmallVectorImpl Addr,
53 SmallVectorImpl &Addr,
5454 const TargetRegisterClass *RC,
5555 SmallVectorImpl &NewMIs) const;
5656
4848 }
4949
5050 void SparcRegisterInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
51 SmallVectorImpl Addr,
51 SmallVectorImpl &Addr,
5252 const TargetRegisterClass *RC,
5353 SmallVectorImpl &NewMIs) const {
5454 unsigned Opc = 0;
9090 }
9191
9292 void SparcRegisterInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
93 SmallVectorImpl Addr,
93 SmallVectorImpl &Addr,
9494 const TargetRegisterClass *RC,
9595 SmallVectorImpl &NewMIs) const {
9696 unsigned Opc = 0;
3535 const TargetRegisterClass *RC) const;
3636
3737 void storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
38 SmallVectorImpl Addr,
38 SmallVectorImpl &Addr,
3939 const TargetRegisterClass *RC,
4040 SmallVectorImpl &NewMIs) const;
4141
4545 const TargetRegisterClass *RC) const;
4646
4747 void loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
48 SmallVectorImpl Addr,
48 SmallVectorImpl &Addr,
4949 const TargetRegisterClass *RC,
5050 SmallVectorImpl &NewMIs) const;
5151
805805 }
806806
807807 void X86RegisterInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
808 SmallVectorImpl Addr,
808 SmallVectorImpl &Addr,
809809 const TargetRegisterClass *RC,
810810 SmallVectorImpl &NewMIs) const {
811811 unsigned Opc = getStoreRegOpcode(RC);
861861 }
862862
863863 void X86RegisterInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
864 SmallVectorImpl Addr,
864 SmallVectorImpl &Addr,
865865 const TargetRegisterClass *RC,
866866 SmallVectorImpl &NewMIs) const {
867867 unsigned Opc = getLoadRegOpcode(RC);
12721272 return true;
12731273 }
12741274
1275 unsigned X86RegisterInfo::getOpcodeAfterMemoryUnfold(unsigned Opc,
1276 bool UnfoldLoad, bool UnfoldStore) const {
1277 DenseMap >::iterator I =
1278 MemOp2RegOpTable.find((unsigned*)Opc);
1279 if (I == MemOp2RegOpTable.end())
1280 return 0;
1281 bool HasLoad = I->second.second & (1 << 4);
1282 bool HasStore = I->second.second & (1 << 5);
1283 if (UnfoldLoad && !HasLoad)
1284 return 0;
1285 if (UnfoldStore && !HasStore)
1286 return 0;
1287 return I->second.first;
1288 }
12751289
12761290 const unsigned *
12771291 X86RegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
8888 const TargetRegisterClass *RC) const;
8989
9090 void storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
91 SmallVectorImpl Addr,
91 SmallVectorImpl &Addr,
9292 const TargetRegisterClass *RC,
9393 SmallVectorImpl &NewMIs) const;
9494
9898 const TargetRegisterClass *RC) const;
9999
100100 void loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
101 SmallVectorImpl Addr,
101 SmallVectorImpl &Addr,
102102 const TargetRegisterClass *RC,
103103 SmallVectorImpl &NewMIs) const;
104104
141141 bool unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N,
142142 SmallVectorImpl &NewNodes) const;
143143
144 /// getOpcodeAfterMemoryUnfold - Returns the opcode of the would be new
145 /// instruction after load / store are unfolded from the specified opcode.
146 /// It returns zero if the specified unfolding is impossible.
147 unsigned getOpcodeAfterMemoryUnfold(unsigned Opc,
148 bool UnfoldLoad, bool UnfoldStore) const;
149
144150 /// getCalleeSavedRegs - Return a null-terminated list of all of the
145151 /// callee-save registers on this target.
146152 const unsigned *getCalleeSavedRegs(const MachineFunction* MF = 0) const;