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Merging r243294: ------------------------------------------------------------------------ r243294 | mareko | 2015-07-27 11:16:08 -0700 (Mon, 27 Jul 2015) | 9 lines AMDGPU: don't match vgpr loads for constant loads Author: Dave Airlie <airlied@redhat.com> In order to implement indirect sampler loads, we don't want to match on a VGPR load but an SGPR one for constants, as we cannot feed VGPRs to the sampler only SGPRs. this should be applicable for llvm 3.7 as well. ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_37@243317 91177308-0d34-0410-b5e6-96231b3b80d8 Hans Wennborg 5 years ago
3 changed file(s) with 4 addition(s) and 19 deletion(s). Raw diff Collapse all Expand all
29092909 defm : MUBUFLoad_Pattern ;
29102910 defm : MUBUFLoad_Pattern ;
29112911 defm : MUBUFLoad_Pattern ;
2912 defm : MUBUFLoad_Pattern ;
2913 defm : MUBUFLoad_Pattern ;
2914 defm : MUBUFLoad_Pattern ;
29152912 } // End Predicates = [isSICI]
29162913
29172914 class MUBUFScratchLoadPat : Pat <
77 @float_gv = internal unnamed_addr addrspace(2) constant [5 x float] [float 0.0, float 1.0, float 2.0, float 3.0, float 4.0], align 4
88
99 ; FUNC-LABEL: {{^}}float:
10 ; FIXME: We should be using s_load_dword here.
11 ; SI: buffer_load_dword
12 ; VI: s_load_dword
10 ; GCN: s_load_dword
1311
1412 ; EG-DAG: MOV {{\** *}}T2.X
1513 ; EG-DAG: MOV {{\** *}}T3.X
3028
3129 ; FUNC-LABEL: {{^}}i32:
3230
33 ; FIXME: We should be using s_load_dword here.
34 ; SI: buffer_load_dword
35 ; VI: s_load_dword
31 ; GCN: s_load_dword
3632
3733 ; EG-DAG: MOV {{\** *}}T2.X
3834 ; EG-DAG: MOV {{\** *}}T3.X
7066 <1 x i32> ]
7167
7268 ; FUNC-LABEL: {{^}}array_v1_gv_load:
73 ; FIXME: We should be using s_load_dword here.
74 ; SI: buffer_load_dword
75 ; VI: s_load_dword
69 ; GCN: s_load_dword
7670 define void @array_v1_gv_load(<1 x i32> addrspace(1)* %out, i32 %index) {
7771 %gep = getelementptr inbounds [4 x <1 x i32>], [4 x <1 x i32>] addrspace(2)* @array_v1_gv, i32 0, i32 %index
7872 %load = load <1 x i32>, <1 x i32> addrspace(2)* %gep, align 4
4242 ; GCN-LABEL: {{^}}smrd3:
4343 ; FIXME: There are too many copies here because we don't fold immediates
4444 ; through REG_SEQUENCE
45 ; SI: s_mov_b32 s[[SLO:[0-9]+]], 0 ;
46 ; SI: s_mov_b32 s[[SHI:[0-9]+]], 4
47 ; SI: s_mov_b32 s[[SSLO:[0-9]+]], s[[SLO]]
48 ; SI-DAG: v_mov_b32_e32 v[[VLO:[0-9]+]], s[[SSLO]]
49 ; SI-DAG: v_mov_b32_e32 v[[VHI:[0-9]+]], s[[SHI]]
50 ; FIXME: We should be able to use s_load_dword here
51 ; SI: buffer_load_dword v{{[0-9]+}}, v{{\[}}[[VLO]]:[[VHI]]{{\]}}, s[{{[0-9]+:[0-9]+}}], 0 addr64
45 ; SI: s_load_dwordx2 s[{{[0-9]:[0-9]}}], s[{{[0-9]:[0-9]}}], 0xb ; encoding: [0x0b
5246 ; TODO: Add VI checks
5347 ; GCN: s_endpgm
5448 define void @smrd3(i32 addrspace(1)* %out, i32 addrspace(2)* %ptr) {