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R600: Emit config values in register / value pairs Reviewed-by: Vincent Lejeune <vljn@ovi.com> Tested-By: Aaron Watry <awatry@gmail.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181228 91177308-0d34-0410-b5e6-96231b3b80d8 Tom Stellard 7 years ago
3 changed file(s) with 58 addition(s) and 5 deletion(s). Raw diff Collapse all Expand all
2121 #include "SIDefines.h"
2222 #include "SIMachineFunctionInfo.h"
2323 #include "SIRegisterInfo.h"
24 #include "R600Defines.h"
2425 #include "R600MachineFunctionInfo.h"
2526 #include "R600RegisterInfo.h"
2627 #include "llvm/MC/MCContext.h"
7778 const R600RegisterInfo * RI =
7879 static_cast(TM.getRegisterInfo());
7980 R600MachineFunctionInfo *MFI = MF.getInfo();
81 const AMDGPUSubtarget &STM = TM.getSubtarget();
8082
8183 for (MachineFunction::iterator BB = MF.begin(), BB_E = MF.end();
8284 BB != BB_E; ++BB) {
100102 }
101103 }
102104 }
103 OutStreamer.EmitIntValue(MaxGPR + 1, 4);
104 OutStreamer.EmitIntValue(MFI->StackSize, 4);
105 OutStreamer.EmitIntValue(killPixel, 4);
105
106 unsigned RsrcReg;
107 if (STM.device()->getGeneration() >= AMDGPUDeviceInfo::HD5XXX) {
108 // Evergreen / Northern Islands
109 switch (MFI->ShaderType) {
110 default: // Fall through
111 case ShaderType::COMPUTE: RsrcReg = R_0288D4_SQ_PGM_RESOURCES_LS; break;
112 case ShaderType::GEOMETRY: RsrcReg = R_028878_SQ_PGM_RESOURCES_GS; break;
113 case ShaderType::PIXEL: RsrcReg = R_028844_SQ_PGM_RESOURCES_PS; break;
114 case ShaderType::VERTEX: RsrcReg = R_028860_SQ_PGM_RESOURCES_VS; break;
115 }
116 } else {
117 // R600 / R700
118 switch (MFI->ShaderType) {
119 default: // Fall through
120 case ShaderType::GEOMETRY: // Fall through
121 case ShaderType::COMPUTE: // Fall through
122 case ShaderType::VERTEX: RsrcReg = R_028868_SQ_PGM_RESOURCES_VS; break;
123 case ShaderType::PIXEL: RsrcReg = R_028850_SQ_PGM_RESOURCES_PS; break;
124 }
125 }
126
127 OutStreamer.EmitIntValue(RsrcReg, 4);
128 OutStreamer.EmitIntValue(S_NUM_GPRS(MaxGPR + 1) |
129 S_STACK_SIZE(MFI->StackSize), 4);
130 OutStreamer.EmitIntValue(R_02880C_DB_SHADER_CONTROL, 4);
131 OutStreamer.EmitIntValue(S_02880C_KILL_ENABLE(killPixel), 4);
106132 }
107133
108134 void AMDGPUAsmPrinter::EmitProgramInfoSI(MachineFunction &MF) {
9696
9797 }
9898
99 //===----------------------------------------------------------------------===//
100 // Config register definitions
101 //===----------------------------------------------------------------------===//
102
103 #define R_02880C_DB_SHADER_CONTROL 0x02880C
104 #define S_02880C_KILL_ENABLE(x) (((x) & 0x1) << 6)
105
106 // These fields are the same for all shader types and families.
107 #define S_NUM_GPRS(x) (((x) & 0xFF) << 0)
108 #define S_STACK_SIZE(x) (((x) & 0xFF) << 8)
109 //===----------------------------------------------------------------------===//
110 // R600, R700 Registers
111 //===----------------------------------------------------------------------===//
112
113 #define R_028850_SQ_PGM_RESOURCES_PS 0x028850
114 #define R_028868_SQ_PGM_RESOURCES_VS 0x028868
115
116 //===----------------------------------------------------------------------===//
117 // Evergreen, Northern Islands Registers
118 //===----------------------------------------------------------------------===//
119
120 #define R_028844_SQ_PGM_RESOURCES_PS 0x028844
121 #define R_028860_SQ_PGM_RESOURCES_VS 0x028860
122 #define R_028878_SQ_PGM_RESOURCES_GS 0x028878
123 #define R_0288D4_SQ_PGM_RESOURCES_LS 0x0288d4
124
99125 #endif // R600DEFINES_H_
44 ; ELF-CHECK: Name: .AMDGPU.config
55
66 ; CONFIG-CHECK: .section .AMDGPU.config
7 ; CONFIG-CHECK-NEXT: .long 2
8 ; CONFIG-CHECK-NEXT: .long 1
7 ; CONFIG-CHECK-NEXT: .long 166100
8 ; CONFIG-CHECK-NEXT: .long 258
9 ; CONFIG-CHECK-NEXT: .long 165900
910 ; CONFIG-CHECK-NEXT: .long 0
1011 define void @test(float addrspace(1)* %out, i32 %p) {
1112 %i = add i32 %p, 2