llvm.org GIT mirror llvm / f06e6c2
Catch more cases where 2-address pass should 3-addressify instructions. rdar://9002648. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@126811 91177308-0d34-0410-b5e6-96231b3b80d8 Evan Cheng 8 years ago
3 changed file(s) with 86 addition(s) and 55 deletion(s). Raw diff Collapse all Expand all
104104 MachineFunction::iterator &mbbi,
105105 unsigned RegB, unsigned RegC, unsigned Dist);
106106
107 bool isProfitableToConv3Addr(unsigned RegA);
107 bool isProfitableToConv3Addr(unsigned RegA, unsigned RegB);
108108
109109 bool ConvertInstTo3Addr(MachineBasicBlock::iterator &mi,
110110 MachineBasicBlock::iterator &nmi,
123123 MachineBasicBlock::iterator &nmi,
124124 MachineFunction::iterator &mbbi,
125125 unsigned SrcIdx, unsigned DstIdx,
126 unsigned Dist);
126 unsigned Dist,
127 SmallPtrSet &Processed);
128
129 void ScanUses(unsigned DstReg, MachineBasicBlock *MBB,
130 SmallPtrSet &Processed);
127131
128132 void ProcessCopy(MachineInstr *MI, MachineBasicBlock *MBB,
129133 SmallPtrSet &Processed);
614618 /// isProfitableToConv3Addr - Return true if it is profitable to convert the
615619 /// given 2-address instruction to a 3-address one.
616620 bool
617 TwoAddressInstructionPass::isProfitableToConv3Addr(unsigned RegA) {
621 TwoAddressInstructionPass::isProfitableToConv3Addr(unsigned RegA,unsigned RegB){
618622 // Look for situations like this:
619623 // %reg1024 = MOV r1
620624 // %reg1025 = MOV r0
621625 // %reg1026 = ADD %reg1024, %reg1025
622626 // r2 = MOV %reg1026
623627 // Turn ADD into a 3-address instruction to avoid a copy.
624 unsigned FromRegA = getMappedReg(RegA, SrcRegMap);
628 unsigned FromRegB = getMappedReg(RegB, SrcRegMap);
629 if (!FromRegB)
630 return false;
625631 unsigned ToRegA = getMappedReg(RegA, DstRegMap);
626 return (FromRegA && ToRegA && !regsAreCompatible(FromRegA, ToRegA, TRI));
632 return (ToRegA && !regsAreCompatible(FromRegB, ToRegA, TRI));
627633 }
628634
629635 /// ConvertInstTo3Addr - Convert the specified two-address instruction into a
661667 }
662668
663669 return false;
670 }
671
672 /// ScanUses - Scan forward recursively for only uses, update maps if the use
673 /// is a copy or a two-address instruction.
674 void
675 TwoAddressInstructionPass::ScanUses(unsigned DstReg, MachineBasicBlock *MBB,
676 SmallPtrSet &Processed) {
677 SmallVector VirtRegPairs;
678 bool IsDstPhys;
679 bool IsCopy = false;
680 unsigned NewReg = 0;
681 unsigned Reg = DstReg;
682 while (MachineInstr *UseMI = findOnlyInterestingUse(Reg, MBB, MRI, TII,IsCopy,
683 NewReg, IsDstPhys)) {
684 if (IsCopy && !Processed.insert(UseMI))
685 break;
686
687 DenseMap::iterator DI = DistanceMap.find(UseMI);
688 if (DI != DistanceMap.end())
689 // Earlier in the same MBB.Reached via a back edge.
690 break;
691
692 if (IsDstPhys) {
693 VirtRegPairs.push_back(NewReg);
694 break;
695 }
696 bool isNew = SrcRegMap.insert(std::make_pair(NewReg, Reg)).second;
697 if (!isNew)
698 assert(SrcRegMap[NewReg] == Reg && "Can't map to two src registers!");
699 VirtRegPairs.push_back(NewReg);
700 Reg = NewReg;
701 }
702
703 if (!VirtRegPairs.empty()) {
704 unsigned ToReg = VirtRegPairs.back();
705 VirtRegPairs.pop_back();
706 while (!VirtRegPairs.empty()) {
707 unsigned FromReg = VirtRegPairs.back();
708 VirtRegPairs.pop_back();
709 bool isNew = DstRegMap.insert(std::make_pair(FromReg, ToReg)).second;
710 if (!isNew)
711 assert(DstRegMap[FromReg] == ToReg &&"Can't map to two dst registers!");
712 ToReg = FromReg;
713 }
714 bool isNew = DstRegMap.insert(std::make_pair(DstReg, ToReg)).second;
715 if (!isNew)
716 assert(DstRegMap[DstReg] == ToReg && "Can't map to two dst registers!");
717 }
664718 }
665719
666720 /// ProcessCopy - If the specified instruction is not yet processed, process it
694748 assert(SrcRegMap[DstReg] == SrcReg &&
695749 "Can't map to two src physical registers!");
696750
697 SmallVector VirtRegPairs;
698 bool IsCopy = false;
699 unsigned NewReg = 0;
700 while (MachineInstr *UseMI = findOnlyInterestingUse(DstReg, MBB, MRI,TII,
701 IsCopy, NewReg, IsDstPhys)) {
702 if (IsCopy) {
703 if (!Processed.insert(UseMI))
704 break;
705 }
706
707 DenseMap::iterator DI = DistanceMap.find(UseMI);
708 if (DI != DistanceMap.end())
709 // Earlier in the same MBB.Reached via a back edge.
710 break;
711
712 if (IsDstPhys) {
713 VirtRegPairs.push_back(NewReg);
714 break;
715 }
716 bool isNew = SrcRegMap.insert(std::make_pair(NewReg, DstReg)).second;
717 if (!isNew)
718 assert(SrcRegMap[NewReg] == DstReg &&
719 "Can't map to two src physical registers!");
720 VirtRegPairs.push_back(NewReg);
721 DstReg = NewReg;
722 }
723
724 if (!VirtRegPairs.empty()) {
725 unsigned ToReg = VirtRegPairs.back();
726 VirtRegPairs.pop_back();
727 while (!VirtRegPairs.empty()) {
728 unsigned FromReg = VirtRegPairs.back();
729 VirtRegPairs.pop_back();
730 bool isNew = DstRegMap.insert(std::make_pair(FromReg, ToReg)).second;
731 if (!isNew)
732 assert(DstRegMap[FromReg] == ToReg &&
733 "Can't map to two dst physical registers!");
734 ToReg = FromReg;
735 }
736 }
751 ScanUses(DstReg, MBB, Processed);
737752 }
738753
739754 Processed.insert(MI);
755 return;
740756 }
741757
742758 /// isSafeToDelete - If the specified instruction does not produce any side
835851 TryInstructionTransform(MachineBasicBlock::iterator &mi,
836852 MachineBasicBlock::iterator &nmi,
837853 MachineFunction::iterator &mbbi,
838 unsigned SrcIdx, unsigned DstIdx, unsigned Dist) {
854 unsigned SrcIdx, unsigned DstIdx, unsigned Dist,
855 SmallPtrSet &Processed) {
839856 const TargetInstrDesc &TID = mi->getDesc();
840857 unsigned regA = mi->getOperand(DstIdx).getReg();
841858 unsigned regB = mi->getOperand(SrcIdx).getReg();
886903 return false;
887904 }
888905
906 if (TargetRegisterInfo::isVirtualRegister(regA))
907 ScanUses(regA, &*mbbi, Processed);
908
889909 if (TID.isConvertibleTo3Addr()) {
890910 // This instruction is potentially convertible to a true
891911 // three-address instruction. Check if it is profitable.
892 if (!regBKilled || isProfitableToConv3Addr(regA)) {
912 if (!regBKilled || isProfitableToConv3Addr(regA, regB)) {
893913 // Try to convert it.
894914 if (ConvertInstTo3Addr(mi, nmi, mbbi, regA, regB, Dist)) {
895915 ++NumConvertedTo3Addr;
950970 MachineBasicBlock::iterator NewMI = NewMIs[1];
951971 bool TransformSuccess =
952972 TryInstructionTransform(NewMI, mi, mbbi,
953 NewSrcIdx, NewDstIdx, Dist);
973 NewSrcIdx, NewDstIdx, Dist, Processed);
954974 if (TransformSuccess ||
955975 NewMIs[1]->getOperand(NewSrcIdx).isKill()) {
956976 // Success, or at least we made an improvement. Keep the unfolded
10991119 mi->getOperand(DstIdx).getReg())
11001120 break; // Done with this instruction.
11011121
1102 if (TryInstructionTransform(mi, nmi, mbbi, SrcIdx, DstIdx, Dist))
1122 if (TryInstructionTransform(mi, nmi, mbbi, SrcIdx, DstIdx, Dist,
1123 Processed))
11031124 break; // The tied operands have been eliminated.
11041125 }
11051126
0 ; RUN: llc < %s -march=x86-64 -stats |& \
1 ; RUN: grep {6 .*Number of machine instrs printed}
1 ; RUN: grep {5 .*Number of machine instrs printed}
22
33 ;; Integer absolute value, should produce something at least as good as:
4 ;; movl %edi, %eax
5 ;; sarl $31, %eax
6 ;; addl %eax, %edi
7 ;; xorl %eax, %edi
8 ;; movl %edi, %eax
4 ;; movl %edi, %ecx
5 ;; sarl $31, %ecx
6 ;; leal (%rdi,%rcx), %eax
7 ;; xorl %ecx, %eax
98 ;; ret
109 define i32 @test(i32 %a) nounwind {
1110 %tmp1neg = sub i32 0, %a
3333 %add5 = add i32 %add3, %d
3434 ret i32 %add5
3535 }
36
37 ; rdar://9002648
38 define i64 @test3(i64 %x) nounwind readnone ssp {
39 entry:
40 ; CHECK: test3:
41 ; CHECK: leaq (%rdi,%rdi), %rax
42 ; CHECK-NOT: addq
43 ; CHECK-NEXT: ret
44 %0 = shl i64 %x, 1
45 ret i64 %0
46 }