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Merging r315485: ------------------------------------------------------------------------ r315485 | spatel | 2017-10-11 11:24:21 -0700 (Wed, 11 Oct 2017) | 7 lines [x86] avoid infinite loop from SoftenFloatOperand (PR34866) Legalization of fp128 assumes things that we should have asserts for, so that's another potential improvement. Differential Revision: https://reviews.llvm.org/D38771 ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_50@316607 91177308-0d34-0410-b5e6-96231b3b80d8 Tom Stellard 1 year, 9 months ago
2 changed file(s) with 70 addition(s) and 0 deletion(s). Raw diff Collapse all Expand all
3474434744 if (!OpVT.isScalarInteger() || OpSize < 128 || isNullConstant(Y))
3474534745 return SDValue();
3474634746
34747 // Bail out if we know that this is not really just an oversized integer.
34748 if (peekThroughBitcasts(X).getValueType() == MVT::f128 ||
34749 peekThroughBitcasts(Y).getValueType() == MVT::f128)
34750 return SDValue();
34751
3474734752 // TODO: Use PXOR + PTEST for SSE4.1 or later?
3474834753 // TODO: Add support for AVX-512.
3474934754 EVT VT = SetCC->getValueType(0);
0 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
1 ; RUN: llc < %s -O2 -mtriple=x86_64-linux-android -mattr=+mmx | FileCheck %s --check-prefix=X64
12 ; RUN: llc < %s -O2 -mtriple=x86_64-linux-gnu -mattr=+mmx | FileCheck %s --check-prefix=X64
3 ; RUN: llc < %s -O2 -mtriple=x86_64-linux-gnu -mattr=-mmx | FileCheck %s --check-prefix=X64_NO_MMX
24 ; RUN: llc < %s -O2 -mtriple=i686-linux-gnu -mattr=+mmx | FileCheck %s --check-prefix=X32
35
46 ; Check soft floating point conversion function calls.
358360 ; X64: retq
359361 }
360362
363 define i1 @PR34866(i128 %x) {
364 ; X64-LABEL: PR34866:
365 ; X64: # BB#0:
366 ; X64-NEXT: movaps {{.*}}(%rip), %xmm0
367 ; X64-NEXT: movaps %xmm0, -{{[0-9]+}}(%rsp)
368 ; X64-NEXT: xorq -{{[0-9]+}}(%rsp), %rsi
369 ; X64-NEXT: xorq -{{[0-9]+}}(%rsp), %rdi
370 ; X64-NEXT: orq %rsi, %rdi
371 ; X64-NEXT: sete %al
372 ; X64-NEXT: retq
373 ;
374 ; X64_NO_MMX-LABEL: PR34866:
375 ; X64_NO_MMX: # BB#0:
376 ; X64_NO_MMX-NEXT: orq %rsi, %rdi
377 ; X64_NO_MMX-NEXT: sete %al
378 ; X64_NO_MMX-NEXT: retq
379 ;
380 ; X32-LABEL: PR34866:
381 ; X32: # BB#0:
382 ; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
383 ; X32-NEXT: movl {{[0-9]+}}(%esp), %ecx
384 ; X32-NEXT: orl {{[0-9]+}}(%esp), %ecx
385 ; X32-NEXT: orl {{[0-9]+}}(%esp), %eax
386 ; X32-NEXT: orl %ecx, %eax
387 ; X32-NEXT: sete %al
388 ; X32-NEXT: retl
389 %bc_mmx = bitcast fp128 0xL00000000000000000000000000000000 to i128
390 %cmp = icmp eq i128 %bc_mmx, %x
391 ret i1 %cmp
392 }
393
394 define i1 @PR34866_commute(i128 %x) {
395 ; X64-LABEL: PR34866_commute:
396 ; X64: # BB#0:
397 ; X64-NEXT: movaps {{.*}}(%rip), %xmm0
398 ; X64-NEXT: movaps %xmm0, -{{[0-9]+}}(%rsp)
399 ; X64-NEXT: xorq -{{[0-9]+}}(%rsp), %rsi
400 ; X64-NEXT: xorq -{{[0-9]+}}(%rsp), %rdi
401 ; X64-NEXT: orq %rsi, %rdi
402 ; X64-NEXT: sete %al
403 ; X64-NEXT: retq
404 ;
405 ; X64_NO_MMX-LABEL: PR34866_commute:
406 ; X64_NO_MMX: # BB#0:
407 ; X64_NO_MMX-NEXT: orq %rsi, %rdi
408 ; X64_NO_MMX-NEXT: sete %al
409 ; X64_NO_MMX-NEXT: retq
410 ;
411 ; X32-LABEL: PR34866_commute:
412 ; X32: # BB#0:
413 ; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
414 ; X32-NEXT: movl {{[0-9]+}}(%esp), %ecx
415 ; X32-NEXT: orl {{[0-9]+}}(%esp), %ecx
416 ; X32-NEXT: orl {{[0-9]+}}(%esp), %eax
417 ; X32-NEXT: orl %ecx, %eax
418 ; X32-NEXT: sete %al
419 ; X32-NEXT: retl
420 %bc_mmx = bitcast fp128 0xL00000000000000000000000000000000 to i128
421 %cmp = icmp eq i128 %x, %bc_mmx
422 ret i1 %cmp
423 }
424
425
361426 declare double @copysign(double, double) #1
362427
363428 attributes #2 = { nounwind readnone }