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Merging r354672: ------------------------------------------------------------------------ r354672 | petarj | 2019-02-22 06:53:58 -0800 (Fri, 22 Feb 2019) | 13 lines [mips][micromips] fix filling delay slots for PseudoIndirectBranch_MM Filling a delay slot in 32bit jump instructions with a 16bit instruction can cause issues. According to the documentation such an operation is unpredictable. This patch adds opcode Mips::PseudoIndirectBranch_MM alongside Mips::PseudoIndirectBranch and other instructions that are expanded to jr instruction and do not allow a 16bit instruction in their delay slots. Patch by Mirko Brkusanin. Differential Revision: https://reviews.llvm.org/D58507 ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_80@358920 91177308-0d34-0410-b5e6-96231b3b80d8 Tom Stellard 4 months ago
2 changed file(s) with 69 addition(s) and 0 deletion(s). Raw diff Collapse all Expand all
725725 // but we don't have enough information to make that decision.
726726 if (InMicroMipsMode && TII->getInstSizeInBytes(*CurrI) == 2 &&
727727 (Opcode == Mips::JR || Opcode == Mips::PseudoIndirectBranch ||
728 Opcode == Mips::PseudoIndirectBranch_MM ||
728729 Opcode == Mips::PseudoReturn || Opcode == Mips::TAILCALL))
729730 continue;
730731 // Instructions LWP/SWP and MOVEP should not be in a delay slot as that
0 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
1 ; RUN: llc -mtriple=mipsel-linux-gnu -mattr=+micromips -relocation-model=pic < %s | FileCheck %s
2
3 ; Test that the delay slot filler correctly handles indirect branches for
4 ; microMIPS in regard to incorrectly using 16bit instructions in delay slots of
5 ; 32bit instructions.
6
7 define i32 @test(i32 signext %x, i32 signext %c) {
8 ; CHECK-LABEL: test:
9 ; CHECK: # %bb.0: # %entry
10 ; CHECK-NEXT: lui $2, %hi(_gp_disp)
11 ; CHECK-NEXT: addiu $2, $2, %lo(_gp_disp)
12 ; CHECK-NEXT: addiur2 $5, $5, -1
13 ; CHECK-NEXT: sltiu $1, $5, 4
14 ; CHECK-NEXT: beqz $1, $BB0_3
15 ; CHECK-NEXT: addu $3, $2, $25
16 ; CHECK-NEXT: $BB0_1: # %entry
17 ; CHECK-NEXT: li16 $2, 0
18 ; CHECK-NEXT: sll16 $5, $5, 2
19 ; CHECK-NEXT: lw $6, %got($JTI0_0)($3)
20 ; CHECK-NEXT: addu16 $5, $5, $6
21 ; CHECK-NEXT: lw $5, %lo($JTI0_0)($5)
22 ; CHECK-NEXT: addu16 $3, $5, $3
23 ; CHECK-NEXT: jr $3
24 ; CHECK-NEXT: nop
25 ; CHECK-NEXT: $BB0_2: # %sw.bb2
26 ; CHECK-NEXT: addiur2 $2, $4, 1
27 ; CHECK-NEXT: jrc $ra
28 ; CHECK-NEXT: $BB0_3:
29 ; CHECK-NEXT: move $2, $4
30 ; CHECK-NEXT: jrc $ra
31 ; CHECK-NEXT: $BB0_4: # %sw.bb3
32 ; CHECK-NEXT: addius5 $4, 2
33 ; CHECK-NEXT: move $2, $4
34 ; CHECK-NEXT: jrc $ra
35 ; CHECK-NEXT: $BB0_5: # %sw.bb5
36 ; CHECK-NEXT: addius5 $4, 3
37 ; CHECK-NEXT: move $2, $4
38 ; CHECK-NEXT: $BB0_6: # %for.cond.cleanup
39 ; CHECK-NEXT: jrc $ra
40 entry:
41 switch i32 %c, label %sw.epilog [
42 i32 4, label %sw.bb5
43 i32 1, label %for.cond.cleanup
44 i32 2, label %sw.bb2
45 i32 3, label %sw.bb3
46 ]
47
48 sw.bb2:
49 %add = add nsw i32 %x, 1
50 br label %sw.epilog
51
52 sw.bb3:
53 %add4 = add nsw i32 %x, 2
54 br label %sw.epilog
55
56 sw.bb5:
57 %add6 = add nsw i32 %x, 3
58 br label %sw.epilog
59
60 sw.epilog:
61 %a.0 = phi i32 [ %add6, %sw.bb5 ], [ %add4, %sw.bb3 ], [ %add, %sw.bb2 ], [ %x, %entry ]
62 br label %for.cond.cleanup
63
64 for.cond.cleanup:
65 %a.028 = phi i32 [ %a.0, %sw.epilog ], [ 0, %entry ]
66 ret i32 %a.028
67 }