llvm.org GIT mirror llvm / ef61ed3
TableGen no longer emit CopyFromReg nodes for implicit results in physical registers. The scheduler is now responsible for emitting them. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@41781 91177308-0d34-0410-b5e6-96231b3b80d8 Evan Cheng 13 years ago
3 changed file(s) with 17 addition(s) and 90 deletion(s). Raw diff Collapse all Expand all
10621062 break;
10631063 }
10641064
1065 case ISD::MUL: {
1066 if (NVT == MVT::i8) {
1067 SDOperand N0 = Node->getOperand(0);
1068 SDOperand N1 = Node->getOperand(1);
1069 SDOperand Tmp0, Tmp1, Tmp2, Tmp3;
1070 bool foldedLoad = TryFoldLoad(N, N1, Tmp0, Tmp1, Tmp2, Tmp3);
1071 if (!foldedLoad) {
1072 foldedLoad = TryFoldLoad(N, N0, Tmp0, Tmp1, Tmp2, Tmp3);
1073 if (foldedLoad)
1074 std::swap(N0, N1);
1075 }
1076
1077 SDNode *ResNode;
1078 if (foldedLoad) {
1079 SDOperand Chain = N1.getOperand(0);
1080 AddToISelQueue(N0);
1081 AddToISelQueue(Chain);
1082 AddToISelQueue(Tmp0);
1083 AddToISelQueue(Tmp1);
1084 AddToISelQueue(Tmp2);
1085 AddToISelQueue(Tmp3);
1086 SDOperand InFlag(0, 0);
1087 Chain = CurDAG->getCopyToReg(Chain, X86::AL, N0, InFlag);
1088 InFlag = Chain.getValue(1);
1089 SDOperand Ops[] = { Tmp0, Tmp1, Tmp2, Tmp3, Chain, InFlag };
1090 ResNode = CurDAG->getTargetNode(X86::MUL8m, MVT::i8, MVT::i8,
1091 MVT::Other, Ops, 6);
1092 ReplaceUses(N1.getValue(1), SDOperand(ResNode, 2));
1093 } else {
1094 SDOperand Chain = CurDAG->getEntryNode();
1095 AddToISelQueue(N0);
1096 AddToISelQueue(N1);
1097 SDOperand InFlag(0, 0);
1098 InFlag = CurDAG->getCopyToReg(Chain, X86::AL, N0, InFlag).getValue(1);
1099 ResNode = CurDAG->getTargetNode(X86::MUL8r, MVT::i8, MVT::i8,
1100 N1, InFlag);
1101 }
1102
1103 ReplaceUses(N.getValue(0), SDOperand(ResNode, 0));
1104 return NULL;
1105 }
1106 break;
1107 }
1108
11091065 case ISD::MULHU:
11101066 case ISD::MULHS: {
11111067 if (Opcode == ISD::MULHU)
551551 // FIXME: Used for 8-bit mul, ignore result upper 8 bits.
552552 // This probably ought to be moved to a def : Pat<> if the
553553 // syntax can be accepted.
554 []>,
554 [(set AL, (mul AL, GR8:$src))]>,
555555 Imp<[AL],[AL,AH]>; // AL,AH = AL*GR8
556556 def MUL16r : I<0xF7, MRM4r, (outs), (ins GR16:$src), "mul{w}\t$src", []>,
557557 Imp<[AX],[AX,DX]>, OpSize; // AX,DX = AX*GR16
562562 // FIXME: Used for 8-bit mul, ignore result upper 8 bits.
563563 // This probably ought to be moved to a def : Pat<> if the
564564 // syntax can be accepted.
565 []>,
565 [(set AL, (mul AL, (loadi8 addr:$src)))]>,
566566 Imp<[AL],[AL,AH]>; // AL,AH = AL*[mem8]
567567 def MUL16m : I<0xF7, MRM4m, (outs), (ins i16mem:$src),
568568 "mul{w}\t$src", []>, Imp<[AX],[AX,DX]>,
27672767 PatternHasProperty(Pattern, SDNPOptInFlag, ISE);
27682768 bool NodeHasInFlag = isRoot &&
27692769 PatternHasProperty(Pattern, SDNPInFlag, ISE);
2770 bool NodeHasOutFlag = HasImpResults || (isRoot &&
2771 PatternHasProperty(Pattern, SDNPOutFlag, ISE));
2770 bool NodeHasOutFlag = isRoot &&
2771 PatternHasProperty(Pattern, SDNPOutFlag, ISE);
27722772 bool NodeHasChain = InstPatNode &&
27732773 PatternHasProperty(InstPatNode, SDNPHasChain, ISE);
27742774 bool InputHasChain = isRoot &&
28682868
28692869 unsigned ResNo = TmpNo++;
28702870 if (!isRoot || InputHasChain || NodeHasChain || NodeHasOutFlag ||
2871 NodeHasOptInFlag) {
2871 NodeHasOptInFlag || HasImpResults) {
28722872 std::string Code;
28732873 std::string Code2;
28742874 std::string NodeName;
28932893 if (NumResults > 0 && N->getTypeNum(0) != MVT::isVoid) {
28942894 Code += ", VT" + utostr(VTNo);
28952895 emitVT(getEnumName(N->getTypeNum(0)));
2896 }
2897 // Add types for implicit results in physical registers, scheduler will
2898 // care of adding copyfromreg nodes.
2899 if (HasImpResults) {
2900 for (unsigned i = 0, e = Inst.getNumImpResults(); i < e; i++) {
2901 Record *RR = Inst.getImpResult(i);
2902 if (RR->isSubClassOf("Register")) {
2903 MVT::ValueType RVT = getRegisterValueType(RR, CGT);
2904 Code += ", " + getEnumName(RVT);
2905 ++NumResults;
2906 }
2907 }
28962908 }
28972909 if (NodeHasChain)
28982910 Code += ", MVT::Other";
29963008 } else
29973009 emitCode("InFlag = SDOperand(ResNode, " +
29983010 utostr(NumResults + (unsigned)NodeHasChain) + ");");
2999 }
3000
3001 if (HasImpResults && EmitCopyFromRegs(N, ResNodeDecled, ChainEmitted)) {
3002 emitCode("ReplaceUses(SDOperand(N.Val, 0), SDOperand(ResNode, 0));");
3003 NumResults = 1;
30043011 }
30053012
30063013 if (FoldedChains.size() > 0) {
32003207 ".getOperand(" + utostr(OpNo) + ");");
32013208 emitCode("AddToISelQueue(InFlag);");
32023209 }
3203 }
3204
3205 /// EmitCopyFromRegs - Emit code to copy result to physical registers
3206 /// as specified by the instruction. It returns true if any copy is
3207 /// emitted.
3208 bool EmitCopyFromRegs(TreePatternNode *N, bool &ResNodeDecled,
3209 bool &ChainEmitted) {
3210 bool RetVal = false;
3211 Record *Op = N->getOperator();
3212 if (Op->isSubClassOf("Instruction")) {
3213 const DAGInstruction &Inst = ISE.getInstruction(Op);
3214 const CodeGenTarget &CGT = ISE.getTargetInfo();
3215 unsigned NumImpResults = Inst.getNumImpResults();
3216 for (unsigned i = 0; i < NumImpResults; i++) {
3217 Record *RR = Inst.getImpResult(i);
3218 if (RR->isSubClassOf("Register")) {
3219 MVT::ValueType RVT = getRegisterValueType(RR, CGT);
3220 if (RVT != MVT::Flag) {
3221 if (!ChainEmitted) {
3222 emitCode("SDOperand Chain = CurDAG->getEntryNode();");
3223 ChainEmitted = true;
3224 ChainName = "Chain";
3225 }
3226 std::string Decl = (!ResNodeDecled) ? "SDNode *" : "";
3227 emitCode(Decl + "ResNode = CurDAG->getCopyFromReg(" + ChainName +
3228 ", " + ISE.getQualifiedName(RR) + ", " + getEnumName(RVT) +
3229 ", InFlag).Val;");
3230 ResNodeDecled = true;
3231 emitCode(ChainName + " = SDOperand(ResNode, 1);");
3232 emitCode("InFlag = SDOperand(ResNode, 2);");
3233 RetVal = true;
3234 }
3235 }
3236 }
3237 }
3238 return RetVal;
32393210 }
32403211 };
32413212