llvm.org GIT mirror llvm / ef572e3
[ARM] Add support for MVFR2 which is new in ARMv8 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@194416 91177308-0d34-0410-b5e6-96231b3b80d8 Artyom Skrobov 6 years ago
5 changed file(s) with 19 addition(s) and 0 deletion(s). Raw diff Collapse all Expand all
15451545 "vmrs", "\t$Rt, mvfr0", []>;
15461546 def VMRS_MVFR1 : MovFromVFP<0b0110 /* mvfr1 */, (outs GPR:$Rt), (ins),
15471547 "vmrs", "\t$Rt, mvfr1", []>;
1548 def VMRS_MVFR2 : MovFromVFP<0b0101 /* mvfr2 */, (outs GPR:$Rt), (ins),
1549 "vmrs", "\t$Rt, mvfr2", []>, Requires<[HasFPARMv8]>;
15481550 def VMRS_FPINST : MovFromVFP<0b1001 /* fpinst */, (outs GPR:$Rt), (ins),
15491551 "vmrs", "\t$Rt, fpinst", []>;
15501552 def VMRS_FPINST2 : MovFromVFP<0b1010 /* fpinst2 */, (outs GPR:$Rt), (ins),
171171
172172 // Special Registers - only available in privileged mode.
173173 def FPSID : ARMReg<0, "fpsid">;
174 def MVFR2 : ARMReg<5, "mvfr2">;
174175 def MVFR1 : ARMReg<6, "mvfr1">;
175176 def MVFR0 : ARMReg<7, "mvfr0">;
176177 def FPEXC : ARMReg<8, "fpexc">;
121121 @ CHECK: vrintm.f64 d3, d4 @ encoding: [0x44,0x3b,0xbb,0xfe]
122122 vrintm.f32 s12, s1
123123 @ CHECK: vrintm.f32 s12, s1 @ encoding: [0x60,0x6a,0xbb,0xfe]
124
125 @ MVFR2
126
127 vmrs sp, mvfr2
128 @ CHECK: vmrs sp, mvfr2 @ encoding: [0x10,0xda,0xf5,0xee]
152152
153153 0x60 0x6a 0xbb 0xfe
154154 # CHECK: vrintm.f32 s12, s1
155
156
157 0x10 0xa 0xf5 0xee
158 # CHECK: vmrs r0, mvfr2
159
1717 [0x41 0x2b 0xb3 0xbe]
1818 # CHECK: invalid instruction encoding
1919 # CHECK-NEXT: [0x41 0x2b 0xb3 0xbe]
20
21 # Would be vmrs r0, mvfr2
22 [0x10 0xa 0xf5 0xee]
23 # CHECK: invalid instruction encoding
24 # CHECK-NEXT: [0x10 0xa 0xf5 0xee]
25